CN104218003B - 具有缓冲材料和加强层的半导体器件 - Google Patents
具有缓冲材料和加强层的半导体器件 Download PDFInfo
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Abstract
所描述的半导体器件包括:具有在衬底(例如半导体晶片)上的多个堆叠的裸片的半导体器件。在一个或多个实施方式中,采用根据本公开的示例技术的晶片级封装器件包括:晶片中形成有镀金属和通孔以及晶片的表面上具有氧化层的超薄半导体晶片,放置在该半导体晶片上的集成电路芯片,介于该集成电路芯片和该半导体晶片之间的底部填充层,形成在该半导体晶片、该底部填充层和该集成电路芯片的至少一侧上的缓冲材料,放置在该缓冲层和该集成电路芯片上的粘结层以及放置在该粘结层上的加强层。然后,可以将半导体器件分割成单个半导体芯片封装。
Description
相关申请的交叉引用
本申请要求2013年4月12日提交的题目为“SEMICONDUCTOR DEVICE HAVING ABUFFER MATERIAL AND STIFFENER”的美国临时专利申请No.61/811,352在35U.S.C.§119(e)下的优先权。在此援引美国临时专利申请No.61/811352的全部内容作为参考。
背景技术
消费类电子设备,特别是诸如智能手机、平板电脑等移动电子设备,日趋采用更小、更紧凑的部件以给其用户提供期望的特性。这些设备通常采用三维集成电路器件(3DIC)。三维集成电路器件是采用两层或更多层有源电子部件的半导体器件。硅穿孔(TSV)互连在器件的不同层(例如,不同衬底)上的电子部件,使得器件可以竖直及水平地集成。因此,与传统的二维集成电路器件相比,三维集成电路器件可以在更小、更紧凑的占用面积中提供更多的功能。
发明内容
所描述的半导体器件包括如下半导体器件,其具有在包括去除了划片道上的氧化物的衬底(例如半导体晶片)上的多个堆叠的裸片、介于该半导体晶片和粘结层之间的缓冲材料并且包括具有与该缓冲材料的热膨胀系数(CTE)匹配的热膨胀系数的底部填充层。在一个或多个实施方式中,采用根据本公开的示例技术的晶片级封装器件包括:晶片中形成有镀金属(metallization)和通孔以及晶片的表面上具有氧化层的超薄半导体晶片,放置在该半导体晶片上的集成电路芯片,介于该集成电路芯片和该半导体晶片之间的底部填充层,形成在该半导体晶片、该底部填充层和该集成电路芯片的至少一侧上的缓冲材料,放置在该缓冲层和该集成电路芯片上的粘结层以及放置在该粘结层上的加强层。然后,可以将半导体器件分割成单个半导体芯片封装。
提供了本发明内容来以简化的形式介绍以下在具体实施方式部分中会进一步描述的概念的选择。本发明内容既不旨在确定所要求的主题的关键特征或者必要特征,也不旨在用于辅助确定所要求保护的主题的范围。
附图说明
参照附图描述具体实施方式部分。在说明书和附图中的不同实例中使用相同的附图标记可以表示相似或相同的项。
图1是示出根据本公开的示例实施方式的晶片级半导体器件(例如,器件分割前)的图解部分截面图。
图2是示出用于制造诸如图1中所示的器件的半导体器件的示例实施方式的方法的流程图。
图3A到3E是示出根据图2中示出的示例实施方式的方法制造诸如图1中所示的半导体器件的晶片级封装的半导体器件的图解部分截面图。
具体实施方式
综述
通常使用晶片上裸片技术制造三维集成电路器件,其中电子部件(例如,电路)首先制造在两个或更多个半导体晶片上。然后,将单个裸片对准、附接到半导体晶片并进行分割,以提供单个器件。硅穿孔(TSV)可在附接之前形成在晶片中,或者可在附接之后形成在晶片堆叠体中。然而,制造三维集成电路器件期间可发生半导体晶片的晶片翘曲和弯曲。这种晶片翘曲可妨碍有效的晶片处理且导致器件中的机械失效,例如导致器件中的层的脱层。而且,包括具有薄硅的硅穿孔(TSV)、使用塑封材料接合的芯片-到-晶片的器件封装高度敏感于热机械失效。此外,在分割处理期间,半导体晶片可被分割成单个裸片并可在背面切片和沿着裸片边缘裂开。进一步的,具有不同热膨胀系数的材料可导致器件失效,例如,芯片-到-晶片焊点裂开。这些问题增加了器件的成本并降低器件的产量。
因此,所描述的技术用于制造如下半导体器件,其具有在包括去除了划片道上的氧化物的衬底(例如半导体晶片)上的多个堆叠的裸片、介于该半导体晶片和粘结层之间的缓冲材料,并且包括具有与该缓冲材料的热膨胀系数(CTE)匹配的热膨胀系数的底部填充层。在一个或多个实施方式中,采用根据本公开的示例技术的晶片级封装器件包括:晶片中形成有镀金属和通孔以及晶片的表面上具有氧化层的超薄半导体晶片;放置在该半导体晶片上的集成电路芯片;介于该集成电路芯片和该半导体晶片之间的底部填充层;形成在该半导体晶片、该底部填充层和该集成电路芯片的至少一侧上的缓冲材料;放置在该缓冲层和该集成电路芯片上的粘结层;以及放置在该粘结层上的加强层。
在实施方式中,根据本公开的示例技术包括:在加工过的半导体晶片上放置集成电路芯片,其中该半导体晶片包括至少一个通孔和至少一个介电层;在该集成电路芯片和该半导体晶片之间形成底胶材料层;在该底胶材料层的一部分、该介电层、该半导体晶片上以及邻近于该集成电路芯片的至少一侧形成缓冲材料层;在该缓冲材料层和该集成电路芯片的一部分上形成粘结层;在该粘结层上放置加强层;以及在该半导体晶片上形成至少一个焊料块。然后,可以将该加工过的半导体晶片分割成单个半导体器件。
示例实施方式
图1示出了根据本公开的示例实施方式的半导体器件100。如所示,示出了在分割之前的晶片级半导体器件100。该半导体器件100可包括半导体晶片102。该半导体晶片102包括一个或多个集成电路(未示出),其形成在该半导体晶片102中。该半导体晶片102包括第一(例如顶或前)表面和第二(例如底或背)表面。集成电路形成(例如,制造)在该半导体晶片102的第一表面附近。该半导体晶片102的该第二表面可被配置为具有形成于其上或附接于其上的至少一个焊料块120。可以预见的是,可以对该半导体晶片102的第一和/或第二表面平坦化或者可以不对其进行平坦化。
该半导体晶片102包括基材,该基材用于通过诸如光刻、离子注入、沉积、蚀刻等各种制造技术来形成一个或多个集成电路器件。可以以各种方式配置该半导体晶片102。例如,该半导体晶片102可以包括n-型硅晶片或者p-型硅晶片。在一个实施方式中,该半导体晶片102可以包括配置为提供n-型电荷载流子元素的V族元素(例如磷、砷、锑等)。在另一实施方式中,该半导体晶片102可以包括配置为提供p-型电荷载流子元素的IIIA族元素(例如硼等)。在一些实施例中,该半导体晶片102包括具有小于约100μm厚度的超薄半导体晶片。进一步,可以以各种方式配置该集成电路。例如,该集成电路可以包括数字集成电路、模拟集成电路、混合信号电路等。在一个或多个实施方式中,该集成电路可以包括数字逻辑器件、模拟器件(例如,放大器等)、其组合等。如上所述,该集成电路可以利用各种制造技术制造。例如,该集成电路可以通过互补金属氧化物半导体(CMOS)技术、双极型半导体技术等制造。
如图1中所示,该半导体器件100还包括形成在该半导体晶片102中的至少一个硅穿孔104。每个硅穿孔104(“TSV”)在第一侧上的触垫106到第二侧上的触垫106之间延伸穿过半导体晶片102。如图1中所示,该硅穿孔104包括为在该半导体晶片102的该第一侧和该第二侧之间提供电互连的导电材料。在一个或多个实施方式中,包括在该硅穿孔104中的该导电材料可包括金属材料(例如铜、铝等)。在实施例中,触垫106可包括配置为在两个元件(例如焊料块、再分布层等)之间提供电互连的金属垫或表面。在某些实施方式中,该触垫106没有直接放置在该硅穿孔104上。在这些实施方式中,该触垫106和硅穿孔104彼此偏移并使用背面再分布层(BRDL)电耦接。
此外,该半导体晶片102包括介电层122。在某些实施方式中,该介电层122包括氧化层。该介电层122可被放置在该半导体晶片102的至少一侧上而不覆盖半导体上放置划片道124的部分。划片道124可包括一个区域,在该区域处晶片级封装的一部分(例如介于形成在晶片中的集成电路之间)被切掉以便于分割该芯片封装。在实施例中,该划片道124放置在该半导体晶片102的边缘,在该边缘处半导体器件100将被分割成单个芯片封装。通过去除该(多个)划片道124上的介电层122和/或不在划片道124上形成介电层122,在分割处理期间的晶片碎裂和潜在的氧化层脱层被阻止。
该半导体器件100包括附接到该半导体晶片102的一侧上的集成电路芯片108。在实施例中,该集成电路芯片108包括用作该集成电路芯片108和该半导体晶片102的电互连件之间的电连接件的至少一个焊料块110(例如芯片-到-晶片焊球)。在其它实施例中,该集成电路芯片108可使用其它方法附接到该半导体晶片102,诸如使用粘结剂。另外,该集成电路芯片108可被电连接到该半导体晶片102,例如使用接合线。在一些实施方式中,该集成电路芯片108可包括倒装芯片,其中焊料块被沉积在该集成电路芯片108上并且该集成电路芯片108被翻转以使其顶面朝下并与该半导体晶片102接触。
该半导体器件100包括放置在该集成电路芯片108和该半导体晶片102上的该介电层122之间的底部填充层112。该底部填充层112可包括用于保护焊料块110和集成电路芯片108的一部分使之免于压力、湿气、污染物和其它环境危害的非导电材料(例如环氧基树脂等)。在实施例中,该底部填充层112的热膨胀系数(CTE)被匹配于与在该集成电路芯片108上的焊料块110的CTE和该缓冲材料114的CTE类似。具有匹配的CTE的该底部填充层112用于消除焊点老化和/或开裂。
如图1中所示,半导体器件100包括缓冲材料114。在实施例中,该缓冲材料114包括在该半导体晶片102和该粘结剂116之间提供热机械缓冲的环氧基材料。该缓冲材料114形成在该半导体晶片102的一部分、该介电层122、该底部填充层112和该集成电路芯片108的至少一侧上,如图1所示。在实施方式中,该缓冲材料114包括具有中间CTE(例如介于该焊料块110和该粘结剂116的CTE之间的CTE)的材料。在一个实施例中,该缓冲材料114包括液体环氧基材料。具有中间CTE的缓冲材料114提供热机械缓冲和良好的划片和温度循环性能。
该半导体器件100包括粘结剂116,如图1所示。该粘结剂形成在缓冲材料114和集成电路芯片108上。该粘结剂材料128配置为将加强层118接合到该半导体器件100。在实施方式中,该粘结剂材料128具有高CTE(例如大于约100ppm/C)、低玻璃转变温度(例如小于约100℃)以及低弯曲模量(例如小于约1GPa)。
另外,加强层118可被附接到粘结剂116,如图1中所示。该加强层118可用于在结构和环境方面保护该半导体器件100。在实施例中,该加强层118可包括硅层(例如硅晶片)。在其它实施例中,加强层118可包括其它合金或支撑材料。在实施例中,加强层118包括具有高模量或机械强度以阻止晶片翘曲(例如小于约1mm)的材料。
半导体器件100包括形成在半导体晶片102的一侧上的至少一个焊料块120。焊料块120被设置为在该半导体晶片102和形成在印刷电路板(未示出)或其它半导体器件的表面上的对应垫(未示出)之间提供机械和/或电互连。在一个或多个实施方式中,该焊料块120可以由诸如锡-银-铜(Sn-Ag-Cu)合金焊料(即,SAC)、锡-银(Sn-Ag)合金焊料、锡-铜(Sn-Cu)合金焊料等无铅焊料制成。在一个具体实施方式中,至少一个焊料块120通过再分布层(例如前侧再分布层)的方式电耦接到该硅穿孔104。
一旦制造完成,可以采用适当的晶片级封装方法来分割并封装半导体器件100。在一个或多个实施方式中,分割的半导体器件可以包括晶片芯片尺寸封装器件,其可进一步附接到另一个器件(例如印刷电路板)以形成电子装置。
示例制造方法
图2示出了采用晶片级封装技术制造诸如图1中所示的半导体器件100的三维半导体器件的示例方法200。图3A至图3E示出了可以用于制造图1中所示的半导体器件300(诸如半导体器件100)的示例晶片的截面。如图3A中所示,半导体晶片302包括第一表面(例如顶或前面)和第二表面(例如底或背面)。半导体晶片302包括形成在第一表面附近的一个或多个集成电路(未示出)。该集成电路连接至一个或多个配置为提供电接触部的触垫306(例如,金属垫等),通过所述电接触部将集成电路互连至与半导体器件300关联的其它部件(例如,其它集成电路、印刷电路板、其它集成电路裸片等)。此外,半导体晶片302包括形成在其中的至少一个硅穿孔304和形成在半导体晶片302的至少一个表面上的介电层322(例如氧化层)。
如图3A中所示,在半导体晶片上放置集成电路芯片(方框202)。在某些实施方式中,将集成电路芯片308放置到半导体晶片302上可包括利用取放(pick and place)方法。取放技术可包括使用自动化机器将表面安装器件(例如集成电路芯片器件308)放置到衬底(例如半导体晶片302)上去。取放方法可放置集成电路芯片308并将其与半导体晶片302上的电互连件(例如触垫306)对准。
如图3B中所示,形成底胶(方块204)。在实施例中,形成底胶312包括在集成电路芯片308和半导体晶片302之间形成底胶312。在实施方式中,形成底胶312可包括使用利用毛细作用填充介于半导体晶片302和集成电路芯片308之间的剩余开口的方法。在实施例中,底胶312被分散器以液体形式施加在集成电路芯片308的边缘。在这个实施例中,底胶312进而因为毛细作用流入焊料块310之间的狭窄间隙,并扩散越过集成电路芯片308直到集成电路芯片308和半导体晶片302之间的空间被填满。
在半导体器件上形成缓冲材料(方框206)。如图3中所示,缓冲材料314形成在半导体晶片302、介电层322、底胶312的一部分以及集成电路芯片308的至少一侧上。在实施方式中,形成缓冲材料314可包括在半导体晶片302、介电层322、底胶312的一部分以及集成电路芯片308的至少一侧上模塑环氧基材料并固化该环氧基材料。在一实施例中,形成缓冲材料314可包括使用转移模塑,因为其能够模塑具有复杂特征的小元件。
在集成电路芯片和缓冲材料上形成粘结层(方框208)。如图3D所示,粘结剂316形成在集成电路芯片308和缓冲材料314上以用作半导体器件100和加强层318之间的接合材料。形成粘结剂316可包括形成配置为粘结剂电介质(例如苯并环丁烯(BCB)、聚酰亚胺(PI)、聚苯并恶唑(PBO)等)的粘结剂材料。
接着,在粘结剂上放置加强层(方块210)。正如图3E所示,放置加强层318包括在粘结剂316上放置加强层318。在实施方式中,放置加强层318包括在粘结剂上放置硅晶片。在另一个实施方式中,放置加强层318包括在粘结剂316上放置合金层。可以预见的是,一旦加强层318附接到粘结剂316,就可以利用固化方法来进一步硬化和/固化粘结剂316。
在半导体晶片上形成至少一个焊料块(方块212)。可使用各种方法形成焊料块320。在一实施方式中,使用球滴(ball drop)方法形成焊料块320。可以预见的是,诸如焊膏印刷、蒸发、电镀、喷射、柱形凸起(stud bumping)等其它技术可被用于形成焊料块320。在一实施方式中,形成焊料块320包括将焊膏施加到半导体晶片302上的预定位置,焊料块320配置为随后回流并在晶片级封装器件和另一元件(例如印刷电路板、其它集成电路芯片等)之间形成最终连接。在另一个实施例中,形成至少一个焊料块包括使用球滴方法滴下至少一滴固体的、预形成的焊球。在另一个实施例中,在半导体晶片302上形成至少一个焊料块320包括将液体或熔融形态的焊球放置在半导体晶片302上。在这些实施例中,通过加热焊球和接触材料,焊球可被接合到半导体晶片302以形成焊料块320。
一旦晶片制造过程完成,就可以采用适当的晶片级封装方法来分割并封装单个半导体器件。在一个或多个实施方式中,经过分割的半导体器件可以包括晶片芯片尺寸封装器件。
总结
虽然以针对结构特征和/或方法操作的语言描述了该主题,但是应当理解,所附权利要求中所定义的主题无需受限于以上所描述的具体特征或动作。相反,以上所描述的具体特征和动作仅作为实施权利要求的示例形式而公开。
Claims (20)
1.一种半导体器件,包括:
加工过的半导体晶片,其中该半导体晶片包括至少一个通孔;
放置在该半导体晶片的至少一部分上的介电层;
耦接到该半导体晶片的集成电路芯片;
放置在该半导体晶片和该集成电路芯片之间的底部填充层;
放置在介电层的至少一部分、该底部填充层和该半导体晶片上的缓冲材料层,并且该缓冲材料层覆盖该集成电路芯片的至少一部分;
放置在该缓冲材料层和该集成电路芯片上的粘结材料,该粘结材料具有大于100ppm/℃的热膨胀系数;
放置在该粘结材料上的加强层,其中该加强层包括具有高模量或机械强度以阻止晶片翘曲的材料,该加强层通过该粘结材料与该集成电路芯片和该缓冲材料层分隔;以及
形成在该加工过的半导体晶片上的至少一个焊料块。
2.根据权利要求1所述的半导体器件,其中该加工过的半导体晶片包括加工过的超薄半导体晶片。
3.根据权利要求1所述的半导体器件,其中该加工过的半导体晶片包括小于大约100μm厚度的晶片。
4.根据权利要求1所述的半导体器件,其中该介电层包括氧化层。
5.根据权利要求1所述的半导体器件,其中该缓冲材料层包括环氧基材料。
6.根据权利要求1所述的半导体器件,其中该缓冲材料层包括覆盖该集成电路芯片的至少一侧而露出该集成电路芯片远离底部填充层的一侧的缓冲材料层。
7.根据权利要求1所述的半导体器件,其中该加强层包括硅晶片。
8.一种电子装置,包括:
印刷电路板;以及
耦接到该印刷电路板的半导体器件,该半导体器件包括:
加工过的半导体晶片,其中该半导体晶片包括至少一个通孔;
放置在该半导体晶片的至少一部分上的介电层;
耦接到该半导体晶片的集成电路芯片;
放置在该半导体晶片和该集成电路芯片之间的底部填充层;
放置在介电层的至少一部分、该底部填充层和该半导体晶片上的缓冲材料层,并且该缓冲材料层覆盖该集成电路芯片的至少一部分;
放置在该缓冲材料层和该集成电路芯片上的粘结材料,该粘结材料具有大于100ppm/℃的热膨胀系数;
放置在该粘结材料上的加强层,其中该加强层包括具有高模量或机械强度以阻止晶片翘曲的材料,该加强层通过该粘结材料与该集成电路芯片和该缓冲材料层分隔;以及
形成在该加工过的半导体晶片上的至少一个焊料块。
9.根据权利要求8所述的电子装置,其中该加工过的半导体晶片包括加工过的超薄半导体晶片。
10.根据权利要求8所述的电子装置,其中该加工过的半导体晶片包括小于大约100μm厚度的晶片。
11.根据权利要求8所述的电子装置,其中该介电层包括氧化层。
12.根据权利要求8所述的电子装置,其中该缓冲材料层包括环氧基材料。
13.根据权利要求8所述的电子装置,其中该缓冲材料层包括覆盖该集成电路芯片的至少一侧而露出该集成电路芯片远离底部填充层的一侧的缓冲材料层。
14.根据权利要求8所述的电子装置,其中该加强层包括硅晶片。
15.一种形成半导体器件的方法,包括:
在加工过的半导体晶片上放置集成电路芯片,其中该半导体晶片包括至少一个通孔和至少一个介电层;
在该集成电路芯片和该半导体晶片之间形成底胶材料层;
在该底胶材料层的一部分、该介电层、该半导体晶片上且邻近于该集成电路芯片的至少一侧形成缓冲材料层,
在该缓冲材料层上和该集成电路芯片的一部分上形成粘结层,该粘结层的材料具有大于100ppm/℃的热膨胀系数;
在该粘结层上放置加强层,其中该加强层包括具有高模量或机械强度以阻止晶片翘曲的材料,该加强层通过该粘结材料与该集成电路芯片和该缓冲材料层分隔;以及
在该半导体晶片上形成至少一个焊料块。
16.根据权利要求15所述的形成半导体器件的方法,其中在加工过的半导体晶片上放置集成电路芯片包括在超薄半导体晶片上放置该集成电路芯片。
17.根据权利要求15所述的形成半导体器件的方法,其中在加工过的半导体晶片上放置集成电路芯片包括在小于大约100μm厚度的晶片上放置该集成电路芯片。
18.根据权利要求15所述的形成半导体器件的方法,其中在加工过的半导体晶片上放置集成电路芯片包括采用在半导体的表面上具有至少一个氧化层的半导体晶片,并且该氧化层不延伸到该半导体晶片的边缘。
19.根据权利要求15所述的形成半导体器件的方法,其中在该底胶材料层的一部分上形成缓冲材料层包括形成环氧基材料的缓冲材料层。
20.根据权利要求15所述的形成半导体器件的方法,其中在该粘结层上放置加强层包括在该粘结层上放置硅晶片。
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