CN104134674A - 一种多晶硅薄膜晶体管阵列基板及其制备方法、显示装置 - Google Patents

一种多晶硅薄膜晶体管阵列基板及其制备方法、显示装置 Download PDF

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CN104134674A
CN104134674A CN201410345316.4A CN201410345316A CN104134674A CN 104134674 A CN104134674 A CN 104134674A CN 201410345316 A CN201410345316 A CN 201410345316A CN 104134674 A CN104134674 A CN 104134674A
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electrode
storage capacitance
semiconductor layer
photoresist
insulating barrier
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CN104134674B (zh
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高涛
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BOE Technology Group Co Ltd
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Abstract

本发明提供一种多晶硅薄膜晶体管阵列基板及其制备方法、显示装置，所述方法包括：形成所述多晶硅薄膜晶体管的栅电极、栅绝缘层、半导体层、源电极和漏电极，存储电容的第一电极和第二电极，以及栅线和数据线的步骤，该步骤中，通过一次构图工艺形成所述半导体层及所述存储电容的第一电极；通过一次构图工艺形成所述栅电极、栅线及所述存储电容的第二电极。使用本发明的方案能够降低掩膜板的使用数量，使得工艺简化，降低了生产成本。

Description

一种多晶硅薄膜晶体管阵列基板及其制备方法、显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种多晶硅薄膜晶体管阵列基板及其制备方法、显示装置。
背景技术
在平面显示例如液晶显示器(LCD)、有机电致发光显示器或者无机电致发光显示器中，薄膜晶体管(TFT)一般使用做开关元件来控制像素的作业，或是用作驱动元件来驱动像素。薄膜晶体管依其硅薄膜性质通常可分为非晶硅(a-Si)与多晶硅(poly-Si)两种。与非晶硅薄膜晶体管相比较，多晶硅薄膜晶体管有更高的电子迁移率、更佳的液晶特性以及较少的漏电流。因此利用多晶硅薄膜晶体管制作的显示器会有较高的分辨率以及较快的反应速度。低温多晶硅技术已逐渐取代非晶硅技术成为薄膜晶体管研发的主流。
然而，具有多晶硅薄膜晶体管阵列基板的工艺却有着许多缺点，例如工艺复杂、成本较高等。常用的多晶硅薄膜晶体管阵列基板的掩膜板多达9道，与一般的非晶硅薄膜晶体管阵列基板的5道或者6道掩膜板相比更为复杂耗时，严重降低了工业化生产产能，增加了成本。
发明内容
有鉴于此，本发明提供一种多晶硅薄膜晶体管阵列基板及制备方法、显示装置，以克服现有技术中的多晶硅薄膜晶体管阵列基板的工艺复杂、成本高的问题。
为解决上述技术问题，本发明的实施例提供一种多晶硅薄膜晶体管阵列基板的制备方法，包括：形成所述多晶硅薄膜晶体管的栅电极、栅绝缘层、半导体层、源电极和漏电极，存储电容的第一电极和第二电极，以及栅线和数据线的步骤，其中，
通过一次构图工艺形成所述半导体层及所述存储电容的第一电极；
通过一次构图工艺形成所述栅电极、栅线及所述存储电容的第二电极。
优选地，所述形成所述多晶硅薄膜晶体管的栅电极、栅绝缘层、半导体层、源电极和漏电极，存储电容的第一电极和第二电极，以及栅线和数据线的步骤具体包括：
通过一次构图工艺形成所述半导体层及所述存储电容的第一电极；
在所述半导体层及所述存储电容的第一电极上形成栅绝缘层；
通过一次构图工艺在所述栅绝缘层上形成所述栅电极、栅线及所述存储电容的第二电极；
在所述栅电极、栅线及所述存储电容的第二电极上形成第二绝缘层，并形成贯穿所述栅绝缘层和所述第二绝缘层的过孔；
通过一次构图工艺在所述第二绝缘层上形成所述源电极、漏电极和所述数据线，所述源电极和漏电极通过所述过孔与所述半导体层接触。
优选地，所述通过一次构图工艺形成所述半导体层及所述存储电容的第一电极的步骤具体包括：
形成多晶硅半导体薄膜；
在所述多晶硅半导体薄膜上形成第一绝缘膜；
在所述第一绝缘膜上涂覆光刻胶；
采用灰色调或半色调掩膜板对所述光刻胶进行曝光和显影，形成光刻胶完全保留区域、光刻胶半保留区域及光刻胶完全去除区域，其中，所述光刻胶完全保留区域对应所述半导体层区域，所述光刻胶半保留区域对应所述存储电容区域，所述光刻胶完全去除区域对应其他区域；
采用刻蚀工艺去除所述光刻胶完全去除区域的多晶硅半导体薄膜及第一绝缘膜；
采用灰化工艺去除所述光刻胶半保留区域的光刻胶；
采用刻蚀工艺去除所述光刻胶半保留区域的第一绝缘膜，形成第一绝缘层的图形；
以所述半导体层区域上方的第一绝缘膜为掩膜进行离子注入，并进行退火工艺，使所述存储电容区域的多晶硅半导体薄膜成为导体，形成所述存储电容的第一电极，所述半导体层区域的多晶硅半导体薄膜上方有第一绝缘膜的保护，仍为半导体。
优选地，所述形成多晶硅半导体薄膜的步骤包括：
形成非晶硅半导体薄膜；
对所述非晶硅半导体薄膜进行退火工艺，去除所述非晶硅半导体薄膜中的氢原子；
对去除氢原子后的所述非晶硅半导体薄膜进行准分子激光晶化工艺，形成所述多晶硅半导体薄膜。
优选地，所述通过一次构图工艺形成所述栅电极、栅线及所述存储电容的第二电极的步骤具体包括：
形成栅金属薄膜；
在所述栅金属薄膜上涂覆光刻胶；
对所述光刻胶进行曝光和显影后，形成对应于栅电极区域、栅线区域和所述存储电容区域的光刻胶完全保留区域和对应于其他区域的光刻胶完全去除区域；
采用刻蚀工艺去除所述光刻胶完全去除区域的栅金属薄膜；
剥离所述光刻胶完全保留区域的光刻胶，形成所述栅电极、栅线和所述存储电容的第二电极。
优选地，所述栅电极位于所述半导体层区域上方，且尺寸小于所述半导体层区域的多晶硅半导体薄膜的尺寸；
所述通过一次构图工艺形成所述栅电极、栅线及存储电容的第二电极的步骤之后还包括：
以所述栅电极和栅线为掩膜进行离子注入，并进行退火工艺，使所述半导体层区域的多晶硅半导体薄膜裸露于所述栅电极的部分区域成为导体，形成接触导体，所述半导体层区域的多晶硅半导体薄膜位于所述栅电极下方的区域仍为半导体，形成所述半导体层，所述源电极和漏电极通过所述接触导体与所述半导体层接触。
优选地，所述通过一次构图工艺形成所述源电极、漏电极以及所述数据线的步骤之后还包括：
在所述源电极、漏电极以及所述数据线上形成第三绝缘层，并在所述第三绝缘层上形成过孔；
通过一次构图工艺在所述第三绝缘层上形成像素电极，所述像素电极通过所述第三绝缘层上的过孔与所述漏电极接触。
优选地，所述通过一次构图工艺形成半导体层及所述存储电容的第一电极的步骤之前还包括：
提供一衬底基板；
在所述衬底基板上形成缓冲层；
其中，通过一次构图工艺在所述缓冲层上形成所述半导体层及所述存储电容的第一电极。
本发明还提供一种多晶硅薄膜晶体管阵列基板，包括：多晶硅薄膜晶体管的栅电极、栅绝缘层、半导体层、源电极和漏电极，存储电容的第一电极和第二电极，栅线和数据线，其中，
所述半导体层及所述存储电容的第一电极同层设置，通过一次构图工艺形成；
所述栅电极、栅线及所述存储电容的第二电极同层设置，通过一次构图工艺形成。
优选地，所述多晶硅薄膜晶体管阵列基板具体包括：
同层设置的半导体层和存储电容的第一电极；
第一绝缘层，位于所述半导体层的上方；
栅绝缘层，覆盖所述半导体层、所述存储电容的第一电极及所述第一绝缘层；
同层设置的栅电极、栅线和所述存储电容的第二电极，位于所述栅绝缘层的上方；
第二绝缘层，覆盖所述栅电极、栅线和所述存储电容的上电极；
同层设置的源电极、漏电极和数据线，位于所述第二绝缘层的上方，所述源电极和漏电极通过贯穿所述栅绝缘层和第二绝缘层的过孔与所述半导体层接触；
第三绝缘层，覆盖所述源电极、漏电极和数据线；
像素电极，位于所述第三绝缘层上方，通过贯穿所述第三绝缘层的过孔与所述漏电极接触。
优选地，所述多晶硅薄膜晶体管阵列基板还包括：
衬底基板；
缓冲层，位于所述衬底基板上方，其中，所述半导体层和存储电容的第一电极位于所述缓冲层上方。
本发明还提供一种显示装置，包括上述多晶硅薄膜晶体管阵列基板。
本发明的上述技术方案的有益效果如下：
通过一次构图工艺形成多晶硅薄膜晶体管的半导体层及存储电容的第一电极，以及通过一次构图工艺形成多晶硅薄膜晶体管的栅电极、栅线及存储电容的第二电极，从而能够降低掩膜板的使用数量，使得工艺简化，降低了生产成本。
附图说明
图1为本发明的实施例一的多晶硅薄膜晶体管阵列基板的制备方法的流程示意图；
图2为本发明的实施例一的多晶硅薄膜晶体管阵列基板的制备方法的流程示意图；
图3A-3J为本发明的实施例三的多晶硅薄膜晶体管阵列基板的制备方法的流程示意图。
具体实施方式
为使本发明要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
本发明实施例提供一种多晶硅薄膜晶体管阵列基板的制备方法，包括：形成所述多晶硅薄膜晶体管的栅电极、栅绝缘层、半导体层、源电极和漏电极，存储电容的第一电极和第二电极，以及栅线和数据线的步骤，其中，所述步骤包括：
通过一次构图工艺形成所述半导体层及所述存储电容的第一电极；
通过一次构图工艺形成所述栅电极、栅线及所述存储电容的第二电极。
由于半导体层及存储电容的第一电极通过一次构图工艺形成，栅电极、栅线及存储电容的第二电极通过一次构图工艺形成，因而，能够降低掩膜板的使用数量，使得工艺简化，降低了生产成本。
上述实施例中形成的多晶硅薄膜晶体管可以为顶栅结构的薄膜晶体管，也可以为底栅结构的薄膜晶体管。
请参考图1，图1为本发明的实施例一的多晶硅薄膜晶体管阵列基板的制备方法的流程示意图。
当所述多晶硅薄膜晶体管为顶栅结构的薄膜晶体管时，所述多晶硅薄膜晶体管阵列基板的制备方法包括：形成所述多晶硅薄膜晶体管的栅电极、栅绝缘层、半导体层、源电极和漏电极，存储电容的第一电极和第二电极，以及栅线和数据线的步骤，所述步骤具体包括：
步骤S11：通过一次构图工艺形成所述半导体层及所述存储电容的第一电极；
形成的半导体层和所述存储电容的第一电极同层设置。
步骤S12：在所述半导体层及所述存储电容的第一电极上形成栅绝缘层；
步骤S13：通过一次构图工艺在所述栅绝缘层上形成所述栅电极、栅线及所述存储电容的第二电极；
所述栅电极、栅线及所述存储电容的第二电极同层设置；所述存储电容的第二电极位于所述存储电容的第一电极的上方，所述第二电极的尺寸与所述第一电极的尺寸相同。
步骤S14：在所述栅电极、栅线及所述存储电容的第二电极上形成第二绝缘层，并通过一次构图工艺形成贯穿所述栅绝缘层和所述第二绝缘层上的过孔，以露出所述半导体层；
步骤S15：通过一次构图工艺在所述第二绝缘层上形成所述源电极、漏电极和所述数据线，所述源电极和漏电极通过所述过孔与所述半导体层接触。
由于形成的多晶硅薄膜晶体管为顶栅结构的薄膜晶体管，因此，上述实施例中的存储电容的第一电极为存储电容的下电极，存储电容的第二电极为存储电容的上电极。
请参考图2，图2为本发明的实施例二的多晶硅薄膜晶体管阵列基板的制备方法的流程示意图。
当所述多晶硅薄膜晶体管为底栅结构的薄膜晶体管时，所述多晶硅薄膜晶体管阵列基板的制备方法包括：形成所述多晶硅薄膜晶体管的栅电极、栅绝缘层、半导体层、源电极和漏电极，存储电容的第一电极和第二电极，以及栅线和数据线的步骤，所述步骤具体包括：
步骤S21：通过一次构图工艺形成所述栅电极、栅线及所述存储电容的第二电极；
所述栅电极、栅线及所述存储电容的第二电极同层设置。
步骤S22：在所述栅电极、栅线及所述存储电容的第二电极上形成栅绝缘层；
步骤S23：通过一次构图工艺在所述栅绝缘层上形成所述半导体层及所述存储电容的第一电极；
形成的半导体层和所述存储电容的第一电极同层设置。所述存储电容的第一电极位于所述存储电容的第二电极的上方，所述第一电极的尺寸与所述第二电极的尺寸相同。
步骤S24：在所述半导体层及所述存储电容的第一电极上形成第二绝缘层，并通过一次构图工艺形成贯穿所述第二绝缘层的过孔，以露出所述半导体层；
步骤S25：通过一次构图工艺在所述第二绝缘层上形成所述源电极、漏电极和所述数据线，所述源电极和漏电极通过所述第二绝缘层上的过孔与所述半导体层接触。
由于形成的多晶硅薄膜晶体管为底栅结构的薄膜晶体管，因此，上述实施例中的存储电容的第一电极为存储电容的上电极，存储电容的第二电极为存储电容的下电极。
上述实施例中，可以采用等离子体增强化学气相沉积法(PECVD)形成栅绝缘层，形成的栅绝缘层厚度可以为材料可以为SiNx(氮化硅)的单层膜或者是SiNx和SiOx(氧化硅)的复合物。
上述实施例中，可以采用PECVD形成第二绝缘层，形成的第二绝缘层的厚度可以为成分可以为SiNx、SiOx，或者是SiNx和SiOx复合物等。
所述形成过孔的步骤可以为：对所述第二绝缘层进行曝光、显影，然后进行刻蚀工艺(具体可以为干法刻蚀)，形成用于源电极和漏电极与半导体层接触的过孔。
所述通过一次构图工艺在所述第二绝缘层上形成所述源电极、漏电极和所述数据线的步骤可以为：通过溅射或者热蒸镀的方法沉积源漏金属薄膜，沉积的源漏金属薄膜的厚度可以为材料可以为Mo、Al、Cu、W等金属，或者是上述几种金属的复合膜层，然后经过曝光显影并刻蚀以后形成源电极、漏电极及数据线的图形。
由于低温多晶硅薄膜晶体管通常为顶栅结构的薄膜晶体管，因而，以下实施例中，均以顶栅结构的薄膜晶体管为例进行说明。
上述实施例中，在形成所述半导体层及所述存储电容的第一电极时，需要进行离子注入工艺，现有技术中在进行离子注入工艺时，需要使用光刻胶作为掩膜，注入的离子极易引起光刻胶的固化，导致光刻胶残留，影响下一步的工序，导致多晶硅薄膜晶体管阵列基板的合格率较低。
为解决上述因在离子注入工艺中由光刻胶引起的产品合格率低的问题，本发明实施例中，在离子注入工艺中不使用光刻胶作为掩膜，而是采用绝缘层薄膜替代光刻胶，以提高产品的良率。
具体的，所述通过一次构图工艺形成所述半导体层及所述存储电容的第一电极的步骤可以包括：
形成多晶硅半导体薄膜；
在所述多晶硅半导体薄膜上形成第一绝缘膜；
在所述第一绝缘膜上涂覆光刻胶；
采用灰色调或半色调掩膜板对所述光刻胶进行曝光和显影，形成光刻胶完全保留区域、光刻胶半保留区域及光刻胶完全去除区域，其中，所述光刻胶完全保留区域对应所述半导体层区域，所述光刻胶半保留区域对应所述存储电容区域，所述光刻胶完全去除区域对应其他区域；
采用刻蚀工艺去除所述光刻胶完全去除区域的多晶硅半导体薄膜及第一绝缘膜；
采用灰化工艺去除所述光刻胶半保留区域的光刻胶；
采用刻蚀工艺去除所述光刻胶半保留区域的第一绝缘膜，形成第一绝缘层的图形；
以所述半导体层区域上方的第一绝缘膜为掩膜进行离子注入，并进行退火工艺，使所述存储电容区域的多晶硅半导体薄膜成为导体，形成所述存储电容的第一电极，所述半导体层区域的多晶硅半导体薄膜上方有第一绝缘膜的保护，仍为半导体。
本实施例中，可以采用等离子体增强化学气相沉积法(PECVD)形成所述第一绝缘膜，第一绝缘膜的材料可以为SiOx，厚度可以为
可以采用干法刻蚀工艺去除所述光刻胶完全去除区域的多晶硅半导体薄膜及第一绝缘膜。
可以采用干法刻刻蚀工艺去除所述光刻胶半保留区域的第一绝缘膜。
本实施例中的离子注入工艺中，注入的离子可以为硼离子，反应气体可以为B2H6(硼烷)，浓度可以为10％，离子加速电压可以为10-50KV(千伏)。
本实施例中，在离子注入工艺中不使用光刻胶作为掩膜，而是采用绝缘层薄膜替代光刻胶，可以有效提高产品的良率。
此外，本实施例中，采用灰色调或半色调掩膜板对光刻胶进行曝光和显影，可以有效减小工艺掩膜板的数量，进而缩短了工艺时间，提高了生产效率。
上述实施例中的多晶硅半导体薄膜可由单晶硅半导体层薄膜转换而来，具体的，所述形成多晶硅半导体薄膜的步骤可以包括：
形成非晶硅半导体薄膜；
对所述非晶硅半导体薄膜进行退火工艺(RTA)，去除所述非晶硅半导体薄膜中的氢原子；
对去除氢原子后的所述非晶硅半导体薄膜进行准分子激光晶化工艺(ELA)，形成所述多晶硅半导体薄膜。
其中，可以通过沉积的方式形成非晶硅半导体薄膜，形成的非晶硅半导体薄膜的厚度可以为对应的反应气体可以是SiH4(硅烷)、H2(氮气)的混合气体或者SiH2Cl2(二氯二氢硅)、H2(氢气)的混合气体。
上述实施例中，所述通过一次构图工艺形成所述栅电极、栅线及所述存储电容的第二电极的步骤可以包括：
形成栅金属薄膜；
在所述栅金属薄膜上涂覆光刻胶；
对所述光刻胶进行曝光和显影后，形成对应于栅电极区域、栅线区域和所述存储电容区域的光刻胶完全保留区域和对应于其他区域的光刻胶完全去除区域；
采用刻蚀工艺去除所述光刻胶完全去除区域的栅金属薄膜；
剥离所述光刻胶完全保留区域的光刻胶，形成所述栅电极、栅线和所述存储电容的第二电极。
上述步骤中，可以采用溅射(Sputter)方式沉积形成所述栅金属薄膜，形成的栅金属薄膜的厚度可以为可以为Mo(钼)、Al(铝)、Cu(铜)、W(钨)等金属，或者是上述几种金属的复合膜层。
上述步骤中，是利用普通掩膜板对光刻胶进行曝光。采用湿法刻蚀工艺去除所述光刻胶完全去除区域的栅金属薄膜。
上述实施例中形成的所述栅电极位于所述半导体层区域上方，其尺寸可以小于所述半导体层区域的多晶硅半导体薄膜的尺寸；此时，所述通过一次构图工艺形成所述栅电极、栅线及存储电容的第二电极的步骤之后还包括：
以所述栅电极和栅线为掩膜进行离子注入，并进行退火工艺，使所述半导体层区域的多晶硅半导体薄膜裸露于所述栅电极的部分区域成为导体，形成接触导体，所述半导体层区域的多晶硅半导体薄膜位于所述栅电极下方的区域仍为半导体，形成所述半导体层，所述源电极和漏电极通过所述接触导体与所述半导体层接触。
本步骤中的离子注入工艺注入的离子可以为硼离子，反应气体可以为B2H6，浓度可以为10％，离子加速电压可以为50-100KV(千伏)。
本实施例中，在离子注入工艺中不使用光刻胶作为掩膜，而是采用栅电极和栅线替代光刻胶，可以进一步提高产品的良率。此外，本实施例中形成了接触导体，使得所述半导体层可以通过该接触导体与后续形成的源电极和漏电极接触，从而减小源电极和漏电极与半导体层的接触电阻。
当然，在本发明的其他一些实施例中，也可以不进行该次离子注入工艺。
上述实施例中，所述通过一次构图工艺形成所述源电极、漏电极以及所述数据线的步骤之后还可以包括：
在所述源电极、漏电极以及所述数据线上形成第三绝缘层，并形成贯穿所述第三绝缘层的过孔；
通过一次构图工艺在所述第三绝缘层上形成像素电极，所述像素电极通过所述第三绝缘层上的过孔与所述漏电极接触。
所述在所述源电极、漏电极以及所述数据线上形成第三绝缘层，并在所述第三绝缘层上形成过孔的步骤可以为：首先采用PECVD形成第三绝缘层，形成的第三绝缘层厚度可以为成分可以为SiNx、SiOx，或者是SiNx和SiOx复合物等，然后进行曝光、显影以及刻蚀工艺(具体地，可以采用干法刻蚀)，最终在第三绝缘层上形成用于漏电极与像素电极相接触的过孔。
所述第三绝缘层也可以用绝缘树脂材料制成。
所述通过一次构图工艺在所述第三绝缘层上形成像素电极的步骤可以为：利用磁控溅射设备(Sputter)沉积一层透明导电膜，成分可以是氧化铟锡(ITO)、氧化铟锌(IZO)或氧化铝锌等材料，厚度可以为然后用普通的掩模板进行曝光工艺，显影并湿法刻蚀后，形成所述像素电极。
此外，所述通过一次构图工艺形成半导体层及所述存储电容的第一电极的步骤之前还可以包括：
提供一衬底基板；
在所述衬底基板上形成缓冲层(Buffer)；其中，通过一次构图工艺在所述缓冲层上形成所述半导体层及所述存储电容的第一电极。
所述衬底基板可以为玻璃基板，也可以为其他材质的基板。
优选地，可以使用PECVD方法沉积所述缓冲层。所述缓冲层的厚度可以为材料可以为SiOx的单层膜、或者是SiNx(氮化硅)、SiOx的复合物，对应的反应气体可以为SiH4、NH3(氨气)、N2(氮气)的混合气体或SiH2Cl2、NH3、N2的混合气体。
请参考图3A-3J，图3A-3J为本发明的实施例三的多晶硅薄膜晶体管阵列基板的制备方法的流程示意图。
所述方法包括以下步骤：
步骤3A：
在玻璃基板301上利用PECVD沉积一层缓冲层302，厚度为 材料可以是SiOx的单层膜、或者是SiNx、SiOx的复合物，对应的反应气体可以为SiH4、NH3、N2的混合气体或SiH2Cl2、NH3、N2的混合气体；
接着，再沉积一层非晶硅半导体薄膜，厚度为对应的反应气体可以是SiH4、H2的混合气体或者SiH2Cl2、H2的混合气体；
将沉积完上述膜层的玻璃基板301，先进行快速热退火工艺处理(RTA)，去除A-Si中的氢气，然后再进行准分子激光晶化工艺(ELA)，使非晶硅半导体薄膜变成多晶硅半导体薄膜303；
做完上述工艺后，再利用PECVD沉积一层第一绝缘膜304，材料可以为SiOx，厚度为
步骤3B：
在第一绝缘膜304上涂覆一层光刻胶305，利用灰色调或者半色调掩膜板对光刻胶305进行曝光、显影后，形成光刻胶完全保留区域A、光刻胶半保留区域B及光刻胶完全去除区域C，其中光刻胶完全保留区域A对应半导体层区域，光刻胶半保留区B对应存储电容区域，光刻胶完全去除区域C对应于其他区域；
步骤3C：
采用干法刻蚀工艺刻蚀掉光刻胶完全去除区域C的第一绝缘膜304及多晶硅半导体薄膜303；
然后进行一次光刻胶的灰化，去除掉光刻胶半保留区域B上的光刻胶305，然后再进行一次干法刻蚀，去除掉存储区域的多晶硅半导体薄膜303上的第一绝缘膜304，形成第一绝缘层304a的图形。
步骤3D：
进入离子注入(Ion Doping)设备，以半导体层区域的多晶硅半导体薄膜303上的第一绝缘层304a为掩膜板，进行离子注入工艺，注入的离子为硼离子，反应气体为B2H6，浓度为10％，离子加速电压可以为10-50KV(千伏)，并进行退火工艺，使存储电容区域的多晶硅半导体薄膜303变为导体，从而形成存储电容的下电极303b(见图3E)。
步骤3E：
利用PECVD沉积一层栅绝缘层306，厚度为材料可以是SiNx的单层膜或者是SiNx、SiOx的复合物；
利用Sputter沉积一层栅金属薄膜307，厚度为可以是Mo、Al、Cu、W等金属，或者是上述几种金属的复合膜层。
步骤3F：
在栅金属薄膜307上涂覆光刻胶，利用普通掩膜板进行曝光，然后进行湿法刻蚀，最终形成栅电极307a，栅线(图未示出)及存储电容的上电极307b。
将上述形成基板再次进入离子注入设备，以栅电极307a及栅线为掩膜板，进行离子注入工艺，注入的离子为硼离子，反应气体为B2H6，浓度为10％，离子加速电压可以为50-100KV(千伏)，并进行退火工艺，使半导体层区域的多晶硅半导体薄膜303大于栅电极307a的部分变为导体，形成连接导体303c(见图3G)，以减小源漏电极与半导体层的接触电阻，位于栅电极307a下方的多晶硅半导体薄膜303仍为半导体，形成半导体层303a(见图3G)。
步骤3G：
利用PECVD沉积第二绝缘层308，厚度为成分可以是SiNx、SiOx，或者是其复合物等。
步骤3H：
对第二绝缘层308进行曝光、显影，然后进行干法刻蚀，在第二绝缘层308上形成源漏电极与半导体层303a相接触的过孔。
步骤3I：
然后通过溅射或者热蒸镀的方法沉积源漏金属薄膜，厚度为 材料可以选用Mo、Al、Cu、W等金属，或者是上述几种金属的复合膜层，经过曝光显影并刻蚀以后形成源电极309a、漏电极309b及数据线(图未示出)的图形。
步骤3J：
利用PECVD沉积第三层绝缘层310，厚度为成分可以是SiNx、SiOx，或者是其复合物等，然后对第三层绝缘层310进行曝光、显影和干法刻蚀，最终在第三绝缘层310上形成漏电极309b与后续形成的像素电极相接触的过孔。第三层绝缘层310也可以用绝缘树脂代替；
利用磁控溅射设备(Sputter)沉积一层透明导电膜，成分可以是氧化铟锡(ITO)、氧化铟锌(IZO)或氧化铝锌等材料，厚度为然后用普通的掩模板进行曝光工艺，显影并湿法刻蚀后，形成像素电极311a。
对应于上述制备方法，本发明实施例还提供一种多晶硅薄膜晶体管阵列基板，包括：多晶硅薄膜晶体管的栅电极、栅绝缘层、半导体层、源电极和漏电极，存储电容的第一电极和第二电极，栅线和数据线，其中，
所述半导体层及所述存储电容的第一电极同层设置，通过一次构图工艺形成；
所述栅电极、栅线及所述存储电容的第二电极同层设置，通过一次构图工艺形成。
上述实施例中形成的多晶硅薄膜晶体管可以为顶栅结构的薄膜晶体管，也可以为底栅结构的薄膜晶体管。
当所述多晶硅薄膜晶体管为顶栅结构的薄膜晶体管时，所述多晶硅薄膜晶体管阵列基板可以具体包括：
同层设置的半导体层和存储电容的第一电极；
第一绝缘层，位于所述半导体层的上方；
栅绝缘层，覆盖所述半导体层、所述存储电容的第一电极及所述第一绝缘层(如图3I所示)；
同层设置的栅电极、栅线和所述存储电容的第二电极，位于所述栅绝缘层的上方；
第二绝缘层，覆盖所述栅电极、栅线和所述存储电容的上电极；
同层设置的源电极、漏电极和数据线，位于所述第二绝缘层的上方，所述源电极和漏电极通过贯穿所述栅绝缘层和第二绝缘层的过孔与所述半导体层接触。
优选地，上述实施例中，所述半导体层中与所述源/漏电极接触的区域经过掺杂处理，形成源/漏电极与沟道区域之间的欧姆接触区。
当所述多晶硅薄膜晶体管为底栅结构的薄膜晶体管时，所述多晶硅薄膜晶体管阵列基板可以具体包括：
同层设置的栅电极、栅线和所述存储电容的第二电极；
栅绝缘层，覆盖所述栅电极、栅线和所述存储电容的第二电极；
同层设置的半导体层和存储电容的第一电极，位于所述栅绝缘层的上方；
第一绝缘层，位于所述半导体层的上方；
第二绝缘层，覆盖所述半导体层、存储电容的第一电极及所述第一绝缘层；
同层设置的源电极、漏电极和数据线，位于所述第二绝缘层的上方，所述源电极和漏电极通过贯穿所述第二绝缘层的过孔与所述半导体层接触；
第三绝缘层，位覆盖所述源电极、漏电极和数据线；
像素电极，位于所述第三绝缘层上方，通过贯穿所述第三绝缘层的过孔与所述漏电极接触。
优选地，上述实施例中，所述半导体层的与所述源/漏电极接触的区域经过掺杂处理。
优选地，所述多晶硅薄膜晶体管阵列基板还包括：
衬底基板；
缓冲层，位于所述衬底基板上方，其中，所述半导体层和存储电容的第一电极位于所述缓冲层上方。
本发明还提供一种显示装置，包括上述实施例中的多晶硅薄膜晶体管阵列基板。所述显示装置可以为：液晶显示面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (12)

1.一种多晶硅薄膜晶体管阵列基板的制备方法，包括：形成所述多晶硅薄膜晶体管的栅电极、栅绝缘层、半导体层、源电极和漏电极，存储电容的第一电极和第二电极，以及栅线和数据线的步骤，其特征在于：
通过一次构图工艺形成所述半导体层及所述存储电容的第一电极；
通过一次构图工艺形成所述栅电极、栅线及所述存储电容的第二电极。
2.根据权利要求1所述的方法，其特征在于，所述形成所述多晶硅薄膜晶体管的栅电极、栅绝缘层、半导体层、源电极和漏电极，存储电容的第一电极和第二电极，以及栅线和数据线的步骤具体包括：
通过一次构图工艺形成所述半导体层及所述存储电容的第一电极；
在所述半导体层及所述存储电容的第一电极上形成栅绝缘层；
通过一次构图工艺在所述栅绝缘层上形成所述栅电极、栅线及所述存储电容的第二电极；
在所述栅电极、栅线及所述存储电容的第二电极上形成第二绝缘层，并形成贯穿所述栅绝缘层和所述第二绝缘层的过孔；
通过一次构图工艺在所述第二绝缘层上形成所述源电极、漏电极和所述数据线，所述源电极和漏电极通过所述过孔与所述半导体层接触。
3.根据权利要求1或2所述的方法，其特征在于，所述通过一次构图工艺形成所述半导体层及所述存储电容的第一电极的步骤具体包括：
形成多晶硅半导体薄膜；
在所述多晶硅半导体薄膜上形成第一绝缘膜；
在所述第一绝缘膜上涂覆光刻胶；
采用灰色调或半色调掩膜板对所述光刻胶进行曝光和显影，形成光刻胶完全保留区域、光刻胶半保留区域及光刻胶完全去除区域，其中，所述光刻胶完全保留区域对应所述半导体层区域，所述光刻胶半保留区域对应所述存储电容区域，所述光刻胶完全去除区域对应其他区域；
采用刻蚀工艺去除所述光刻胶完全去除区域的多晶硅半导体薄膜及第一绝缘膜；
采用灰化工艺去除所述光刻胶半保留区域的光刻胶；
采用刻蚀工艺去除所述光刻胶半保留区域的第一绝缘膜，形成第一绝缘层的图形；
以所述半导体层区域上方的第一绝缘膜为掩膜进行离子注入，并进行退火工艺，使所述存储电容区域的多晶硅半导体薄膜成为导体，形成所述存储电容的第一电极，所述半导体层区域的多晶硅半导体薄膜上方有第一绝缘膜的保护，仍为半导体。
4.根据权利要求3所述的方法，其特征在于，所述形成多晶硅半导体薄膜的步骤包括：
形成非晶硅半导体薄膜；
对所述非晶硅半导体薄膜进行退火工艺，去除所述非晶硅半导体薄膜中的氢原子；
对去除氢原子后的所述非晶硅半导体薄膜进行准分子激光晶化工艺，形成所述多晶硅半导体薄膜。
5.根据权利要求3所述的方法，其特征在于，所述通过一次构图工艺形成所述栅电极、栅线及所述存储电容的第二电极的步骤具体包括：
形成栅金属薄膜；
在所述栅金属薄膜上涂覆光刻胶；
对所述光刻胶进行曝光和显影后，形成对应于栅电极区域、栅线区域和所述存储电容区域的光刻胶完全保留区域和对应于其他区域的光刻胶完全去除区域；
采用刻蚀工艺去除所述光刻胶完全去除区域的栅金属薄膜；
剥离所述光刻胶完全保留区域的光刻胶，形成所述栅电极、栅线和所述存储电容的第二电极。
6.根据权利要求5所述的方法，其特征在于，所述栅电极位于所述半导体层区域上方，且尺寸小于所述半导体层区域的多晶硅半导体薄膜的尺寸；
所述通过一次构图工艺形成所述栅电极、栅线及存储电容的第二电极的步骤之后还包括：
以所述栅电极和栅线为掩膜进行离子注入，并进行退火工艺，使所述半导体层区域的多晶硅半导体薄膜裸露于所述栅电极的部分区域成为导体，形成接触导体，所述半导体层区域的多晶硅半导体薄膜位于所述栅电极下方的区域仍为半导体，形成所述半导体层，所述源电极和漏电极通过所述接触导体与所述半导体层接触。
7.根据权利要求2所述的方法，其特征在于，所述通过一次构图工艺形成所述源电极、漏电极以及所述数据线的步骤之后还包括：
在所述源电极、漏电极以及所述数据线上形成第三绝缘层，并在所述第三绝缘层上形成过孔；
通过一次构图工艺在所述第三绝缘层上形成像素电极，所述像素电极通过所述第三绝缘层上的过孔与所述漏电极接触。
8.根据权利要求2所述的方法，其特征在于，所述通过一次构图工艺形成半导体层及所述存储电容的第一电极的步骤之前还包括：
提供一衬底基板；
在所述衬底基板上形成缓冲层；
其中，通过一次构图工艺在所述缓冲层上形成所述半导体层及所述存储电容的第一电极。
9.一种多晶硅薄膜晶体管阵列基板，包括：多晶硅薄膜晶体管的栅电极、栅绝缘层、半导体层、源电极和漏电极，存储电容的第一电极和第二电极，栅线和数据线，其特征在于，
所述半导体层及所述存储电容的第一电极同层设置，通过一次构图工艺形成；
所述栅电极、栅线及所述存储电容的第二电极同层设置，通过一次构图工艺形成。
10.根据权利要求9所述的多晶硅薄膜晶体管阵列基板，其特征在于，所述多晶硅薄膜晶体管阵列基板具体包括：
同层设置的半导体层和存储电容的第一电极；
第一绝缘层，位于所述半导体层的上方；
栅绝缘层，覆盖所述半导体层、所述存储电容的第一电极及所述第一绝缘层；
同层设置的栅电极、栅线和所述存储电容的第二电极，位于所述栅绝缘层的上方；
第二绝缘层，覆盖所述栅电极、栅线和所述存储电容的上电极；
同层设置的源电极、漏电极和数据线，位于所述第二绝缘层的上方，所述源电极和漏电极通过贯穿所述栅绝缘层和第二绝缘层的过孔与所述半导体层接触；
第三绝缘层，覆盖所述源电极、漏电极和数据线；
像素电极，位于所述第三绝缘层上方，通过贯穿所述第三绝缘层的过孔与所述漏电极接触。
11.根据权利要求10所述的多晶硅薄膜晶体管阵列基板，其特征在于，还包括：
衬底基板；
缓冲层，位于所述衬底基板上方，其中，所述半导体层和存储电容的第一电极位于所述缓冲层上方。
12.一种显示装置，其特征在于，包括如权利要求9-11任一项所述的多晶硅薄膜晶体管阵列基板。
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