CN104134651A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN104134651A
CN104134651A CN201410182740.1A CN201410182740A CN104134651A CN 104134651 A CN104134651 A CN 104134651A CN 201410182740 A CN201410182740 A CN 201410182740A CN 104134651 A CN104134651 A CN 104134651A
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Prior art keywords
wiring board
chip
semiconductor chip
semiconductor
semiconductor device
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CN201410182740.1A
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CN104134651B (zh
Inventor
宮本浩靖
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

本发明涉及半导体装置。矩形的控制芯片的长边和矩形的存储器芯片的长边被布置为平行于BGA中的布线衬底的上表面的第一边。盖子包括一对第一边檐和一对第二边檐，第二边檐的宽度被形成为比第一边檐更宽，并且在安装在布线衬底的上表面上的控制芯片的短边的外侧以及安装在布线衬底的上表面上的存储器芯片的短边的外侧确保用于安装片状部件的安装区域和用于接合盖子的接合基底区，这使得能够在接合基底区上布置盖子的较宽的宽度的第二边檐。因此，能够减小BGA的安装面积。

Description

半导体装置
相关申请的交叉引用
将2013年5月1日提交的日本专利申请No.2013-096477的公开内容(包括说明书、附图以及摘要)通过参考全部并入在本申请中。
技术领域
本发明涉及半导体装置，并且更特别地，本发明涉及可以有用地应用于在布线衬底上具有多个半导体芯片的半导体装置的技术。
背景技术
日本未经审查的专利申请公开No.2012-54597公开了一种半导体装置的配置，该半导体装置包括：其上安装有半导体元件的封装衬底；具有其中安放半导体元件的凹陷部分以及围绕这个凹陷部分的外周边形成的凸缘(flange)的盖子(lid)；在半导体元件与盖子的凹陷部分之间形成的粘附层；以及在封装衬底与盖子的凸缘之间形成的粘附层。
此外，日本未经审查的专利申请公开No.平07(1995)-50360公开了一种半导体装置的配置，该半导体装置包括：沿着与封装体的主体相对布置的表面的周边形成的金属层，其作为用于焊料层的底层并且其宽度部分地或各处窄或宽；以及盖子衬底(盖子)。
此外，日本未经审查的专利申请公开No.平08(1996)-51167公开了一种半导体装置的配置，该半导体装置包括用于密封安装在半导体封装基底衬底的半导体芯片安装部上的半导体芯片的半导体封装密封盖子。
发明内容
作为安装在诸如移动终端之类的电子设备上的半导体装置的封装体(在下文中被称为封装体或半导体封装体)，具有其中多个半导体芯片被倒装芯片式安装在布线衬底上的配置的封装体是公知的。特别地，倒装芯片安装技术是对于用于在与外部的信号传输中的高速处理(例如，约12Gbps响应频率传输)的半导体装置的有效安装技术。
此外，倒装芯片安装技术也是对于使安装在布线衬底上的封装体的安装面积尺寸缩小的有效安装技术。
然而，在包括如上所述以这种高速操作的半导体芯片的半导体装置中，用于释放从半导体芯片辐射出的热量的放热是非常重要的。例如，作为用于释放热量的手段之一，公知一种半导体装置的配置，在其中称为盖子的覆盖部件被接合到被倒装芯片式安装在布线衬底上的半导体芯片以便释放从半导体芯片辐射的热量。
然而，实际上，在配置为具有如上所述的这种盖子的半导体装置被安装在诸如移动终端之类的电子设备上的情况下，因为半导体装置被安装在电子设备中的母板上，所以必须使得封装体的安装面积尽可能小。此外，必要的是应该尽可能多地减少封装体的安装高度。
在上述的三个日本未经审查的专利申请公开中，虽然公开了每个都包括盖子的半导体装置(封装体)的配置，但是没有充分地考虑使得封装体的安装面积尽可能小或尽可能多地减少封装体的安装高度。
根据在下文中的本说明书和附图的描述将揭示有关技术的其它问题和本发明的新的特征。
根据本发明一个方面，一种半导体装置包括：第一半导体芯片，其第一主表面为矩形；第二半导体芯片，其第二主表面为矩形；布线衬底，具有第一表面，第一半导体芯片和第二半导体芯片经由多个突出电极安装在第一表面上，第一表面被形成为四角形形状，所述四角形形状具有彼此相对地布置的一对第一边和彼此相对地布置的一对第二边；以及覆盖部件，覆盖第一半导体芯片和第二半导体芯片。此外，在该半导体装置中，第一半导体芯片的第一主表面和第二半导体芯片的第二主表面分别与布线衬底的第一表面相对地布置，并且第一半导体芯片的长边以及第二半导体芯片的长边被分别布置为基本上平行于布线衬底的第一表面的第一边。此外，在该半导体装置中，所述覆盖部件包括分别沿着布线衬底的第一表面的第一边布置的一对第一边檐以及分别沿着布线衬底的第一表面的第二边布置的一对第二边檐，并且第二边檐的宽度比第一边檐的宽度更宽。
根据本发明的该方面，可以减少半导体装置的安装面积。
附图说明
图1是示出根据本发明实施例的半导体装置的结构的示例的平面图；
图2是示出在覆盖部件被假设为透明的情况下的图1中示出的半导体装置的结构的平面图；
图3是沿着图1中示出的线A-A切割的结构的截面图；
图4是沿着图1中示出的线B-B切割的结构的截面图；
图5是图3中示出的部分C的部分放大截面图；
图6是图4中示出的部分C的部分放大截面图；
图7是示出图1中示出的半导体装置的背面的结构的背面视图；
图8是示出安装在图1中示出的半导体装置上的片状部件(chippart)的结构的示例的透视图；
图9是示出安装在图1中示出的半导体装置上的覆盖部件的结构的示例的平面图和侧视图；
图10是示出根据实施例的第一变型的半导体装置的结构的截面图；
图11是示出根据第一比较示例的半导体装置的结构的截面图；
图12是示出根据实施例的第二变型的半导体装置的结构的截面图；
图13是示出根据第二比较示例的半导体装置的结构的截面图；以及
图14是示出焊料由于底部填料(underfill)的粘附而被推出到片状部件的状态的截面图。
具体实施方式
在下文中要给出的本发明的实施例的描述中，除需要重复说明的情况之外通常不重复关于相同或类似的部分的说明。
此外，在实施例的描述中，虽然实施例之一被分成多个部分或多个实施例，并且为了说明的方便起见分别给出关于该多个部分或多个实施例的说明，但是这些说明不是彼此无关的，并且除非明确地指定，否则这些说明之一与其它说明的部分或整体的修改、细节、补充说明等有些关系。
此外，在下面的实施例的描述中，在提及要素等的数字(包括数量、数值、量、以及范围等)的情况下，除非另有明确地指定或除非它们原理上被限制于指定的数字，否则该要素等的数字不限于指定的数字并且将假设要素等的数字可以大于指定的数字或小于指定的数字。
此外，在下面的实施例的描述中，不用说，除非另有明确地指定或除非它们在原理上明显地是必不可少的，否则任何实施例的组成要素(包括要素的步骤)不一定是必不可少的。
此外，在下面的实施例的描述中，不用说，当陈述一个实施例“包括”、“包含”、“具有”或“含有”组成要素时，除非明确地陈述实施例仅仅包括上述组成要素，否则它不意指除上述组成要素以外的要素被排除在外。以类似的方式，在下面的实施例的描述中，将假设，当给出关于一个实施例包括的组成要素等的形状、位置关系等的说明时，相同的说明可以用于实施例包括的近似或类似的组成要素的形状、位置关系等。这适用于上述数字、范围等。
在下文中，将参考附图详细说明本发明的实施例。此外，在用于说明实施例的所有附图中，具有相同功能的组成要素将由相同的附图标记表示，并且将省略其冗余的描述。此外，为了提供容易理解的附图，将有即使在平面图中也使用阴影线的情况。
(实施例)
图1是示出根据本发明实施例的半导体装置的结构的示例的平面图；图2是示出在覆盖部件被假设为透明的情况下的图1中示出的半导体装置的结构的平面图；图3是沿着图1中示出的线A-A切割的结构的截面图；图4是沿着图1中示出的线B-B切割的结构的截面图；图5是图3中示出的部分C的部分放大截面图；并且图6是图4中示出的部分C的部分放大截面图。此外，图7是示出图1中示出的半导体装置的背面的结构的背面视图；图8是示出安装在图1中示出的半导体装置上的片状部件的结构的示例的透视图；并且图9是示出安装在图1中示出的半导体装置上的覆盖部件的结构的示例的平面图和侧视图。
根据本实施例的半导体装置是半导体封装体中安放的半导体装置，在该半导体封装体中两个半导体芯片被平放地倒装芯片式安装在作为布线衬底的封装衬底上，并且另外安装称为盖子的覆盖部件使得覆盖这些半导体芯片。
此外，作为根据本实施例的半导体装置的示例，将说明包括作为安装在布线衬底的下表面上的多个球电极的外部连接端子的半导体装置。因此，在本实施例中描述的半导体装置是安放在BGA(球栅阵列)型封装体中的半导体装置。
此外，根据本实施例的半导体装置是在其中在内部芯片之间或与外部的信号传输中执行高速处理的半导体装置(例如，执行在内部芯片之间约1.2Gbps响应频率传输以及与外部约12Gbps响应频率传输)。
将参考图1到图7描述用于本实施例的BGA5的结构。如图2到图4所示，BGA5包括倒装芯片式安装在布线衬底1上的第一半导体芯片、也倒装芯片式安装(平放地)在第一半导体芯片旁边的第二半导体芯片、以及安装为使得覆盖第一和第二半导体芯片的盖子(覆盖部件)7。
在本实施例中，将描述包括作为控制芯片2的第一半导体芯片和作为存储器芯片3的第二半导体芯片的半导体装置的示例。具体而言，存储器芯片3由控制芯片2控制。
在该情况下，控制芯片2具有主表面(第一主表面)2a和与主表面2a相对布置的背面(第一背面)2b，并且主表面2a被形成为相对细长的矩形。换句话说，如图2所示，控制芯片2是其平面图为细长的矩形的半导体芯片。
另一方面，存储器芯片3具有主表面(第二主表面)3a和与主表面3a相对布置的背面(第二背面)3b，并且主表面3a被形成为具有大面积的相对接近正方形的矩形。换句话说，如图2所示，存储器芯片3是其平面图为接近正方形的矩形，并且与控制芯片2的主表面2a相比该存储器芯片3的主表面3a具有大面积。这是因为优选的是存储器芯片3具有大存储容量，使得主表面3a的面积被设定为较大(存储器芯片3的芯片尺寸比控制芯片2的芯片尺寸大得多)。
此外，如图5所示，多个电极焊盘(电极)2c被形成在控制芯片2的主表面2a上，而如图6所示，多个电极焊盘(电极)3c也被形成在存储器芯片3的主表面3a上。此外，半导体集成电路分别形成在控制芯片2和存储器芯片3内部，并且这些电路与电极焊盘2c和电极焊盘3C电气耦接。
如图3所示，布线衬底1具有上表面(第一表面)1a和与上表面相对的下表面(第二表面)1b，并且上表面1a和下表面1b被布置为在其之间具有基底材料1e。此外，如图2所示，上表面1a被形成为四角形的形状，该四角形具有彼此相对地布置的一对第一边1aa和1ab以及彼此相对地布置的一对第二边1ac和1ad。另一方面，如图7所示，如上表面1a的情况一样，下表面1b也被形成为四角形的形状。
此外，如图5和图6所示，多个连接盘(land)(端子或电极)1c被安装在布线衬底1的上表面1a上，而多个连接盘(端子或电极)1d也被安装在下表面1b上。此外，阻焊膜(绝缘膜)1f被形成在上表面1a和下表面1b上，并且上表面1a上的连接盘1c在上表面1a上的阻焊膜1f的多个开口处被暴露，并且下表面1b上的连接盘1d在下表面1b上的阻焊膜1f的多个开口处被暴露。
因此，在布线衬底1中，上表面1a上的连接盘1c和下表面1b上的与连接盘1c对应的连接盘1d分别经由内部布线或通孔布线(未示出)被电气耦接。
控制芯片2和存储器芯片3被倒装芯片式安装在如上配置的布线衬底1的上表面1a上。换句话说，控制芯片2的主表面2a和存储器芯片3的主表面3a分别与布线衬底1的上表面1a相对地布置。此外，控制芯片2的主表面2a和存储器芯片3的主表面3a经由多个凸块电极(凸块或突出电极)4分别与布线衬底1的上表面1a上的连接盘1c电气耦接。
此外，如图3、图4和图7所示，作为外部连接端子的球电极(外部电极端子)8以网格图案(格子状图案)方式被安装在布线衬底1的下表面1b上。
在上面描述的根据本实施例的BGA5中，安装在布线衬底1的上表面1a上的控制芯片2的电极焊盘2c和存储器芯片3的电极焊盘3c分别经由对应的凸块电极4、连接盘1c和连接盘1d而与多个球电极8耦接。
此外，在BGA5中，如图3到图6所示，在控制芯片2与布线衬底1之间的空间和在存储器芯片3与布线衬底1之间的空间分别用底部填料(树脂剂或粘合剂)6填充。用底部填料填充上述空间使得可以减少在封装体被组装之后执行的热处理(例如，热循环试验)中给封装体(半导体装置)加热时施加于倒装芯片接合部的热应力，这是因为底部填料6可以缓和每个芯片的热膨胀系数与布线衬底1的热膨胀系数之间的差别。
换句话说，控制芯片2和存储器芯片3的倒装芯片接合部可以通过底部填料6被加强。
此外，底部填料6被形成为使得覆盖控制芯片2的侧表面2d和存储器芯片3的侧表面3d，使得控制芯片2和存储器芯片3自身也可以由底部填料6保护。
此外，在根据本实施例的BGA5的平面图中，布线衬底1的上表面1a是正方形的，如图2所示。换句话说，上表面1a的四边的长度彼此相等，即，上表面1a的彼此相对地布置的第一边1aa和1ab与彼此相对的第二边1ac和1ad彼此相等。
虽然布线衬底1的上表面1a是正方形的，但是控制芯片2的主表面2a的彼此相对的长边2aa和2ab以及存储器芯片3的主表面3a的彼此相对的长边3aa和3ab分别被布置为基本上平行于布线衬底1的上表面1a的第一边1aa(或第一边1ab)。
换句话说，控制芯片2的主表面2a的彼此相对的短边2ac和2ad以及存储器芯片3的主表面3a的彼此相对的短边3ac和3ad分别被布置为基本上平行于布线衬底1的上表面1a的第二边1ac(或第二边1ad)。
此外，在根据本实施例的BGA5中，多个片状部件(在本实施例中为片状电容器(chip capacitor))9(9a)被安装在布线衬底1的上表面1a上的控制芯片2的短边2ac和2ad的外侧以及布线衬底1的上表面1a上的存储器芯片3的短边3ac和3ad的外侧。
详细地说，在布线衬底1的上表面1a上，片状部件9a(9)被安装在控制芯片2的短边2ac(短边2ad)与布线衬底1的上表面1a的第二边1ac(第二边1ad)之间的区域上。此外，片状部件9a(9)被类似地安装在存储器芯片3的短边3ac(短边3ad)与布线衬底1的上表面1a的第二边1ac(第二边1ad)之间的区域上。
此外，如图3和图7所示，多个片状部件9b(9)被安装在布线衬底1的下表面1b上。
这些片状部件9a、9b(9)被安装以用于BGA5中的噪声减少。由于在BGA5中的内部芯片之间的或与外部的信号传输中执行高速处理(例如，1.2Gbps响应频率传输或更高的传输)，因此信号易于受噪声的影响。特别地，存在模拟电路受从数字电路振荡的噪声的影响的高可能性。因此，可以通过在半导体芯片附近安装许多作为片状电容器的片状部件9来增强噪声去除效果。
在根据本实施例的BGA5中，由于安装在布线衬底1的上表面1a上的片状部件9的数量不够，因此若干数量的片状部件9还被安装在布线衬底1的下表面1b上。
这里，如图8所示，片状部件9具有如下的结构，即在该结构中端子部(电极部)9d被形成在片状部件9的主体9c的两侧上，并且片状部件9经由焊料13而与布线衬底1耦接，如图4和图6所示。此外，为了使得安装的片状部件9的数量尽可能小，可推荐的是片状部件9应该被安装为尽可能靠近半导体芯片或者大容量(大尺寸)的片状部件(片状电容器)9应该被安装。
然而，由于存在用户的规范等施加的对封装体的尺寸(高度等)的限制，因此难以安装大尺寸的片状部件(片状电容器)9，因此为了减少噪声也必须在使用BGA5的情况下安装大量的低高度片状部件9。
因此，在根据本实施例的BGA5中，两个矩形的控制芯片2和存储器芯片3被布置为使得控制芯片2的长边2aa(或2ab)以及存储器芯片3的长边3aa(或3ab)基本上平行于并且尽可能靠近正方形的布线衬底1的上表面1a的第一边1aa(或1ab)。(图2示出其中控制芯片2的长边2aa和存储器芯片3的长边3aa基本上平行于并且尽可能靠近正方形的布线衬底1的上表面1a的第一边1aa的示例。)除了上述布置条件之外，控制芯片2和存储器芯片3被布置在正方形的布线衬底1的上表面1a的第二边1ac和1ad之间的中间位置处。在该情况下，可以在正方形的布线衬底1的上表面1a的第二边1ac和1ad侧确保其上安装有多个片状部件9的空间。
此外，与盖子(覆盖部件)7接合的接合基底区1h被制备在多个片状部件9的安装区域1g外侧的在其它方向(平行于第一边1aa和1ab的方向)上的端部上。换句话说，由于必须在布线衬底1的所述一个方向(平行于第二边1ac和1ad的方向)上的端部上确保用于安装控制芯片2和存储器芯片3的安装空间，因此不在第一边1aa和1ab侧的端部上提供与盖子7接合的接合基底区1h。
换句话说，在其上表面为正方形的布线衬底1上安装两个矩形的半导体芯片和在两个芯片附近的多个片状部件9的情况下，如图2所示，其中两个半导体芯片的长边被设定为相同方向并且在半导体芯片的短边的外侧的区域中确保与盖子7接合的接合基底区1h和用于安装片状部件9的安装区域1g的布置使得半导体装置的安装面积能够最小。
结果，芯片、片状部件9、以及与盖子7接合的接合基底区1h的上述布置可以使得BGA5的平面图的尺寸最小。
因此，如图4所示，因为在第二边1ac和1ad侧的上表面1a的边缘上提供图2中示出的接合基底区1h，盖子7经由粘合剂10在布线衬底1的上表面1a的第二边1ac和1ad侧被接合到布线衬底1，而如图3所示，因为不在第一边1aa和1ab侧提供接合基底区1h，盖子7不在布线衬底1的上表面1a的第一边1aa和1ab侧与布线衬底1耦接。
这里，图2中示出的区域C为由盖子7覆盖的区域。
如图1、图3和图4所示，盖子7包括分别沿着布线衬底1的上表面1a的第一边1aa和1ab布置的一对边檐(brim)(第一边檐或凸缘)7a和7b以及分别沿着第二边1ac和1ad布置的一对边檐(第二边檐或凸缘)7c和7d。
换句话说，凸缘形状的边檐7a、7b、7c和7d被形成在盖子7的周边上，并且周边内侧的区域为形成在比边檐7a、7b、7c和7d更高的位置中而且由通过弯曲处理形成的弯曲部7e支撑的天花板(ceiling)部7f。在该情况下，弯曲部7e的弯曲量例如为0.2mm。
因此，盖子7具有在高位置中形成的天花板部7f以及围绕天花板部7f形成的凸缘形状的边檐7a、7b、7c和7d。
此外，如图5、图6和图9所示，边檐7c和7d的宽度M被设定为大于边檐7a和7b的宽度L(M>L，例如，M＝1.5mm，并且L＝0.5mm)。这是因为在布线衬底1的正方形的上表面1a的第二边1ac和1ad侧的端部上提供接合基底区1h并且不在第一边1aa和1ab侧的端部上提供接合基底区1h。由于这个原因，与其中提供接合基底区1h的边缘对应的盖子7的边檐7c和7d的宽度M大于与其中不提供接合基底区1h的边缘对应的边檐7a和7b的宽度L。
因此，在BGA5中，如图4和图6所示，在布线衬底1的上表面1a的第二边1ac和1ad侧的端部上的接合基底区1h中，盖子7的边檐7c和7d经由粘合剂10被接合到布线衬底1，而如图3和图5所示，在布线衬底1的上表面1a的第一边1aa和1ab侧的边缘上，盖子7的边檐7a和7b不耦接到布线衬底1，并且在盖子7的边檐7a和7b与布线衬底1之间存在空间11。
这里，接合盖子7和布线衬底1的粘合剂10为例如环氧树脂粘合剂10。
此外，在BGA5中，如图2所示，两个矩形的半导体芯片被安装在布线衬底1上，并且两个芯片被倒装芯片式安装为使得控制芯片2的短边2ac和2ad以及存储器芯片3的短边3ac和3ad被布置为平行于布线衬底1的上表面1a的第二边1ac和1ad。
当在封装体被组装之后执行的热处理(例如，热循环试验)中热应力被施加到倒装芯片接合部时，在布线衬底1的上表面1a的第二边1ac和1ad的方向上(在存储器芯片3的短边3ac和3ad以及控制芯片2的短边2ac和2ad的延伸方向上)存在由于用于半导体芯片的底部填料6的热收缩而发生翘曲的趋势。
因此，在根据本实施例的BGA5中，盖子7的边檐(第二边檐)7c和7d的宽度被设定为大于边檐(第一边檐)7a和7b的宽度，并且盖子7经由粘合剂10在边檐7c和7d处被接合到布线衬底1，这在布线衬底1的上表面1a的第二边1ac和1ad的延伸方向上(在存储器芯片3的短边3ac和3ad以及控制芯片2的短边2ac和2ad的延伸方向上)增强布线衬底1的强度。
结果，在BGA5中，即使在用于半导体芯片的底部填料6由于热应力而收缩时，也可以抑制布线衬底1的翘曲。
这里，盖子7由例如金属板(诸如铜板)组成。如图3和图4所示，在盖子7的表面上执行金属镀敷7g。此外，盖子7经由导热粘合剂(导电的树脂剂)12(或经由焊料剂)被接合到控制芯片2的背面(面向上的表面)2b和存储器芯片3的背面(面向上的表面)3b。
上述导热粘合剂12例如由银浆或基于铝的浆料制成。
如上所述，因为控制芯片2和存储器芯片3经由导热粘合剂12被接合到由金属板组成的盖子7，所以从控制芯片2和存储器芯片3辐射的热可以经由导热粘合剂12通过盖子7被释放，因此可以改善BGA5的可靠性。
此外，如图1和图2所示，标记1i被放到布线衬底1的上表面1a的四个角之一。
这个标记1i扮演在将半导体芯片和盖子7安装在布线衬底1上时用于对准半导体芯片和盖子7的记号的角色。通过参考标记1i将半导体芯片和盖子7安装在布线衬底1上，可以无误地检查布线衬底1、控制芯片2、存储器芯片3和盖子7的安装方向。同样在完成BGA5的配置之后，可以由标记1i示出半导体装置的方向。
此外，在根据本实施例的BGA5中，如图2和图3所示，在布线衬底1的上表面1a上在控制芯片2和存储器芯片3之间形成树脂扩散防止部。在本实施例中，树脂扩散防止部是通过将布线衬底1的上表面1a上形成的阻焊膜1f开槽而形成的凹槽(凹陷部分)1j。可替代地，可以通过部分地去除阻焊膜1f使得阻焊膜1f之下的布线层(铜)的一部分被暴露，来形成凹槽(凹陷部分)1j。
在BGA5的组装中，在其尺寸彼此不同的控制芯片2和存储器芯片3被安装在布线衬底1上之后在控制芯片2和布线衬底1之间以及在存储器芯片3和布线衬底1之间分别滴下底部填料6的情况下，如果用于半导体的底部填料6彼此接触，则可能发生由于底部填料的表面张力之间的不平衡而底部填料之一被其它底部填料吸引的现象。
这个现象是经常发生的现象，这是因为如果底部填料的每施加面积的施加量较大，底部填料更容易湿润地扩散。因此其特性容易受施加量的变化影响的底部填料6(也就是说，底部填料的施加面积小)具有容易湿润地扩散的倾向，并且具有相对稳定的每施加面积的施加量的底部填料6(也就是说，底部填料的施加面积大)吸引具有小施加面积的底部填料6。在BGA5中，施加于控制芯片2的小施加面积的底部填料6a被施加于存储器芯片3的大施加面积的底部填料6b吸引，使得发生施加量之间的平衡丢失的现象。
因此，通过在布线衬底1的上表面1a上的存储器芯片3和控制芯片2之间的区域上，并且更确切地说，在底部填料6a和底部填料6b的施加区域之间的区域上，形成凹槽1j，易于扩散的底部填料6a的湿润扩散被阻挡，使得可以防止底部填料6a扩散到底部填料6b侧(存储器芯片3侧)。
此外，在BGA5中，如图2和图4所示，作为树脂扩散防止部的凹槽(凹陷部分)1k被形成在控制芯片2和存储器芯片3中的至少一个半导体芯片与布线衬底1的上表面1a上的多个片状部件9之间的区域上。在本实施例中，因为存储器芯片3的长边3aa和3ab比控制芯片2的长边2aa和2ab更长，所以底部填料6b比底部填料6a更靠近片状部件9。
因此凹槽1k被形成在布线衬底1的上表面1a上的存储器芯片3和片状部件9之间的区域上。
因此，当底部填料6b被滴下以便填充布线衬底1的上表面1a和存储器芯片3之间的间隙时，易于扩散到片状部件9的区域中的底部填料6b的湿润扩散被阻挡，使得可以防止底部填料6b扩散到片状部件9的安装区域1g中。
下面将描述在底部填料(树脂)6b粘附于片状部件9的焊料接合部时发生的缺陷。
图14是示出焊料由于底部填料的粘附而被推出到片状部件的状态的截面图。如果底部填料(树脂)6b粘附于片状部件9的焊料接合部，则通过由于温度变化等的重复弯曲从底部填料6b的粘附部分的开口22(在图14中的P方向上)推出焊料23，并且推出的焊料23可以在片状部件9的端子部9d上形成焊料的块(lump)。
结果，如下这种缺陷可能发生，即推出的焊料23变得接触周围部件并且短路或者推出的焊料23掉落且变得接触其它部件并且短路。
因此，通过在存储器芯片3和片状部件9之间的区域上形成凹槽1k，底部填料6b的湿润扩散被阻挡并且防止底部填料6b粘附于片状部件9，使得可以防止发生上述缺陷。
此外，如图3和图7所示，多个球电极(外部连接端子)8和多个片状部件(片状电容器)9b被形成在BGA5中的布线衬底1的下表面1b上。此外，如图3所示，球电极8的距离下表面1b的高度被设定为高于安装在下表面1b上的多个片状部件9b的距离下表面1b的高度。
由于上述配置，在安装板等上安装BGA5时，可以防止发生诸如安装在布线衬底1的下表面1b上的片状部件9b接触安装板之类的关于BGA5的安装缺陷。
在根据本实施例的BGA5中，两个半导体芯片的长边2aa、2ab、3aa和3ab被布置为平行于布线衬底1的上表面1a的第一边1aa和1ab，并且盖子7具有分别沿着平行于第一边1aa和1ab布置的一对边檐7a和7b、以及分别沿着第二边1ac和1ad布置的一对边檐7c和7d。此外，边檐7c和7d的宽度被设定为大于边檐7a和7b的宽度。
由于上述配置，在布线衬底1的上表面1a上，在存储器芯片3的短边3ac和控制芯片2的短边2ac侧以及存储器芯片3的短边3ad和控制芯片2的短边2ad侧分别确保两个区域，使得盖子7的较宽的边檐7c和7d可以分别被布置在上述两个区域上。
换句话说，在BGA5中，两个矩形的半导体芯片的长边被布置在相同方向并且两个矩形的半导体芯片的短边被布置在相同方向，并且在正方形的布线衬底1的上表面1a的两个方向之一上(在平行于第二边1ac和1ad的方向上)最大程度地安装半导体芯片。此外，在沿着第二边1ac和1ad的边缘上(在平行于第一边1aa和1ab的方向上的两端上)确保用于片状部件9的安装区域1g和用于盖子7的接合基底区1h。
结果，盖子7的较宽的边檐7c和7d可以被布置在布线衬底1的上表面1a上的接合基底区1h上，并且盖子7可以经由粘合剂10通过接合基底区1h被接合到布线衬底1。
由于上述配置，变得可以减少包括两个矩形的半导体芯片(即，控制芯片2和存储器芯片3)以及覆盖这些半导体芯片的盖子7的BGA5的平面图的面积。
换句话说，可以借助于上述配置使包括其上安装有两个矩形的半导体芯片和多个片状部件9(两个半导体芯片被平放地安装)的布线衬底1以及盖子7的BGA5的安装面积最小化。
接下来，下面将说明本实施例的变型。
图10是示出根据实施例的第一变型的半导体装置的结构的截面图。图11是示出根据第一比较示例的半导体装置的结构的截面图。图12是示出根据实施例的第二变型的半导体装置的结构的截面图。图13是示出根据第二比较示例的半导体装置的结构的截面图。
图10中示出的第一变型具有包括薄结构的存储器芯片3的结构(如果第一变型包括薄结构的控制芯片2而不是薄结构的存储器芯片3也行)。
公知的是，减少嵌入有数字电路的半导体芯片的厚度作为用于减少从这个半导体芯片产生的噪声的手段是有效的。具体而言，通过减小半导体芯片的厚度使得半导体的截面积小，使得半导体芯片的电阻值变大并且从半导体芯片产生的噪声的移动被阻碍。
这里，图11中示出的第一比较示例的BGA20具有装备有薄结构的存储器芯片3的结构(如果第一比较示例具有装备有薄结构的控制芯片2而不是薄结构的存储器芯片3的结构也行)。在该情况下，因为存储器芯片3是薄结构的芯片，所以布置在存储器芯片3之上的盖子7的安装高度降低，结果是可能发生盖子7接触安装在布线衬底1上的片状部件9中的一个或更多个的缺陷。
为了解决上述问题，图10中示出的第一变型的BGA14以使得硅通孔3e被形成在薄的存储器芯片3上并且其它薄的存储器芯片15被堆积在存储器芯片3之上且在其之间具有硅通孔3e的方式被配置。
由于存储器芯片3和15的上述配置，盖子7可以被布置在更高位置处。
换句话说，BGA14具有其中薄的存储器芯片15被堆积在其上形成有多个硅通孔3e的存储器芯片3之上的结构，这使得盖子7能够被布置在比在其处布置图11中示出的BGA20的盖子7的位置更高的位置处。因此变得可以防止盖子7接触片状部件9中的一个或更多个，并且可以阻碍噪声的产生。
这里，上部存储器芯片15经由树脂粘合剂17被物理地接合到下部存储器芯片3，并且经由硅通孔3e和凸块18被电气接合到下部存储器芯片3。
如根据上述实施例的BGA5的情况一样，根据第一变型的BGA14也具有它的安装面积可以被减少的优点。
作为存储器芯片15的代替，伪(dummy)芯片、间隔物等可以被堆积在存储器芯片3之上。
接下来，图12中示出的第二变型具有形成为使得盖子7的高度高的结构。
换句话说，作为用于减少从嵌入有数字电路的半导体芯片产生的噪声的手段，将作为片状电容器的片状部件9的高度设定为较大(较高)是用于增强噪声去除效果的有效的方式。
此外，虽然图13所示出的根据第二比较示例的BGA21具有其中通过将片状部件9的尺寸(高度)设定为较大(较高)以便增强噪声去除效果而使得作为片状电容器的片状部件9的容量大的结构，但是，因为使得片状部件9的高度高，所以可能发生在存储器芯片3上布置的盖子7接触在布线衬底1上安装的片状部件9中的一个或更多个的缺陷。
因此，图12中示出的第二变型的BGA16被配置为使得硅通孔3e被形成在存储器芯片3上，其它薄的存储器芯片15被堆积在存储器芯片3之上，盖子7被布置在更高位置处并且另外使得盖子7的高度更高。
换句话说，BGA16具有其中其它薄的存储器芯片15被堆积在其上形成有硅通孔3e的存储器芯片3之上的结构，这使得盖子7能够被布置在比在其处布置图13所示出的BGA21的盖子7的位置更高的位置处。另外，使得盖子7的高度更高，因此变得可以防止盖子7接触片状部件9中的一个或更多个，并且可以增强噪声去除效果。
这里，如第一变型的情况一样，上部存储器芯片15经由树脂粘合剂17被物理地接合到下部存储器芯片3，并且经由硅通孔3e和凸块18被电气接合到下部存储器芯片3。
此外，如根据上述实施例的BGA5的情况一样，根据第二变型的BGA16也具有它的安装面积可以被减少的优点。
此外，作为存储器芯片15的代替，伪芯片、间隔物等可以被堆积在存储器芯片3之上。
虽然已经基于本发明的实施例描述了由发明人作出的本发明，但是不用说本发明不限于本发明的上述实施例，并且可以在不背离本发明的范围和精神的情况下进行各种修改。
例如，在上述实施例中，虽然已经在防止底部填料(树脂剂)6扩散的树脂扩散防止部是凹槽1j和1k的假设之下进行了描述，但是上述树脂扩散防止部不限于凹槽1j和1k，并且由阻焊膜等形成的凸的坝可以被使用来代替凹槽1j和1k。
然而，如果采用在安装芯片之后借助于喷嘴滴下底部填料6的方法，则因为存在凸的坝阻碍喷嘴移动的可能性，所以优选的是由布线衬底1上的凹陷部分形成的凹槽被用作树脂扩散防止部。
此外，在上述的实施例中，虽然已经在布线衬底1的上表面1a的形状是正方形的假设之下进行了描述，但是布线衬底1的上表面1a的形状并不总是必须是正方形。换句话说，如果上表面1a的形状(布线衬底1的平面图的形状)是接近正方形的矩形也是可以的。
在布线衬底1的上表面1a的形状为接近正方形的矩形的情况下，通过布置控制芯片2和存储器芯片3使得控制芯片2的长边2aa和2ab以及存储器芯片3的长边3aa和3ab变得平行于这个上表面1a的长边，半导体装置的安装面积可以被减少。
然而，在具有其中两个矩形的半导体芯片和多个片状部件9被安装在布线衬底上(两个半导体芯片被平放地布置)并且盖子7被安装的结构的半导体装置中，期望的是使得布线衬底1的上表面1a的形状为正方形以便使半导体装置的安装面积最小化。
此外，在上述的实施例中，虽然已经在假设半导体装置是例如安放在BGA封装体中的半导体的情况下进行了描述，但是可以设想半导体装置被例如安放在具有安装在布线衬底1的下表面1b上并且导电部件被固定到其每个的表面的多个连接盘1d的LGA(平面网格阵列(land grid array))封装体中。在半导体装置被安放在LGA中的情况下，片状部件9不一定被安装在布线衬底1的下表面1b上。

Claims (15)

1.一种半导体装置，包括：
第一半导体芯片，具有第一主表面和与第一主表面相对的第一背面，第一主表面被形成为矩形形状；
第二半导体芯片，具有第二主表面和与第二主表面相对的第二背面，第二主表面被形成为矩形形状；
布线衬底，具有第一表面和与第一表面相对的第二表面，第一半导体芯片和第二半导体芯片经由多个突出电极分别安装在第一表面上，第一表面被形成为四角形形状，所述四角形形状具有彼此相对地布置的一对第一边和彼此相对地布置的一对第二边；
覆盖部件，被布置在布线衬底的第一表面上并且覆盖第一半导体芯片和第二半导体芯片，
其中第一半导体芯片的第一主表面和第二半导体芯片的第二主表面分别与布线衬底的第一表面相对地布置，
其中第一半导体芯片的第一主表面的长边以及第二半导体芯片的第二主表面的长边被布置为基本上平行于布线衬底的第一表面的第一边，
其中，所述覆盖部件包括分别沿着布线衬底的第一表面的第一边布置的一对第一边檐以及分别沿着布线衬底的第一表面的第二边布置的一对第二边檐，以及
其中第二边檐的宽度比第一边檐的宽度更宽。
2.根据权利要求1所述的半导体装置，其中布线衬底的第一表面是正方形的。
3.根据权利要求2所述的半导体装置，其中多个片状部件被安装在安装于布线衬底的第一表面上的第一半导体芯片和第二半导体芯片的各个短边的外侧。
4.根据权利要求3所述的半导体装置，其中覆盖部件的第二边檐和布线衬底的第一表面经由粘合剂彼此接合。
5.根据权利要求4所述的半导体装置，其中覆盖部件的第一边檐和布线衬底的第一表面被布置为在第一边檐和第一表面之间具有空间。
6.根据权利要求1所述的半导体装置，其中第一半导体芯片与布线衬底之间的空间以及第二半导体芯片与布线衬底之间的空间分别用树脂填充。
7.根据权利要求6所述的半导体装置，其中树脂扩散防止部被形成在安装于布线衬底的第一表面上的第一表面半导体芯片和第二半导体芯片之间的区域上。
8.根据权利要求7所述的半导体装置，其中树脂扩散防止部被形成在安装于布线衬底的第一表面上的第一表面半导体芯片和第二半导体芯片中的任意一个与片状部件之间的区域上。
9.根据权利要求8所述的半导体装置，其中树脂扩散防止部为凹槽。
10.根据权利要求1所述的半导体装置，其中第一半导体芯片的第一背面和第二半导体芯片的第二背面经由导热粘合剂或焊料剂分别接合到覆盖部件。
11.根据权利要求1所述的半导体装置，其中覆盖部件由金属板组成。
12.根据权利要求1所述的半导体装置，其中多个外部连接端子和多个片状部件被安装在布线衬底的第二表面上。
13.根据权利要求12所述的半导体装置，其中外部连接端子的距离布线衬底的第二表面的各个高度高于安装在第二表面上的片状部件的距离第二表面的高度。
14.根据权利要求1所述的半导体装置，其中第一半导体芯片为控制芯片，第二半导体芯片为存储器芯片，并且存储器芯片由控制芯片控制。
15.根据权利要求3所述的半导体装置，其中各个片状部件为片状电容器，并且安装在布线衬底的第二表面上的外部连接端子为球电极。
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