CN104081885B - 元器件内置基板 - Google Patents

元器件内置基板 Download PDF

Info

Publication number
CN104081885B
CN104081885B CN201380004107.7A CN201380004107A CN104081885B CN 104081885 B CN104081885 B CN 104081885B CN 201380004107 A CN201380004107 A CN 201380004107A CN 104081885 B CN104081885 B CN 104081885B
Authority
CN
China
Prior art keywords
built
component
sheet material
mount device
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201380004107.7A
Other languages
English (en)
Other versions
CN104081885A (zh
Inventor
乡地直树
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Publication of CN104081885A publication Critical patent/CN104081885A/zh
Application granted granted Critical
Publication of CN104081885B publication Critical patent/CN104081885B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10Inductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6616Vertical connections, e.g. vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6661High-frequency adaptations for passive devices
    • H01L2223/6672High-frequency adaptations for passive devices for integrated passive components, e.g. semiconductor device with passive components only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/4617Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

为了能以更高的密度将表面安装元器件安装到多层基板表面,本发明的元器件内置基板(1)包括:在规定方向上层叠多个热塑性片材而成的多层基板(2);内置于多层基板(2)的内置元器件(3);以及利用凸点(33)安装于多层基板(2)表面的表面安装元器件(31),表面安装元器件(31)配置成从规定方向俯视时,表面安装元器件(31)与所述内置元器件(3)的轮廓线相交,且该表面安装元器件(31)的凸点(33)不与该内置元器件(3)的轮廓线相交。

Description

元器件内置基板
技术领域
本发明涉及一种元器件内置基板,该元器件内置基板包括内置于由热塑性材料构成的多层基板的内置元器件、以及安装在其表面的表面安装元器件。
背景技术
以往,作为这种元器件内置基板,存在有例如下述专利文献1所记载的元器件内置基板。该元器件内置基板包括多层基板。多层基板内埋设有作为内置元器件的陶瓷电容器,在该多层基板表面(具体而言为上表面)规定有元件搭载区域,该元件搭载区域位于内置元器件的正上方。元件搭载区域设置为从层叠方向俯视时包含在内置元器件的轮廓线内。该元件搭载区域中形成有由导体图案等构成的端子连接部,并安装有表面安装元器件。
现有技术文献
专利文献
专利文献1:日本专利特开2006-310544号公报
发明内容
发明所要解决的技术问题
然而,若如上述那样设置元件搭载区域,则会存在难以在多层基板表面上高密度地配置表面安装元器件的问题。
因此,本发明的目的在于提供一种能以更高的密度在多层基板表面安装表面安装元器件的元器件内置基板。
解决技术问题所采用的技术方案
为实现上述目的,本发明的一个方面在于一种元器件内置基板,其特征在于,包括:在规定方向上层叠多个热塑性片材而成的多层基板;内置在所述多层基板中的内置元器件;以及利用凸点安装于所述多层基板的表面的表面安装元器件,所述表面安装元器件配置成从所述规定方向俯视时,所述表面安装元器件与所述内置元器件的轮廓线相交,且该表面安装元器件的凸点距离该内置元器件的轮廓线50μm以上。
发明效果
根据上述方面,能提供一种能以更高的密度将表面安装元器件安装于多层基板表面的元器件内置基板。
附图说明
图1是本发明的一个实施方式所涉及的元器件内置基板的纵向剖视图。
图2A是表示图1的元器件内置基板的制造方法的最初工序的示意图。
图2B是表示图2A的下一工序的示意图。
图2C是表示图2B的下一工序的示意图。
图2D是表示图2C的下一工序的示意图。
图2E是表示完成后的元器件内置基板的纵向剖视图。
图3是表示多层基板中表面安装元器件的配置关系的示意图。
图4是表示内置元器件的侧面到凸点的X轴方向距离的图。
图5是表示压接前的内置元器件的侧面与空腔外缘的距离的图。
图6是表示内置元器件侧面到凸点的X轴方向距离所对应的不良率的曲线图。
图7A是表示表面安装元器件与轮廓线相交、且凸点距离轮廓线50μm以上时的第一示例的俯视图。
图7B是表示表面安装元器件与轮廓线相交、且凸点距离轮廓线50μm以上时的第二示例的俯视图。
图7C是表示表面安装元器件与轮廓线相交、且凸点设置在距离轮廓线不足50μm的范围内时的第一示例的俯视图。
图7D是表示表面安装元器件与轮廓线相交、且凸点设置在距离轮廓线不足50μm的范围内时的第二示例的俯视图。
图8是变形例所涉及的元器件内置基板的纵向剖视图。
具体实施方式
(引言)
首先,对图中的X轴、Y轴以及Z轴进行说明。X轴、Y轴及Z轴彼此正交。Z轴表示热塑性片材的层叠方向。为便于说明,将Z轴的负方向侧以及正方向侧设为下侧以及上侧。此外,X轴表示热塑性片材的左右方向。特别地,将X轴的正方向侧以及负方向侧设为右侧以及左侧。此外,Y轴表示热塑性片材的前后方向。特别地,将Y轴的正方向侧以及负方向侧设为后方向以及前方向。
(实施方式所涉及的元器件内置基板的结构)
图1是表示本发明的实施方式1所涉及的元器件内置基板的纵向截面的图。图1中,元器件内置基板1包括多层基板2、至少一个内置元器件3、多个图案导体5、多个通孔导体6、以及多个外部电极7。此外,该元器件内置基板1包括多个表面安装型元器件(以下称为表面安装元器件)31。
多层基板2是由多个热塑性片材8(图中为第一到第六热塑性片材8a~8f)构成的层叠体,优选为具有柔性。片材8a~8f由具有电绝缘性的可挠性材料(例如聚酰亚胺、液晶聚合物等热塑性树脂)构成。液晶聚合物由于高频特性优异且吸水性较低,因此优选作为片材8a~8f的材料。此外,各片材8a~8f具有从Z轴正方向侧俯视时彼此相同的矩形形状,并具有10~100[μm]左右的厚度。
在将元器件内置基板1安装于母基板(未图示)时,在多个片材8a~8f中片材8a最接近母基板。在该片材8a的下表面上以与母基板上的连接盘电极的位置相匹配的方式形成有由铜等导电性材料构成的多个外部电极7。
此外,片材8a上形成有多个通孔导体6。各通孔导体6例如由锡以及银的合金等导电性材料构成。这些通孔导体6用于使由内置元器件3和表面安装元器件31构成的电子电路与母基板的连接盘电极进行电连接,形成为在Z轴方向上贯穿片材8a。另外,图1中为了使附图清晰,仅对一部分通孔导体6标注了参照标号。
片材8b层叠在片材8a的Z轴的正方向侧的主面上。该片材8b的Z轴负方向侧的主面上形成有由铜等导电性材料构成的图案导体5。图案导体5用于经由至少一个通孔导体6与内置元器件3的外部电极4(后述)、片材8c的图案导体5等电连接。此外,片材8b上也形成有上述同样的通孔导体6。
片材8c、8d层叠在片材8b、8c的Z轴正方向侧的主面上。该片材8c、8d的Z轴正方向侧的主面上形成有多个图案导体5,用于与各表面安装元器件31以及母基板的连接盘电极电连接。此外,片材8c、8d上也形成有上述同样的通孔导体6。此外,在从Z轴方向俯视(以下称为顶面视)时,在片材8c、8d的中央部分形成有用于收纳后述的内置元器件3的空腔C1、C2。
片材8e层叠在片材8d的Z轴正方向侧的主面上,将空腔C2的开口封住。片材8e的Z轴正方向侧的主面上形成有图案导体5,该图案导体5经由片材8f的通孔导体6使表面安装元器件31与母基板的连接盘电极电连接。此外,片材8e上也形成有上述同样的多个通孔导体6。
片材8f层叠在片材8e的Z轴正方向侧的主面上。片材8f的Z轴正方向侧的主面上形成有表面安装元器件31的安装所使用的连接盘电极35作为图案导体5的一个示例。此外,片材8f上也形成有多个通孔导体6。多个通孔导体6形成在片材8f的连接盘电极35的正下方,使得在Z轴方向上贯穿该片材8f。
内置元器件3例如是天线线圈。该天线线圈包含以下公知的结构,即:在铁氧体基板表面或内部具有以与X轴(或Z轴)平行的轴为中心卷绕成螺旋状的线圈。此外,内置元器件3的下表面设有多个外部电极4。多个外部电极4与形成在片材8b上的通孔导体6接合,并经由通孔导体6与片材8b的图案导体5电连接。内置元器件3在制造时收纳在空腔C1、C2中。因此,空腔C1、C2的尺寸比内置元器件3稍大。
另外,本实施方式中,将内置元器件3设为天线线圈来进行说明。然而,内置元器件3并不限于此,也可以是IC芯片、或其它无源元器件。
此外,表面安装元器件31利用设置在自身表面的端子电极上的凸点33安装到形成于多层基板2的Z轴正方向侧的主面的连接盘电极35上。本实施方式中,作为表面安装元器件31,举例示出了13.56MHZ频带的NFC(Near Field Communication:近场通信)中所使用的RFIC芯片31a以及与上述内置元器件3一同构成谐振电路的贴片电容器31b。
多个图案导体5基本上形成在多层基板2内,用作为布线导体。此外,在如本实施方式那样将表面安装元器件31安装于多层基板2的情况下,在多层基板2的表面也形成图案导体5作为连接盘电极35。另外,图案导体5不限于布线导体、连接盘电极35,也可以是用于形成电容器、线圈的图案导体。
以上说明的内置元器件3与表面安装元器件31通过图案导体5以及通孔导体6连接,构成规定的电子电路。该电子电路在本实施方式中由RFIC芯片31a以及与其相连接的谐振电路构成。谐振电路是与RFIC芯片31a并联连接的内置元器件(即天线线圈)3以及贴片电容器31b。
(元器件内置基板的制造方法)
接着,参照图2A~图2E对元器件内置基板1的制造方法进行说明。以下说明一个元器件内置基板1的制造过程,但实际上通过对大型片材进行层叠以及切割能同时制造大量的元器件内置基板1。
首先,准备所需片数的在表面的大致整个区域上形成有铜箔的大型片材。该大型片材在元器件内置基板1完成后成为任一片材8。为了制作图1的元器件内置基板1,准备与片材8a~8f相对应的大型片材9a~9f(参照图2A)。此外,各片材9a~9f是具有10~100[μm]左右的厚度的液晶聚合物。另外,铜箔的厚度例如为6~35[μm]。另外,铜箔的表面优选用锌等进行电镀以防生锈,并进行平坦化。
接着,通过光刻工序去除不需要部分的铜箔,从而如图2A所示,在至少一个片材9a的一个面(例如下表面)上形成多个外部电极7。此外,同样地在片材9b的一个面(例如下表面)上形成图案导体5。同样地,在大型片材9c~9f的一个面(例如Z轴正方向侧的主面)上也形成图案导体5。
接着,如图2B所示,在片材9a上从未形成外部电极7的一面侧向要形成通孔导体6的位置照射激光束。由此,形成未贯穿外部电极7,而贯穿片材9a的贯通孔,之后在各贯通孔中填充导电性糊料。
此外,在片材9b上,从未形成图案导体5的一面侧向要形成通孔导体6的位置照射激光束。向由此形成的各贯通孔填充导电性糊料。同样地,在片材9c~9f的规定位置也形成贯通孔,并向各贯通孔填充导电性糊料。
接着,如图2C所示,将内置元器件3定位在图9e的未形成图案导体5的面上。然后,利用磨具对各片材9c、9d的规定区域进行冲压加工,形成贯通孔C1、C2。另外,也可以使用贯通孔C1、C2来对内置元器件3进行定位。该情况下,内置元器件3插入到贯通孔C1、C2中。
接着,如图2D所示,按从下到上的顺序层叠片材9a~9f。这里,以片材9a的形成有外部电极7的形成面朝向Z轴负方向侧的状态,且片材9b的形成有图案导体5的形成面朝向Z轴负方向侧的状态进行层叠。此外,以片材9c~9f的形成有图案导体5的形成面朝向Z轴正方向侧的状态进行层叠。
之后,从Z轴的两个方向向层叠的片材9a~9f施加热和压力。通过该加热和加压使片材9a~9f软化、从而进行压接并成为一体。同时,使各通孔内的导电性糊料固化,由此形成通孔导体6。
此外,通过回流等,利用凸点33将表面安装元器件31安装到片材9f的连接盘电极35上,之后将一体化后的片材9a~9f切割成规定尺寸,由此完成图2E所示的元器件内置基板1。
(表面安装元器件的安装性)
在利用凸点33将表面安装元器件31安装于多层基板2的情况下,其安装性会受到多层基板2中凸点33正下方部分的平滑性的影响。这里,在回流时等,由于压接后的热量,可能会使多层基板2表现出可塑性。
此外,本申请发明人研究后发现,在将内置元器件3内置于多层基板2的情况下,可知以下(1)、(2)两点。
(1)在内置元器件3的侧面(更具体而言,与Z轴大致平行的侧面)附近,可能会由于空腔C1、C2的影响而导致热塑性树脂的填充不充分。
(2)热塑性树脂容易沿着内置元器件3的侧面在Z轴方向滑动。
这里,已知:若假设将表面安装元器件31配置成在顶面视时,表面安装元器件31的凸点33与内置元器件3的轮廓线相交,则表面安装元器件31自身的重量会施加给凸点33正下方的部分,在内置元器件3的侧面附近,由于热塑性树脂的填充不充分,且热塑性树脂容易沿着内置元器件3的侧面向Z轴方向滑动,因此容易在凸点33的正下方及其附近产生凹陷,从而容易发生表面安装元器件31的接合不良、安装不良。
为此,在本元器件内置基板1中,首先,为了以更高的密度将多个表面安装元器件31安装到多层基板2表面上的空间内,如图3所示,在顶面视时,表面安装元器件31配置成不包含在轮廓线L内,而与内置元器件3的轮廓线L相交。更具体而言,配置成在顶面视时,表面安装元器件夹着轮廓线L与内置元器件3的内侧以及外侧这两侧相交。除此以外,明确了若如图3所示,在顶面视时,表面安装元器件31的凸点33不与内置元器件3的轮廓线L相交,且凸点33距离内置元器件3的轮廓线L50μm,则能降低接合不良。
本申请发明人为了验证上述这种表面安装元器件31的配置效果,进行了下述测定。具体而言,测定从内置元器件3的侧面(轮廓线L)到凸点33的X轴方向距离x(参照图4)所对应的不良率。这里,在x为0的时,意味着在顶面视时,凸点33与内置元器件3的轮廓线L相交。此外,分别在压接前的内置元器件3的侧面与空腔C1、C2外边缘的距离d(参照图5)为100μm、150μm、200μm的条件下实施该测定。其测定结果如图6所示。图6中,d=100μm时的不良率由◆表示,d=150μm时的不良率由■表示,d=200μm时的不良率由▲表示。由这些测定结果可知,若凸点33与内置元器件3的轮廓线L距离50μm,则不论d的值为多少,不良率均会大幅降低到约20%以下。
这里,图7A、图7B示出在顶面视时、表面安装元器件31与内置元器件3的轮廓线L相交、而凸点33与内置元器件3的轮廓线L隔开50μm以上时的示例,该情况下,能有效利用多层基板2表面上的空间,且能降低接合不良。与此相对,图7C、图7D示出了在顶面视时、表面安装元器件31与内置元器件3的轮廓线L相交、而凸点33设置在距离内置元器件3的轮廓线L不足50μm的范围内时的示例,此时没有起到上述技术效果。
(变形例)
在图1的示例中,将内置元器件3设作为天线线圈进行了说明。然而并不限于此,如图8所示,内置元器件3可以单单是铁氧体,利用图案导体5以及通孔导体6在该铁氧体周围形成线圈。另外,图8中为了便于图示,用虚线箭头示出了通孔导体6。
工业上的实用性
本发明所涉及的元器件内置基板适用于能以更高的密度将表面安装元器件安装于多层基板表面的例如智能手机那样的电子设备等。
标号说明
1 元器件内置基板
2 多层基板
3 内置元器件
31 表面安装基板
33 凸点
35 连接盘电极

Claims (2)

1.一种元器件内置基板,其特征在于,包括:
在规定方向上层叠多个热塑性片材而成的多层基板;
内置在所述多层基板中的内置元器件;以及
利用凸点安装于所述多层基板表面的表面安装元器件,
所述表面安装元器件配置成从所述规定方向俯视时,所述表面安装元器件与所述内置元器件的轮廓线相交,且该表面安装元器件的凸点中的不与所述内置元器件重叠的凸点距离该内置元器件的所有轮廓线50μm以上。
2.如权利要求1所述的元器件内置基板,其特征在于,
所述热塑性片材由液晶聚合物构成。
CN201380004107.7A 2012-12-26 2013-11-08 元器件内置基板 Active CN104081885B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2012282059 2012-12-26
JP2012-282059 2012-12-26
PCT/JP2013/080253 WO2014103530A1 (ja) 2012-12-26 2013-11-08 部品内蔵基板

Publications (2)

Publication Number Publication Date
CN104081885A CN104081885A (zh) 2014-10-01
CN104081885B true CN104081885B (zh) 2017-12-08

Family

ID=51020629

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201380004107.7A Active CN104081885B (zh) 2012-12-26 2013-11-08 元器件内置基板

Country Status (4)

Country Link
US (1) US9484397B2 (zh)
JP (1) JP5574071B1 (zh)
CN (1) CN104081885B (zh)
WO (1) WO2014103530A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016047446A1 (ja) * 2014-09-26 2016-03-31 株式会社村田製作所 積層モジュール用基板、積層モジュールおよび積層モジュールの製造方法
CN106207383A (zh) * 2015-05-06 2016-12-07 佳邦科技股份有限公司 通信模组
CN107615894B (zh) * 2015-06-03 2020-07-17 株式会社村田制作所 元器件安装基板
CN210124036U (zh) * 2016-08-23 2020-03-03 株式会社村田制作所 树脂多层基板
JP2018032848A (ja) * 2016-08-25 2018-03-01 株式会社村田製作所 半導体装置
JP6497487B2 (ja) 2016-12-02 2019-04-10 株式会社村田製作所 多層配線基板
EP3755127A1 (en) * 2019-06-18 2020-12-23 GN Hearing A/S A printed circuit board (pcb) module comprising an embedded radiofrequency semiconductor die

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101653053A (zh) * 2008-01-25 2010-02-17 揖斐电株式会社 多层线路板及其制造方法
CN102215637A (zh) * 2010-04-02 2011-10-12 株式会社电装 嵌有半导体芯片的布线基片的制造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4243922B2 (ja) * 2001-06-26 2009-03-25 イビデン株式会社 多層プリント配線板
JP4298559B2 (ja) * 2004-03-29 2009-07-22 新光電気工業株式会社 電子部品実装構造及びその製造方法
US7218007B2 (en) * 2004-09-28 2007-05-15 Intel Corporation Underfill material to reduce ball limiting metallurgy delamination and cracking potential in semiconductor devices
JP4718890B2 (ja) 2005-04-28 2011-07-06 日本特殊陶業株式会社 多層配線基板及びその製造方法、多層配線基板構造体
KR100770874B1 (ko) * 2006-09-07 2007-10-26 삼성전자주식회사 매설된 집적회로를 구비한 다층 인쇄회로기판
KR100819278B1 (ko) * 2006-11-22 2008-04-02 삼성전자주식회사 인쇄회로 기판 및 그 제조 방법
JP2009141169A (ja) * 2007-12-07 2009-06-25 Shinko Electric Ind Co Ltd 半導体装置
US8618669B2 (en) * 2008-01-09 2013-12-31 Ibiden Co., Ltd. Combination substrate
JPWO2011121993A1 (ja) * 2010-03-30 2013-07-04 株式会社村田製作所 部品集合体
US8669651B2 (en) * 2010-07-26 2014-03-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structures with reduced bump bridging
JP2012151372A (ja) * 2011-01-20 2012-08-09 Ibiden Co Ltd 配線板及びその製造方法
US9905524B2 (en) * 2011-07-29 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures in semiconductor device and packaging assembly
US8698308B2 (en) * 2012-01-31 2014-04-15 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structural designs to minimize package defects
JP5967028B2 (ja) * 2012-08-09 2016-08-10 株式会社村田製作所 アンテナ装置、無線通信装置およびアンテナ装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101653053A (zh) * 2008-01-25 2010-02-17 揖斐电株式会社 多层线路板及其制造方法
CN102215637A (zh) * 2010-04-02 2011-10-12 株式会社电装 嵌有半导体芯片的布线基片的制造方法

Also Published As

Publication number Publication date
US20140264737A1 (en) 2014-09-18
CN104081885A (zh) 2014-10-01
JP5574071B1 (ja) 2014-08-20
US9484397B2 (en) 2016-11-01
JPWO2014103530A1 (ja) 2017-01-12
WO2014103530A1 (ja) 2014-07-03

Similar Documents

Publication Publication Date Title
CN104081885B (zh) 元器件内置基板
CN206727226U (zh) 天线装置以及电子设备
US9974165B2 (en) Electronic component-embedded module and communication terminal device
CN103460822A (zh) 芯片元器件内置树脂多层基板及其制造方法
CN107887109A (zh) 表面安装在电路板的电子部件
CN105027692B (zh) 元器件内置多层基板的制造方法以及元器件内置多层基板
US20090173793A1 (en) Ic module, ic inlet, and ic mounted body
CN102231382B (zh) 图像传感器的陶瓷封装及其封装方法
US9560766B2 (en) Circuit board and method for producing same
CN205093051U (zh) 部件内置基板以及通信模块
CN104051405A (zh) 嵌埋有电子组件的线路板结构及其制法
CN204466070U (zh) 电路基板
CN204518238U (zh) 部件内置基板以及通信终端装置
CN204425772U (zh) 多层基板
CN209517682U (zh) 多层基板
CN206759827U (zh) 部件内置基板
CN206388849U (zh) 天线装置以及电子设备
JP6003532B2 (ja) 部品内蔵基板およびその製造方法
CN208188872U (zh) 元器件内置装置及rfid标签
CN206293432U (zh) 连接元件、以及半导体元件相对于安装基板的安装结构
KR101628904B1 (ko) Nfc 안테나 구조체 및 이를 포함하는 배터리 보호회로 패키지
CN105225792A (zh) 磁性构件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant