CN104051266B - 用于鳍式场效应晶体管的鳍形状及其形成方法 - Google Patents

用于鳍式场效应晶体管的鳍形状及其形成方法 Download PDF

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CN104051266B
CN104051266B CN201310329355.0A CN201310329355A CN104051266B CN 104051266 B CN104051266 B CN 104051266B CN 201310329355 A CN201310329355 A CN 201310329355A CN 104051266 B CN104051266 B CN 104051266B
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gate electrode
effect transistor
field effect
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dielectric layer
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CN104051266A (zh
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林志忠
林志翰
张铭庆
陈昭成
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了鳍式场效应晶体管（finFET）和形成方法。在一个或多个鳍上方形成栅电极。在栅电极的端部中沿着栅电极的基底形成沟槽。可选地，可以使诸如浅沟道隔离件的下面的介电层凹进到沟槽下方，从而减少间隙填充问题。本发明还提供了用于鳍式场效应晶体管的鳍形状及其形成方法。

Description

用于鳍式场效应晶体管的鳍形状及其形成方法
相关申请的交叉引用
本申请为非临时申请，且本申请要求于2013年3月11日提交的标题为“Fin ShapeFor Fin Field-Effect Transistors And Method Of Forming”的美国专利申请第61/776,515号的优先权以及2013年3月15日提交的标题为“Fin Shape For Fin Field-EffectTransistors And Method Of Forming”的美国专利申请第61/788,345号的优先权，其全部内容结合于此作为参考。
技术领域
本发明一般地涉及半导体技术领域，更具体地，涉及鳍式场效应晶体管及其形成方法。
背景技术
金属氧化物半导体场效应晶体管（MOSFET）技术是用于超大尺寸集成（ULSI）电路制造的主要半导体技术。在过去几十年中，MOSFET的尺寸减小对速度、性能、电路密度以及每个单元功能件的成本均提供了持续的改善。由于传统块状MOSFET栅极长度的减小，源极和漏极与沟道相互作用逐渐增大且增加了对沟道电势的影响。因此，具有短栅极长度的晶体管所具有的问题涉及栅极实质上无法控制沟道的导通状态和截止状态。
诸如与具有短沟道长度的晶体管相关联的减小的栅极控制的现象被称为短沟道效应。增加主体掺杂浓度、减小栅极氧化层厚度以及超浅源极/漏极结（ultra-shallowsource/drain junction）是抑制短沟道效应的方法。然而，为了将器件的尺寸缩小至30nm以下的形态，正在研究包括使用鳍式场效应晶体管（finFET）的方法以改善短沟道效应。
通常，finFET包括具有一个或多个凸起沟道区域的凸起的源极/漏极区域（被称为鳍）。在鳍上方形成栅介电层和栅电极。已经发现，finFET根据设计需要的收缩以及更好的短沟道控制提供改善的可伸缩性（scalability）。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种形成鳍式场效应晶体管（finFET）的方法，所述方法包括：提供衬底，所述衬底具有从其延伸的鳍；在相邻鳍之间形成第一介电层；在所述鳍和所述介电层上方形成栅电极层；以及将所述栅电极层图案化为多个栅电极，其中，所述多个栅电极的端部具有沿底部边缘的沟槽。
该方法进一步包括：在所述多个栅电极的所述沟槽下方的所述介电层中形成凹口。
在该方法中，利用CHF3、CH3F、CF4、CH2F2、SF6或O2的工艺气体，至少部分地使用干蚀刻来形成所述凹口。
在该方法中，利用HF、NH3或H2O的工艺气体以及N的载气，至少部分地使用干蚀刻来形成所述凹口。
在该方法中，所述多个栅电极中的两个栅电极端部与端部对齐，并且所述方法进一步包括在所述两个栅电极的所述沟槽的下方形成凹口。
该方法进一步包括：在凹进的所述两个栅电极之间的所述介电层中形成所述凹口，使得所述两个栅电极的所述沟槽下方的所述凹口形成从一个沟槽下方延伸到另一沟槽下方的单个连续凹口。
在该方法中，至少部分地使用干蚀刻工艺形成所述多个栅电极中的所述沟槽。
在该方法中，所述干蚀刻工艺利用CHF3、CF4、CH2F2、SF6或O2的工艺气体。
根据本发明的另一方面，提供了一种形成鳍式场效应晶体管（finFET）的方法，所述方法包括：提供具有横向对齐的至少两个鳍的衬底；在所述两个鳍的端部之间形成第一介电层；至少在第一鳍上方形成第一栅电极并且至少在第二鳍上方形成第二栅电极，所述第一栅电极和所述第二栅电极的纵轴对齐；在所述第一栅电极的朝向所述第二栅电极的端部中形成第一沟槽；以及在所述第二栅电极的朝向所述第一栅电极的端部中形成第二沟槽。
该方法进一步包括：在所述第一栅电极和所述第二栅电极之间形成第二介电层。
在该方法中，所述第二介电层延伸至所述第一沟槽和所述第二沟槽中。
该方法进一步包括：在所述第一介电层中形成凹口。
在该方法中，所述凹口从所述第一沟槽下方延伸到所述第二沟槽下方。
在该方法中，所述凹口的深度小于约
在该方法中，至少部分地使用干蚀刻工艺形成所述第一沟槽和形成所述第二沟槽。
在该方法中，所述干蚀刻工艺利用CHF3、CF4、CH2F2、SF6或O2的工艺气体。
根据本发明的又一方面，提供了一种鳍式场效应晶体管（finFET），包括：鳍，远离衬底延伸；介电层，紧邻所述鳍；以及栅电极，形成在所述鳍和所述介电层上方，其中，所述栅电极的端部在所述栅电极和所述介电层的界面处具有沟槽。
在该finFET中，所述沟槽的高度小于2000nm。
该finFET进一步包括位于所述沟槽下方的所述介电层中的凹口。
在该finFET中，所述凹口的深度小于约
附图说明
为了更全面地理解本发明及其优势，现将结合附图所进行的以下描述作为参考，其中：
图1A至图1C、图2A至图2C、图3A至图3C、图4A至图4C以及图5A至图5C示出了根据本发明的另一实施例在形成finFET的各种工艺步骤过程中的各个示图；
图6示出了根据实施例的在栅电极中所形成的沟槽的放大图；
图7A至图7F示出了根据实施例的沟槽的各种形状；
图8A至图8F示出了根据实施例的凹口（notch）的各种形状；以及
图9是根据实施例示出的形成finFET的方法的流程图。
具体实施方式
下面，详细讨论本发明优选的示例性实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的发明概念。所讨论的具体的示例性实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。
本发明的实施例提供了用于半导体器件的形成的多种改进的方法以及产生的结构。在下文中论述了在块状硅衬底上形成具有单个鳍或多个鳍的finFET晶体管的实施例。本领域普通技术人员认识到，本发明的实施例可以用于其他结构（诸如omega-FET或具有两个或多个鳍的结构）。
图1A至图5C示出了根据本发明的实施例的形成finFET器件的方法。首先参考图1A至图1C，图1C示出了包括衬底110、鳍112、介电层114、和第一掩模层126的晶圆的俯视图。如图1A和图1B所示，图1A是沿图1C的A-A线所截取的截面图，并且图1B是沿图1C的B-B线所截取的截面图，在栅极绝缘层118和栅电极层120上方形成第一掩模层126。图1A至图1C所示的结构提供了仅用于示例性的目的且可以通过形成finFET的任何合适的方法来形成该结构。
通常，衬底110可以是任何半导体材料且可以包括已知结构，例如可以包括梯度层或埋氧层。在实施例中，衬底110包括可以是非掺杂的或掺杂的（诸如p型、n型或它们的组合）块状硅。也可以使用适用于半导体器件形成的其他材料。诸如锗、石英、蓝宝石以及玻璃的其他材料可以可选地用于衬底110。可选地，硅衬底110可以是绝缘体上半导体（SOI）衬底的有缘层或诸如在块状硅层上所形成的硅锗层的多层结构。
例如，可以使用光刻技术通过图案化和蚀刻衬底110来形成鳍112。通常，光刻胶材料层沉积在衬底110上方。根据期望的图案（此处为鳍112）照射（曝光）光刻胶材料的层且显影以去除光刻胶材料的部分。剩余的光刻胶材料在诸如蚀刻的接下来的工艺步骤中保护下面的材料。应该理解诸如氧化物掩模或氮化硅掩模的其他掩模也可以在蚀刻工艺中使用。
在其他实施例中，可以外延生长鳍112。例如，可以在外延工艺中使用下面的材料的露出部分（诸如衬底110的露出部分）以形成鳍112。在外延生长工艺过程中，可以将掩模用于控制鳍112的形状。
介电层114用作环绕鳍112的浅沟道隔离件（STI），可以通过使用正硅酸乙酯（TEOS）和氧作为前体的化学汽相沉积（CVD）技术来形成该介电层114。在另一实施例中，可以通过将诸如氧、氮、碳等离子注入到硅衬底110内来形成介电层114。在又一实施例中，介电层114是SOI晶圆的绝缘层。
栅极绝缘层118可以是通过在包括O2、H2O、NO或它们的组合的环境中的氧化工艺（诸如湿式热氧化或干式热氧化）、在O2、H2O、NO或它们的组合的环境中的原位蒸汽生成（ISSG）工艺等所形成的氧化层，该栅极绝缘层118防止电子损耗。也可以使用包括高k介电材料的其他材料，诸如HfO2、HfSiO2、ZnO、ZrO2、Ta2O5、Al2O3等，以及诸如原子层沉积（ALD）、原子汽相沉积（AVD）等的其他工艺。
如图1A所示，优选地，栅电极层120包括在鳍112上方沉积的半导体材料，诸如多晶硅、非晶硅等。可以沉积掺杂的或非掺杂的栅电极层120。例如，在实施例中，栅电极层120包括通过低压化学汽相沉积（LPCVD）所沉积的非掺杂的多晶硅。一旦应用，多晶硅就可以掺杂诸如磷离子（或其他P型掺杂物）以形成PMOS器件或掺杂例如硼（或其他N型掺杂物）以形成NMOS器件。可以通过例如原位掺杂多晶硅的炉沉积（furnace deposition）来沉积多晶硅。可选地，栅电极120可以包括例如多晶硅金属合金或包括金属（诸如钨、镍、铝、钽和钛）的金属栅极。
第一掩模层126是保护层，随后对其进行图案化以防止在接下来的工艺（诸如蚀刻或注入步骤）期间去除下面的结构（诸如栅电极层120）。如图1A和图1B所示，一种这样合适的第一掩模层126包括氧化物掩模层122和氮化物掩模层124。氧化物掩模层122可以是通过使用TEOS和氧作为前体的CVD技术所形成的氧化硅层。氮化物层可以是通过使用硅烷和氨作为前体气体的CVD技术所形成的氮化硅，且沉积温度介于550℃和900℃的范围内。氮化物层可以包括其它含氮的层，诸如氮氧化硅SiOxNy、硅肟SiOxNy:Hz或它们的组合。
本领域普通技术人员应该理解，其它掩模材料和/或结构也可以用于形成第一掩模层126。例如，可以使用其他材料、单层、三层或多层等。
图1A至图1C进一步示出了在第一掩模层126上方所形成的第一图案化掩模230以及对其图案化以限定栅电极线。在实施例中，第一图案化掩模230是通过沉积光刻胶材料层、对该光刻胶材料层进行曝光和显影所形成的光刻胶掩模。如在下文中更详细地讨论的，对图案化掩模230进行图案化以在接下来的工艺步骤中形成栅电极线。
现在参考图2A至图2C，（其中图2A和图2B是分别沿着图2C的A-A线和B-B线所截取的截面图）根据实施例示出了图案化的第一掩模层126以限定栅电极线。在实施例中，第一掩模层126包括氮化物掩模层124和氧化物掩模层122，例如，可以使用在磷酸（H3PO4）、氢氟酸等中的湿式浸渍（wet dip）来图案化第一掩模层126。
应该注意，为了示例性目的，在图2A至图2C中未示出诸如光刻胶掩模的第一图案化掩模230。光刻胶掩模或它的部分可以保留。在蚀刻工艺过程中诸如第一掩模层126的硬掩模对下面的区域提供额外的保护。如图2B所示，在第一掩模层126的图案化过程中的蚀刻可以导致栅电极层120的轻微过蚀刻。
如下文中更详细地说明的，使用两个图案化步骤限定栅电极。如上文所讨论的第一图案化步骤形成连续的栅极线。下文中参考图3A至图4C所讨论的第二图案化步骤实施“切割”上文中所限定的栅极线的切割工艺，从而限定栅极线的端部。
图3A至图3C（其中，图3A和图3B是分别沿图3C的A-A线和B-B线所截取的截面图）示出了在第一掩模层126上方形成的第二图案化掩模232以及对第二图案化掩模232进行图案化以限定栅电极端部。在实施例中，第二图案化掩模232为通过沉积光刻胶材料的层、对光刻胶材料的层进行曝光和显影所形成的光刻胶掩模。如下文中更详细地讨论的，对第二图案化掩模232进行图案化以在第一掩模层126中限定栅电极端部。
如图3C所示，对第二图案化掩模232进行图案化以形成在第一掩模层126的多条线上方延伸的线状开口。在其他实施例中，通过第二图案化掩模232所形成的图案可以是一个或多个开口，每个开口都在通过第一掩模层126所形成的一条或多条线上方延伸。例如，在实施例中，通过第一掩模层126所形成的每条线都具有圆形、矩形或在第二图案化掩模232中所形成的其他形状的开口，从而限定线端部。
图4A至图4C（其中，图4A和图4B是分别沿图4C的A-A线和B-B线所截取的截面图）示出了第一掩模层126的第二图案化步骤以限定栅极端部。在实施例中，第一掩模层126包括氮化物掩模层124和氧化物掩模层122，例如，可以使用在磷酸（H3PO4）、氢氟酸等中湿润浸渍来图案化第一掩模层126。应该注意，为了示例性的目的，提供了进行图案化以形成栅电极线然后进行图案化以切割线的顺序。其他实施例可以利用不同的顺序。例如，在其他实施例中，可以颠倒图案化的顺序，使得首先实施图案化栅电极的端部，然后进行图案化以形成栅电极线。
如上文所述，使用两种图案化工艺来图案化第一掩模层126。上文中参考图1和图2所述的第一图案化工艺图案化第一掩模层126以限定栅电极线，以及上文中参考图3和图4所述的第二图案化工艺切割第一掩模层126的栅电极线图案以形成栅极端部。
如图4A所示，在栅极线端部的图案化过程中可以实施过蚀刻。在实施例中，过蚀刻导致在栅电极层120中形成凹口430。在实施例中，栅电极层120的深度T介于约至约之间。在栅极端部的蚀刻过程中所形成的凹口430大于可以在进行蚀刻以形成栅极线（参见图1和图2）的过程中形成的任何凹口。栅极端部区域中的该凹口430在接下来的工艺步骤中有助于在栅极端部形成沟槽，并且下文中将对其进行描述。
应该理解，为了示例性的目的，在图4A至图4C中未示出诸如光刻胶掩模的第二图案化掩模232。诸如第一掩模层126的硬掩模在蚀刻工艺过程中为下面的区域提供额外的保护。可以在图案化第一掩模层126之后去除第二图案化掩模232。
现在，参考图5A至图5C（其中图5A和图5B是分别沿图5C的A-A线和B-B线所截取的截面图），示出了第二蚀刻工艺的结果以完成栅电极层120的蚀刻并且在栅电极线端部形成沟槽558，从而根据实施例形成栅电极432。使用图案化的第一掩模层126（参见图4A-图4C）作为蚀刻掩模来图案化栅电极层120。如图5B所示，栅电极432的侧部的轮廓是相对线性的（在工艺变化内）。相比之下，如图5A所示，在实施例中，在栅电极层120（参见图4A）中所形成的凹口430（参见图4A）允许在栅电极432的端部中形成沟槽558。如图5A至图5C所示，这种布置提供了良好的控制。如图5C所示，可以减小并控制相邻栅极端部之间的间距（例如，作为距离S1），从而减小栅极端部之间的桥接的风险以及栅极泄漏的风险。
图5A和图5B进一步示出了在栅电极432上方和沟槽558中所形成的层间介电层（ILD）560。在实施例中，由诸如磷硅酸盐玻璃（PSG）、硼硅酸盐玻璃（BSG）、掺硼磷硅酸盐玻璃（BPSG）、TEOS等的氧化物形成ILD560。
图6是在图5A所示的栅电极432端部处的缩进区域（indented region）或沟槽的放大图。应该注意，图6示出了栅电极432上所保留的掩模126。如图5A所示，在形成ILD560之前，可以选择性地去除掩模126。沟槽558具有（exhibit）高度H1，在实施例中，H1大于0nm并且小于2000nm。在这种实施例中，栅电极432延伸超过鳍112的距离为第一距离D1，且沟槽558与鳍112的偏移量为第二距离D2。在这种结构中，D1:D2的比率大于1。第二距离可以大于0并且小于第一距离，从而提供与鳍112的接触，也提供沟槽以减小桥接。诸如此类的结构提供从栅电极线端部与栅电极线端部的更长的距离，从而增加工艺窗口并减小泄漏。此外，诸如此类的结构也可以提供用于高k金属栅极间隙填充的更大的工艺窗口。如下文中更详细地讨论的，沟槽区进一步提供介于线端部之间的短距离而仍维持通过介电材料进行充分回填（backfilling）。
图7A至图7F示出了可以用于形成沟槽558的各种形状。通常，可以通过改变诸如工艺气体的类型、工艺气体的浓度、温度、压力等的工艺条件来获得沟槽558的期望形状。
首先参见图7A，形成三角形沟槽。在实施例中，使用诸如CHF3、CF4、CH2F2、SF6、O2等的工艺气体，以及诸如He、Ar等的载气通过干蚀刻工艺来形成三角形沟槽558。实施干蚀刻工艺的温度可以介于约25℃和约80℃之间并且压力可以介于约1mtorr和约20mtorr之间。
图7B示出了形成椭圆形沟槽的实施例。在实施例中，使用诸如CHF3、CF4、CH2F2、SF6、O2等的工艺气体以及诸如He、Ar等的载气通过干蚀刻工艺来形成椭圆形沟槽558。可以在约25℃至约80℃的温度且在约3mtorr至约20mtorr的压力的条件下实施干蚀刻工艺。
图7C示出了形成正方形沟槽的实施例。在实施例中，使用诸如CHF3、CF4、CH2F2、SF6、O2等的工艺气体以及诸如He、Ar等的载气通过干蚀刻工艺形成正方形沟槽558。可以在约25℃至约80℃之间且在约1mtorr至约20mtorr的压力的条件下实施干蚀刻工艺的温度。
图7D示出了形成圆角沟槽的实施例。在实施例中，使用诸如CHF3、CH2F2、SF6、O2等的工艺气体以及诸如He、Ar等的载气通过干蚀刻工艺形成圆角沟槽558。可以在约25℃至约80℃的温度且在约1mtorr和约10mtorr的压力的条件下实施干蚀刻工艺。
图7E示出了形成粗糙或阶梯状沟槽的实施例。在实施例中，使用诸如CF4、CH2F2、SF6等的工艺气体以及诸如He、Ar等的载气通过干蚀刻工艺形成粗糙或阶梯形沟槽558。可以在约40℃至约80℃之间的温度且在约1mtorr至约10mtorr的压力的条件下实施干蚀刻工艺。
图7F示出了形成云状或平滑状沟槽的实施例。在实施例中，使用诸如CF4、SF6等的工艺气体以及诸如He、Ar等的载气通过干蚀刻工艺形成云状或平滑状沟槽558。可以在约40℃至约80℃的温度且在约1mtorr至约10mtorr的压力的条件下实施干蚀刻工艺。
图8A至图8F示出了在可选实施例中可以用于在下面的介电层114中形成凹口的各种形状。应该相信，在一些实施例中，当试图使用诸如ILD560（参见图5A）的介电材料填充沟槽558时，上文中所示的沟槽558可能会出现间隙填充问题。在这些实施例中，期望在栅电极432的端部之间的介电层114中形成凹口。图8A至图8F示出了可以用于在介电层114中形成凹口832的各种形状。在实施例中，凹口832的深度介于约和约之间。
应该理解，图8A至图8F示出了作为三角形沟槽的沟槽558，但也可以使用其他沟槽形状，诸如上文中参考图7A至图7F所讨论的那些沟槽的形状。
在实施例中，将介电层114中的凹口832限定在沟槽区及紧邻栅电极线端部的区域内。在这些实施例中，诸如光刻胶掩模的一个或多个掩模（未示出）可以用于保护介电层114的其他区域而露出紧邻栅电极线端部的介电层114。
首先参见图8A，示出了在介电层114中形成的正方形凹口。在实施例中，使用诸如CHF3、CF4、CH2F2、SF6、O2等的工艺气体以及诸如He、Ar等的载气通过干蚀刻工艺来形成正方形凹口。可以在约25℃至约80℃的温度且在约1mtorr至约20mtorr的压力的条件下实施干蚀刻工艺。
图8B示出了在介电层114中形成各向异性的底部圆角凹口的实施例。在实施例中，使用诸如CHF3、CF4、SF6、O2等的工艺气体以及诸如He、Ar等的载气通过干蚀刻工艺形成底部圆角凹口。可以在约25℃至约80℃的温度且在约3mtorr至约20mtorr的压力的条件下实施干蚀刻工艺。
图8C示出了在介电层114中形成钻石形凹口的实施例。在实施例中，使用诸如CHF3、CF4、CH2F2、O2等的工艺气体以及诸如He、Ar等的载气通过干蚀刻工艺形成钻石形凹口。可以在约25℃至约80℃的温度且在约3mtorr至约20mtorr的压力的条件下实施干蚀刻工艺。
图8D示出了在介电层114中形成梯形或三角形凹口的实施例。在实施例中，使用诸如CHF3、CF4、CH2F2、O2等的工艺气体以及诸如He、Ar等的载气通过干蚀刻工艺形成梯形或三角形凹口。可以在约25℃至约80℃的温度且在约1mtorr至约20mtorr的压力的条件下实施干蚀刻工艺。
图8E示出了在介电层114中形成各向异性的侧壁圆角凹口的实施例。在实施例中，使用诸如CF4、CH2F2、SF6、CH3F、O2等的工艺气体以及诸如He、Ar等的载气通过干蚀刻工艺形成侧壁圆角凹口。可以在约40℃至约80℃的温度且在约1mtorr至约10mtorr的压力的条件下实施干蚀刻工艺。
图8F示出了在介电层114中形成各向同性形（isotropic-shape）凹口的实施例。在实施例中，使用诸如HF、NH3、H2O等的工艺气体以及诸如N等的载气通过干蚀刻工艺形成梯形或各项同性形凹口。可以在约20℃至约300℃的温度且在1个大气压（ATM）的条件下实施干蚀刻工艺。
此后，可以实施额外的工艺以完成器件。例如，可以掺杂栅电极、形成间隔件、可以硅化栅电极的部分、可以形成层间介电（ILD）层或/和金属间介电（IMD）层、可以形成金属化层等。
图9是根据实施例的示出形成finFET的方法的流程图。工艺开始于步骤902，如上文中参考图1A至图1C所讨论的，提供了具有鳍的衬底、相邻鳍之间的介电层、以及位于鳍和介电层上方的栅电极层。在步骤906中，如上文中参考图2A至图7F所讨论的，图案化栅电极层以形成具有在线端部中形成的沟槽的栅电极。可选地，在步骤908中，如上文中参考图8A至图8F所讨论的，在沟槽下方的介电层中形成凹口。
在实施例中，提供了形成finFET的方法。方法包括提供了具有鳍（从衬底延伸出）的衬底和在相邻鳍之间形成第一介电层，以及在鳍和介电层上方形成栅电极层。图案化栅电极层以提供多个栅电极，其中多个栅电极的端部具有沿底部边缘的沟槽。可以使沟槽下方的介电层凹进。
在另一实施例中，提供了形成finFET的另一方法。方法包括提供了具有横向对齐的至少两个鳍的衬底，在两个鳍端部之间形成第一介电层，以及至少在第一鳍上方形成第一栅电极并且至少在第二鳍上方形成第二栅电极，使得第一栅电极和第二栅电极的纵轴对齐。在第一栅电极的朝向第二栅电极的端部中形成第一沟槽，且在第二栅电极的朝向第一栅电极的端部形成第二沟槽。可以使在沟槽下方的介电层凹进。
在又一实施例中，提供了finFET。finFET包括远离衬底延伸的鳍以及紧邻鳍的介电层。栅电极位于鳍和介电层的上方，其中栅电极的端部具有位于栅电极和介电层的界面处的沟槽。可以使沟槽下方的介电层凹进。
尽管已经详细描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变、替换和更改。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定的示例性实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结构的工艺、机器、制造、材料组分、装置、方法或步骤根据本发明可以被使用。相应地，所附权利要求意指在其范围内包括例如工艺、机器、制造、材料组分、装置、方法或步骤。

Claims (20)

1.一种形成鳍式场效应晶体管(finFET)的方法，所述方法包括：
提供衬底，所述衬底具有从其延伸的鳍；
在相邻鳍之间形成第一介电层；
在所述鳍和所述第一介电层上方形成栅电极层；以及
将所述栅电极层图案化为多个栅电极，其中，在所述多个栅电极的端部形成沿所述栅电极层底部边缘的凹入以形成沟槽，所述沟槽由所述第一介电层的顶面和所述栅电极层的端部的底部凹入部分的侧面形成。
2.根据权利要求1所述的形成鳍式场效应晶体管的方法，进一步包括：在所述多个栅电极的所述沟槽下方的所述第一介电层中形成凹口。
3.根据权利要求2所述的形成鳍式场效应晶体管的方法，其中，利用CHF3、CH3F、CF4、CH2F2、SF6或O2的工艺气体，至少部分地使用干蚀刻来形成所述凹口。
4.根据权利要求2所述的形成鳍式场效应晶体管的方法，其中，利用HF、NH3或H2O的工艺气体以及N的载气，至少部分地使用干蚀刻来形成所述凹口。
5.根据权利要求1所述的形成鳍式场效应晶体管的方法，其中，所述多个栅电极中的两个栅电极端部与端部对齐，并且所述方法进一步包括在所述两个栅电极的所述沟槽的下方形成凹口。
6.根据权利要求5所述的形成鳍式场效应晶体管的方法，进一步包括：在凹进的所述两个栅电极之间的所述第一介电层中形成所述凹口，使得所述两个栅电极的所述沟槽下方的所述凹口形成从一个沟槽下方延伸到另一沟槽下方的单个连续凹口。
7.根据权利要求1所述的形成鳍式场效应晶体管的方法，其中，至少部分地使用干蚀刻工艺形成所述多个栅电极中的所述沟槽。
8.根据权利要求7所述的形成鳍式场效应晶体管的方法，其中，所述干蚀刻工艺利用CHF3、CF4、CH2F2、SF6或O2的工艺气体。
9.一种形成鳍式场效应晶体管(finFET)的方法，所述方法包括：
提供具有横向对齐的至少两个鳍的衬底；
在所述两个鳍的端部之间形成第一介电层；
至少在第一鳍上方形成第一栅电极并且至少在第二鳍上方形成第二栅电极，所述第一栅电极和所述第二栅电极的纵轴对齐；
在所述第一栅电极的朝向所述第二栅电极的端部中形成沿所述第一栅电极底部边缘的凹入以形成第一沟槽；以及
在所述第二栅电极的朝向所述第一栅电极的端部中形成沿所述第二栅电极底部边缘的凹入以形成第二沟槽；
其中，所述第一沟槽和所述第二沟槽分别由所述第一介电层的顶面和所述第一栅电极的端部的底部凹入部分的侧面以及所述第一介电层的顶面和所述第二栅电极的端部的底部凹入部分的侧面形成；
在形成所述第一沟槽之后，在所述第一沟槽中形成第二介电层。
10.根据权利要求9所述的形成鳍式场效应晶体管的方法，其中，所述第二介电层在所述第一栅电极和所述第二栅电极之间延伸。
11.根据权利要求10所述的形成鳍式场效应晶体管的方法，其中，所述第二介电层延伸至所述第二沟槽中。
12.根据权利要求9所述的形成鳍式场效应晶体管的方法，进一步包括：在所述第一介电层中形成凹口。
13.根据权利要求12所述的形成鳍式场效应晶体管的方法，其中，所述凹口从所述第一沟槽下方延伸到所述第二沟槽下方。
14.根据权利要求12所述的形成鳍式场效应晶体管的方法，其中，所述凹口的深度小于
15.根据权利要求9所述的形成鳍式场效应晶体管的方法，其中，至少部分地使用干蚀刻工艺形成所述第一沟槽和形成所述第二沟槽。
16.根据权利要求15所述的形成鳍式场效应晶体管的方法，其中，所述干蚀刻工艺利用CHF3、CF4、CH2F2、SF6或O2的工艺气体。
17.一种鳍式场效应晶体管(finFET)，包括：
鳍，远离衬底延伸；
介电层，紧邻所述鳍；以及
栅电极，形成在所述鳍和所述介电层上方，其中，所述栅电极的端部在所述介电层的顶面上方形成沿所述栅电极底部边缘的凹入以形成沟槽，所述沟槽由所述介电层的顶面和所述栅电极的端部的底部凹入部分的侧面形成。
18.根据权利要求17所述的鳍式场效应晶体管，其中，所述沟槽的高度小于2000nm。
19.根据权利要求17所述的鳍式场效应晶体管，进一步包括位于所述沟槽下方的所述介电层中的凹口。
20.根据权利要求19所述的鳍式场效应晶体管，其中，所述凹口的深度小于
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