CN104037092A - 一种基于aaqfn的二次曝光和塑封技术的封装件及其制作工艺 - Google Patents

一种基于aaqfn的二次曝光和塑封技术的封装件及其制作工艺 Download PDF

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CN104037092A
CN104037092A CN201410203916.7A CN201410203916A CN104037092A CN 104037092 A CN104037092 A CN 104037092A CN 201410203916 A CN201410203916 A CN 201410203916A CN 104037092 A CN104037092 A CN 104037092A
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chip
aaqfn
lead frame
green oil
lead wire
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李涛涛
崔梦
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Huatian Technology Xian Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

本发明公开了一种基于AAQFN的二次曝光和塑封技术的封装件及其制作工艺，所述封装件主要由引线框架、下芯片、上芯片、胶膜、键合线、塑封体、绿油和植球组成。所述引线框架上焊接有下芯片，下芯片通过胶膜与上芯片粘接，键合线连接上芯片和引线框架，塑封体包围了引线框架的部分、下芯片、上芯片、胶膜和键合线，所述引线框架间填充有绿油，引线框架连接有植球。所述制作工艺主要流程如下：晶圆减薄→划片→上芯→压焊→塑封→后固化→印刷感光油墨→曝光显影→引脚分离→去膜→刷绿油→曝光显影→植球。所述封装件和制作工艺显著提高了封装件的可靠性，且此法易行，生产效率高。

Description

一种基于AAQFN的二次曝光和塑封技术的封装件及其制作工艺
技术领域
本发明属于集成电路封装技术领域，优化普通基于AAQFN封裝件的塑封制作工艺，涉及一种利用二次曝光技术和塑封技术改良封装件的结构和制作工艺。
背景技术
集成电路是信息产业和高新技术的核心，是经济发展的基础。集成电路封装是集成电路产业的主要组成部分，它的发展一直伴随着其功能和器件数的增加而迈进。自20世纪90年代起，它进入了多引脚数、窄间距、小型薄型化的发展轨道。无载体栅格阵列封装(即AAQFN)是为适应电子产品快速发展而诞生的一种新的封装形式，是电子整机实现微小型化、轻量化、网络化必不可少的产品。
无载体栅格阵列封装元件，底部没有焊球，焊接时引脚直接与PCB板连接，与PCB的电气和机械连接是通过在PCB焊盘上印刷焊膏，配合SMT回流焊工艺形成的焊点来实现的。该技术封装可以在同样尺寸条件下实现多引脚、高密度、小型薄型化封装，具有散热性、电性能以及共面性好等特点。
AAQFN封装产品适用于大规模、超大规模集成电路的封装。AAQFN封装的器件大多数用于手机、网络及通信设备、数码相机、微机、笔记本电脑和各类平板显示器等高档消费品市场。掌握其核心技术，具备批量生产能力，将大大缩小国内集成电路产业与国际先进水平的差距，该产品有着广阔市场应用前景。
但是由于技术难度等限制，目前AAQFN产品在市场上的推广有一定难度，尤其是在可靠性方面，直接影响产品的使用及寿命，已成为AAQFN封装件的技术攻关难点。
发明内容
为了克服上述现有技术存在的问题，本发明提供了一种基于AAQFN的二次曝光和塑封技术的封装件及其制作工艺，使集成电路框架与塑封体结合更加牢固，不受外界环境影响，提高了产品的封装可靠性。
一种基于AAQFN的二次曝光和塑封技术的封装件，主要由引线框架、下芯片、上芯片、胶膜、键合线、塑封体、绿油和植球组成。所述引线框架上焊接有下芯片，下芯片通过胶膜与上芯片粘接，键合线连接上芯片和引线框架，塑封体包围了引线框架的部分、下芯片、上芯片、胶膜和键合线，所述引线框架间填充有绿油，引线框架连接有植球。
一种基于AAQFN的二次曝光和塑封技术的封装件的制作工艺主要流程如下：晶圆减薄→划片→上芯→压焊→塑封→后固化→印刷感光油墨→曝光显影→引脚分离→去膜→刷绿油→曝光显影→植球。
所述封装件和制作工艺显著提高封装件的可靠性，且此法易行，生产效率高。
附图说明
图1半蚀刻框架剖面图；
图2倒装上芯、回流焊后产品剖面图；
图3点胶、上芯后产品剖面图；
图4压焊后产品剖面图；
图5一次塑封后产品剖面图；
图6印刷感光油墨后产品剖面图；
图7曝光、显影后产品剖面图；
图8引脚分离后产品剖面图；
图9去膜后产品剖面图；
图10刷绿油后产品剖面图；
图11曝光、显影(制作环状绿油)后产品剖面图；
图12植球后产品剖面图。
图中，1为引线框架，2为焊球、3为下芯片、4为上芯片、5为胶膜、6为键合线、7为塑封体、8为感光油墨、9为绿油、10为植球。
具体实施方式
下面结合附图对本发明做一详细描述。
一种基于AAQFN的二次曝光和塑封技术的封装件，主要由引线框架1、焊球2、下芯片3、上芯片4、胶膜5、键合线6、塑封体7、绿油9和植球10组成。所述引线框架1上通过焊球2焊接在下芯片3上，下芯片3通过胶膜5与上芯片4粘接，键合线6连接上芯片4和引线框架1，塑封体7包围了引线框架1的部分、下芯片3、上芯片4、胶膜5和键合线6，所述引线框架1间填充有绿油9，引线框架1连接有植球10。
一种基于AAQFN的二次曝光和塑封技术的封装件的制作工艺主要流程如下：晶圆减薄→划片→上芯→压焊→塑封→后固化→印刷感光油墨→曝光显影→引脚分离→去膜→刷绿油→曝光显影→植球。
一种基于AAQFN的二次曝光和塑封技术的封装件的制作工艺，具体按照以下步骤进行：
1、晶圆减薄：减薄厚度50μm～200μm，粗糙度Ra0.10mm～0.05mm；
2、划片：150μm以上晶圆同普通QFN划片工艺，但厚度在150μm以下晶圆，使用双刀划片机及其工艺；
3、上芯(粘片)：既可采用粘片胶又可采用胶膜片(DAF)上芯，如图1、图2和图3所示；
4、压焊：压焊同常规AAQFN工艺相同，如图4所示；
5、塑封：用传统塑封料进行塑封，如图5所示；
6、后固化工艺同常规AAQFN工艺；
7、印刷感光油墨，如图6所示；
8、曝光、显影，如图7所示；
9、引脚蚀刻分离，如图8所示；
10、去膜：去感光油墨，如图9所示；
11、刷绿油：用绿油填充引脚分离后的空隙，如图10所示；
12、曝光、显影，制作环状绿油，如图11所示；
13、植球，如图12所示。

Claims (2)

1.一种基于AAQFN的二次曝光和塑封技术的封装件，其特征在于：主要由引线框架(1)、焊球(2)、下芯片(3)、上芯片(4)、胶膜(5)、键合线(6)、塑封体(7)、绿油(9)和植球(10)组成；所述引线框架(1)上通过焊球(2)焊接在下芯片(3)上，下芯片(3)通过胶膜(5)与上芯片(4)粘接，键合线(6)连接上芯片(4)和引线框架(1)，塑封体(7)包围了引线框架(1)的部分、下芯片(3)、上芯片(4)、胶膜(5)和键合线(6)，所述引线框架(1)间填充有绿油(9)，引线框架(1)连接有植球(10)。
2.一种基于AAQFN的二次曝光和塑封技术的封装件的制作工艺，其特征在于：具体按照以下步骤进行：
(1)晶圆减薄：减薄厚度50μm～200μm，粗糙度Ra0.10mm～0.05mm；
(2)划片：150μm以上晶圆同普通QFN划片工艺，但厚度在150μm以下晶圆，使用双刀划片机及其工艺；
(3)上芯(粘片)：既可采用粘片胶又可采用胶膜片(DAF)上芯；
(4)压焊：压焊同常规AAQFN工艺相同；
(5)塑封：用传统塑封料进行塑封；
(6)后固化工艺同常规AAQFN工艺；
(7)印刷感光油墨；
(8)曝光、显影；
(9)引脚蚀刻分离；
(10)去膜：去感光油墨；
(11)刷绿油：用绿油填充引脚分离后的空隙；
(12)曝光、显影，制作环状绿油；
(13)植球。
CN201410203916.7A 2014-05-14 2014-05-14 一种基于aaqfn的二次曝光和塑封技术的封装件及其制作工艺 Pending CN104037092A (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090298237A1 (en) * 2006-12-27 2009-12-03 Canon Kabushiki Kaisha Semiconductor module
CN102194775A (zh) * 2010-03-03 2011-09-21 南茂科技股份有限公司 四边扁平无接脚封装结构
CN103094240A (zh) * 2012-12-15 2013-05-08 华天科技（西安）有限公司 一种高密度蚀刻引线框架fcaaqfn封装件及其制作工艺

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090298237A1 (en) * 2006-12-27 2009-12-03 Canon Kabushiki Kaisha Semiconductor module
CN102194775A (zh) * 2010-03-03 2011-09-21 南茂科技股份有限公司 四边扁平无接脚封装结构
CN103094240A (zh) * 2012-12-15 2013-05-08 华天科技（西安）有限公司 一种高密度蚀刻引线框架fcaaqfn封装件及其制作工艺

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Application publication date: 20140910