CN104009001B - The processing method and bonding sheet of stacked wafers - Google Patents
The processing method and bonding sheet of stacked wafers Download PDFInfo
- Publication number
- CN104009001B CN104009001B CN201410056892.7A CN201410056892A CN104009001B CN 104009001 B CN104009001 B CN 104009001B CN 201410056892 A CN201410056892 A CN 201410056892A CN 104009001 B CN104009001 B CN 104009001B
- Authority
- CN
- China
- Prior art keywords
- chip
- bonding sheet
- stacked wafers
- segmentation
- protrusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 235000012431 wafers Nutrition 0.000 title claims abstract description 110
- 238000003672 processing method Methods 0.000 title claims abstract description 21
- 230000011218 segmentation Effects 0.000 claims abstract description 58
- 238000012986 modification Methods 0.000 claims description 13
- 230000004048 modification Effects 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 12
- 238000004026 adhesive bonding Methods 0.000 claims description 10
- 230000035699 permeability Effects 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 description 11
- 230000002093 peripheral effect Effects 0.000 description 11
- 239000011347 resin Substances 0.000 description 8
- 229920005989 resin Polymers 0.000 description 8
- 238000012545 processing Methods 0.000 description 7
- 238000007689 inspection Methods 0.000 description 4
- 229920000915 polyvinyl chloride Polymers 0.000 description 3
- 239000004800 polyvinyl chloride Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000010023 transfer printing Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-N Acrylic acid Chemical class OC(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 229920000098 polyolefin Polymers 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/50—Working by transmitting the laser beam through or within the workpiece
- B23K26/53—Working by transmitting the laser beam through or within the workpiece for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Optics & Photonics (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Mechanical Engineering (AREA)
- Plasma & Fusion (AREA)
- Oil, Petroleum & Natural Gas (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Dicing (AREA)
Abstract
The present invention provides the processing method and bonding sheet of stacked wafers, is laminated on chip in the stacked wafers of multiple chips, in the state that chip side is pasted onto on bonding sheet, also can reliably divide the wafer into each stacked die.It will be in paste layer(22)Upper and stacked wafers(1)Periphery remaining area(1B)Accordingly it is formed with protrusion(3)Bonding sheet(2)Paste layer(22)It is pasted onto stacked wafers(1)Chip(15)On, by protrusion(3)With periphery remaining area(1B)Accordingly it is pasted onto chip(10)Surface(10a)On, pass through protrusion(3)Support chip(10)Periphery remaining area(1B).In this state, it is formed along segmentation preset lines(11)To chip(10)Segmentation starting point(Modify layer 10c), pass through bonding sheet(2)Expansion to chip(10)Apply external force, as a result, the stacked die of outermost circumference(1c)It also can be with other stacked dies(1c)It is carried out similarly segmentation.
Description
Technical field
The present invention relates to the processing method for the stacked wafers that multiple chips are arranged on chip and it is suitble in the processing method
The middle bonding sheet used.
Background technology
As one of method integrated in encapsulating multiple semiconductor devices at 1, multiple semiconductor device chips are existed
CoW (the Chip on Wafer for being laminated and being installed on three-dimensional:Chip on chip) etc. three-dimensional installation be known
's.CoW is split by the chip of the stacked wafers to chip has been laminated on chip according to each chip, is formd in core
The stacked die (referring to patent document 1) of chip has been laminated on piece.
On the other hand, in order to be split to this chip, usually chip is cut into the bite for exercising cutting apparatus
Cutting based on mechanical processing (with reference to patent document 2).In addition, in recent years, developing by being irradiated by laser beam in chip
It is that the method that segmentation starting point is split is (literary with reference to patent to modify layer to chip application external force after inside formation modification layer
It offers 3), proposes expanded to pasting bonding sheet on the wafer to apply technology (the reference patent of external force in the method
Document 4).
Patent document 1:Japanese Unexamined Patent Publication 2012-209522 bulletins
Patent document 2:Japanese Unexamined Patent Publication 2007-214201 bulletins
Patent document 3:No. 3408805 bulletins of Japanese Patent No.
Patent document 4:Japanese Unexamined Patent Publication 2010-034250 bulletins
However, as the chip for realizing three-dimensional installation, in the internal intermediary's layer wafer for being packed into wiring and electrode etc.
(Interposer wafer) has been practical.It is brilliant the stacking that multiple chips obtain has been folded on such intermediary's layer wafer upper layer
Piece is divided into stacked die obtained from each chip, carries out spy to being formed in the electrodes such as the convex block in intermediary's layer wafer sometimes
Property inspection.Therefore, it after being divided into stacked die, needs, using intermediary layer wafer side as upper surface, to pass through bonding sheet supporting-core
Piece side could carry out the inspection.Therefore, as it is commonly practiced, pasting bonding sheet simultaneously in wafer side, that is, intermediary layer wafer side
In the case of being divided, if after chip segmentation, implements to paste bonding sheet in chip side and make the bonding sheet of wafer side
The transfer printing process of the such bonding sheet of stripping, then can realize the inspection to intermediary's layer wafer of stacked die.However, the transfer
Process expends the time, productivity can be caused to decline.
Therefore, by pasting bonding sheet in the chip side of stacked wafers, and in the state of so that intermediary layer wafer side is exposed
Divide intermediary's layer wafer, necessity of the transfer of bonding sheet can be eliminated.But in stacked wafers, due in the non-layer of peripheral part
Folded chip, therefore, in intermediary layer wafer side, there are scales between chip area and peripheral part, therefore, are pasted in chip side
In the case of bonding sheet, the phenomenon that peripheral part of intermediary's layer wafer is bent to bonding sheet side will produce.
In this way, when the peripheral part of intermediary's layer wafer produces flexure, problems with is generated:On being formed on intermediary's layer wafer
It, can not be suitably in the boundary portion of chip area and peripheral part due to deflection in the case of stating segmentation starting point and being split
Divide and forms the segmentation starting point.Such as in the case where it is the modification layer that laser beam irradiates to divide starting point, focal point occurs inclined
From and modification layer can not be formed, in addition, in the case where dividing the slot that starting point is laser processing or machining obtains, the depth of slot
Degree can be inadequate.Moreover, even if foring segmentation starting point, the crystalline substance of the expansion based on bonding sheet recorded in above patent document 4
In the dividing method of piece, due to there are above-mentioned scale, being unable to fully paste bonding sheet in the peripheral part of intermediary's layer wafer, therefore,
In the boundary part of chip area and peripheral part, the external force for expanding generation is difficult to be transmitted to the boundary part, generates outermost circumference
Stacked die the problem of can not being split.
Invention content
The present invention has been made in view of the above-described circumstances, and main technical task is, provides the processing of stacked wafers
Method and bonding sheet have been laminated on chip in stacked wafers obtained from multiple chips, and chip side is being pasted onto bonding sheet
In the state of upper, also can chip be reliably divided into each stacked die.
The processing method of the stacked wafers of the present invention, the stacked wafers have chip and chip and as intermediary's layer wafers
Chip, the chip are laminated on each region divided by the multiple segmentation preset lines intersected on the surface of the chip respectively,
The stacked wafers have the chip area for being laminated with multiple chips and the periphery remaining area around the chip area, in the core
It is formed with scale between panel region and the periphery remaining area, which is characterized in that the bonding pasted with the stacked wafers
Piece has:Substrate layer;The paste layer being disposed on the substrate layer;And protrusion, it is surplus with the periphery of the stacked wafers
Remaining region is correspondingly formed in the paste layer, have thickness with the thickness same degree of the chip, at least the protrusion
Upper surface has cementability for the chip, and the processing method of the stacked wafers includes:Bonding sheet gluing steps, by the layer
The paste layer of the chip and the bonding sheet of folded chip is pasted, and the periphery of the stacked wafers is remained
It is pasted with the protrusion in remaining region;Divide starting point forming step, after implementing the bonding sheet gluing steps, from described
The back side of stacked wafers forms segmentation starting point along region corresponding with the segmentation preset lines;And segmentation step, in reality
After having applied the segmentation starting point forming step, external force is applied to the stacked wafers, using the segmentation starting point as starting point to described
Chip is split, implement the bonding sheet gluing steps and so that the chip of the stacked wafers is secured at institute
State in the paste layer of bonding sheet and the periphery remaining area of the stacked die by the protrusion support in the state of,
The segmentation starting point forming step and the segmentation step (technical solution 1) are implemented to the stacked wafers.
In the processing method of the stacked wafers of the present invention, bonding sheet has been pasted in chip side by bonding sheet gluing steps
Stacked wafers become following state:The upper surface of the protrusion of bonding sheet is with the scale compared to stacked wafers close to peripheral side
Periphery remaining area bonding, which is supported by protrusion.Therefore, it is suppressed that the periphery remaining area of chip to
Bonding sheet side is bent, as a result, when chip is divided into stacking by forming segmentation starting point on chip and applying external force
When chip, segmentation starting point can be properly formed.Therefore, in the state being pasted onto the chip side of stacked wafers on bonding sheet
Under, each chip can be also divided the wafer into, it is outermost especially in the case where being expanded to bonding sheet and divide chip
The stacked die of circumference can be also split.It is bonded further, since being pasted in the chip side of stacked wafers before dividing chip
Piece, the transfer printing process of required bonding sheet when therefore, there is no need to be split in the state that wafer side has pasted bonding sheet.
In the segmentation step of the present invention, including applying external force to the chip by expanding the bonding sheet
Mode (technical solution 2).In this approach, as described above, the stacked die of the outermost circumference of chip also can be with other layers
Folded chip is similarly split.
In addition, in the segmentation starting point forming step, including irradiation has the chip wavelength of permeability
Laser beam and the inner wafer formed modification layer mode (technical solution 3).
Then, bonding sheet of the invention is the processing for the stacked wafers recorded in any one of above-mentioned technical proposal 1~3
Bonding sheet used in method, which is characterized in that the bonding sheet has:Substrate layer;The paste layer being disposed on the substrate layer;With
And the protrusion accordingly formed in the paste layer with the periphery remaining areas of the stacked wafers, the protrusion have with
The thickness of the thickness same degree of chip, at least upper surface of the protrusion have the chip of the stacked wafers viscous
Connecing property.
According to the present invention, it is provided the processing method of stacked wafers and the effect of bonding sheet, has been laminated on chip more
In the stacked wafers of a chip, in the state that chip side is pasted onto on bonding sheet, also chip can be reliably divided into
Each stacked die.
Description of the drawings
(a) of Fig. 1 is the stereogram of the stacked wafers of the processing method segmentation of an embodiment through the invention, Fig. 1
(b) be the stacked wafers side view, (c) of Fig. 1 is the partly enlarged top view of the stacked wafers.
(a) of Fig. 2 is the stereogram of the bonding sheet of one embodiment of the present invention, and (b) of Fig. 2 is the part of the bonding sheet
Enlarged cross-sectional view.
Fig. 3 is the frame pasted on bonding sheet in the processing method for show an embodiment with decomposing state and stacking
The stereogram of chip.
Fig. 4 is the sectional view for the bonding sheet gluing steps for showing the processing method.
(a) of Fig. 5 is the sectional view for the segmentation starting point forming step for showing the processing method, and (b) of Fig. 5 is to show in detail
Go out to modify the figure of layer formation.
Fig. 6 is that the partial side for the stacked wafers for foring modification layer in inner wafer through over-segmentation starting point forming step is cutd open
View.
Fig. 7 is the sectional view of the segmentation step for the processing method for showing an embodiment.
Label declaration
1:Stacked wafers
1A:Chip area
1B:Periphery remaining area
10:Chip
10a:The surface of chip
10b:The back side of chip
10c:Modify layer (segmentation starting point)
11:Divide preset lines
12:Region
15:Chip
16:Scale
2:Bonding sheet
21:Bonding sheet substrate layer
22:The paste layer of bonding sheet
3:Protrusion
L:Laser beam
Specific implementation mode
[1] stacked wafers
Fig. 1 shows the stacked wafers 1 for being divided into each stacked die in one embodiment.Stacked wafers 1 are in inside
It encloses and multiple squares is laminated on the surface 10a of disk-shaped intermediary's layer wafer (hereinafter referred to as chip) 10 of wiring and electrode etc.
The chip 15 of shape.Chip 15 is semiconductor devices etc., and as shown in (c) of Fig. 1, each chip 15 is laminated in point by clathrate
It cuts on rectangular-shaped each region 12 that preset lines 11 divide on the surface 10a of chip 10.Chip 10 in advance to the back side sides 10b into
Row grinding, thinning are processed as defined thickness.
Stacked wafers 1 are divided to the chip area 1A of the substantially rectangular shape to be laminated with multiple chips 15 and non-stacked die
The periphery remaining area 1B of 15 peripheral part.The thickness of chip 15 is, for example, 100 μm or so, therefore, as shown in (b) of Fig. 1,
Chip area 1A and it is formed with scale corresponding with the thickness of chip 15 between the periphery remaining area 1B of chip area 1A
16。
[2] bonding sheet
Fig. 2 shows the bonding sheets 2 for the embodiment pasted on above-mentioned stacked wafers 1.It, should as shown in (b) of Fig. 2
Bonding sheet 2 is that have flexibility by PO (polyolefin), PVC (polyvinyl chloride), PET (polyethylene terephthalate) etc.
The paste layer 22 being made of the resin of rubber series or acrylic acid series is formed on one face of the substrate layer 21 that resin sheet is constituted and is obtained
's.It is equipped with cricoid protrusion 3 in 22 side of paste layer of the bonding sheet 2.
There is protrusion 3 size corresponding with the periphery remaining area 1B of chip 10 to be formed as having as shown in (b) of Fig. 2
There is the section of certain width rectangular-shaped.The internal diameter of protrusion 3 is set to bigger than the chip area 1A of stacked wafers 1 and compares
The small range of the outer diameter of chip 10, also, the outer diameter of protrusion 3 be set to it is bigger than the outer diameter of chip 10.
As shown in (b) of Fig. 2,3 use of protrusion structure identical with bonding sheet 2, i.e., by by above-mentioned PO, PVC etc.
The band that paste layer 32 is formed on the substrate layer 31 that resin with flexibility is constituted constitutes protrusion 3, and protrusion 3 is equipped
At 31 side of stickup substrate layer in the paste layer 22 of bonding sheet 2.Therefore the upper surface of protrusion 3 is formed by paste layer 32, has bonding
Property.The thickness of protrusion 3 is set as journey identical with the height of the above-mentioned scale 16 of stacked wafers 1, the i.e. thickness of chip 15
Degree.That is, the thickness of the band for constituting protrusion 3 is selected according to the thickness of chip 15, in addition, in the feelings of the band thinner than chip 15
Under condition, by the way that multiple protrusions 3 for bringing composition same with the thickness of chip 15 are laminated.
[3] processing method
Then, multiple stacked dies are obtained to dividing the chip 10 of above-mentioned stacked wafers 1 along segmentation preset lines 11
The processing method of one embodiment illustrates.
[3-1] bonding sheet gluing steps
First, the cricoid frame 4 of operation (Handling) shown in Fig. 3 is disposed in the protrusion of above-mentioned bonding sheet 2
Around portion 3.Frame 4 by stainless steel etc. there is the metallic plate etc. of rigidity to constitute, and inner peripheral is formed as round, and internal diameter is formed as comparing
The outer diameter of protrusion 3 is big.The position concentric with protrusion 3 is set in by frame 4, as shown in figure 4, being pasted onto the paste of bonding sheet 2
On layer 22.
Then, as shown in figure 4, on the bonding sheet 2 of tape frame 4 patch laminate chip 1 15 side of chip.That is, such as Fig. 4
(a) shown in so that the paste layer 22 of the bonding sheet 2 of the inside of chip 15 and protrusion 3 is opposite, and periphery remaining area 1B with it is prominent
3 corresponding mode of portion is played, stacked wafers 1 and bonding sheet 2 are oppositely disposed, from the state, as shown in (b) of Fig. 4, by each core
Piece 15 is pasted onto in paste layer 22, and the periphery remaining area 1B of the surface sides 10a of chip 10 is pasted onto to the paste layer 32 of protrusion 3
On.As a result, in stacked wafers 1, each chip 15 is secured in paste layer 22, and the back side 10b of chip 10 exposes, in addition, chip
The periphery remaining area 1B of the 10 surface sides 10a is secured in the paste layer 32 of protrusion 3, becomes and is supported by the protrusion 3
State.Since the thickness of protrusion 3 is the thickness with the thickness same degree of chip 15, the periphery remaining area of chip 10
Domain 1B will not be bent to 2 side of bonding sheet, and in plane identical with chip area 1A, chip 10 is whole flatly to be protected
It holds.In addition, obtaining being not limited to above-mentioned steps, example the step of having pasted the state of stacked wafers 1 on the bonding sheet 2 of tape frame 4
After such as stacked wafers 1 can also be pasted onto on bonding sheet 2, frame 4 is pasted onto on bonding sheet 2.
[3-2] divides starting point forming step
Then, it is formed and is divided along region corresponding with segmentation preset lines 11 from the back side sides 10b of the chip 10 of stacked wafers 1
Cut starting point.Segmentation starting point will be for example, the slot obtained by laser processing or machining still will pass through laser herein
Obtained modification layer is processed as segmentation starting point, forms the modification layer as follows.
As shown in figure 5, on holding unit 5 by make the back side sides 10b expose in a manner of keep stacked wafers 1, by from swash
Light irradiation unit 6 has chip 10 along the segmentation irradiation of preset lines 11 the laser beam L of the wavelength of permeability, in chip 10
Portion forms modification layer 10c.As shown in (b) of Fig. 5, the focal point of laser beam L is arranged in the position of the prescribed depth from the 10b of the back side
It sets, forms modification layer 10c along segmentation preset lines 11 in the inside of chip 10 as a result,.Modifying layer 10c has intensity than chip 10
The low characteristic of interior other parts becomes segmentation starting point, chip 10 is along segmentation preset lines 11 when applying external force to chip 10
It is divided.
It is carried out by making holding unit 5 and laser beam irradiation unit 6 relatively move in the horizontal direction predetermined along segmentation
The scanning of the laser beam L of line 11 is still set on hold 5 side of unit and is moved herein.Alternatively, it is also possible to be set as laser irradiation
6 side of unit is moved, and may be also constructed to holding unit 5 and 6 both sides of laser beam irradiation unit move.
Holding unit 5 is around the disk-shaped holding station 51 of the retaining surface 51a with the level for keeping stacked wafers 1
The multiple clamping devices 52 for keeping frame 4 are equipped with, therefore, stacked wafers 1 are positioned in across bonding sheet 2 on retaining surface 51a, are led to
It crosses clamping device 52 and seizes frame 4 on both sides by the arms, as a result, in the state of being applied with tension to radial outside to bonding sheet 2, by stacked wafers
1 is maintained on holding unit 5.
Holding unit 5 being capable of (left and right directions in Fig. 5) and another direction orthogonal with a direction in one direction
Upper movement, also, be supported for be rotated by rotary shaft of center, on the other hand, laser beam irradiation unit 6 is by fixedly
Support.Then, so that holding unit 5 is moved on one side and be processed feeding, on one side from laser beam irradiation unit 6 along segmentation preset lines
11 irradiation laser beam L form modification layer along the segmentation preset lines 11 extended in one direction in the inside of chip 10 as a result,
10c can carry out point of the segmentation preset lines 11 of laser beam to be irradiated by making holding unit 5 move in the other directions
Degree.In addition, by making holding unit 5 be rotated by 90 °, laser beam L can be irradiated to unprocessed segmentation preset lines 11.
[3-3] segmentation step
As shown in fig. 6, by above-mentioned segmentation starting point forming step along whole segmentation preset lines 11 in chip 10
After forming modification layer 10c, stacked wafers 1 are moved out from holding unit 5, stacked wafers 1 are moved in into extension fixture 7 shown in Fig. 7.
The cricoid liter that extension fixture 7 has the cylinder platform 71 of mounting chip 10 and is arranged around cylinder platform 71
Platform 72 drops.The outer diameter of cylinder platform 71 is bigger than the protrusion 3 of bonding sheet 2, is loaded across bonding sheet 2 in horizontal upper end opening portion
Stacked wafers 1.Lifting platform 72 be adapted to 71 same heart shaped of cylinder platform and liftable, by using air pressure or the fluid of hydraulic pressure
The piston rod 74 of cylinder apparatus 73 is carried out flexible and is lifted.On lifting platform 72, interval is equipped in the circumferential
Multiple clamping devices 75.
In order to implement segmentation step, as shown in (a) of Fig. 7, the height and position of lifting platform 72 is set as and cylinder platform 71
Upper end opening portion is identical, and the upper end opening portion across bonding sheet 2 in cylinder platform 71 loads stacked wafers 1, also, passes through clamping machine
Structure 75 is seized on both sides by the arms and fixed frame 4, and bonding sheet 2 is made to become horizontal state, and stacked wafers 1 are arranged on cylinder platform 71.Then,
As shown in (b) of Fig. 7, the piston rod 74 of each cylinder assembly 73 is made synchronously to reduce, lifting platform 72 is made to decline.
When lifting platform 72 declines, bonding sheet 2 is stretched to radial outside and is expanded, with the expansion of bonding sheet 2, to crystalline substance
Piece 10 similarly applies the external force of stretching to radial outside.Then, chip 10 using modify layer 10c be starting point along segmentation preset lines
11 are divided, and stacked wafers 1 are divided into each stacked die 1c that 1 chip 15 is laminated on the chip 10 divided.
Thus segmentation step terminates, then, for each stacked die for the state for having pasted chip 15 on bonding sheet 2
1c implements characteristic check to the electrode such as convex block formed on the chip 10 of overleaf 10b exposings.After the inspection, by layer
Folded chip 1c is picked up from bonding sheet 2 and is transferred to subsequent processing.
The function and effect of [4] embodiments
According to said one embodiment, the stacking of bonding sheet 2 has been pasted in 15 side of chip by bonding sheet gluing steps
Chip 1 becomes following state:The paste layer 32 of the upper surface of the protrusion 3 of bonding sheet 2 is leaned on the scale 16 compared to stacked wafers 1
The periphery remaining area 1B bondings of nearly peripheral side, the chip 10 surface sides 10a, periphery remaining area 1B are supported by protrusion 3.
Therefore, the periphery remaining area 1B of chip 10 with protrusion 3 by abutting, it is suppressed that is bent to 2 side of bonding sheet.
By implementing to divide starting point forming step in this state, so that focal point is located at the defined depth in chip 10
Position mode, it is pre- to the segmentation of the outermost circumference as the boundary part between chip area 1A and periphery remaining area 1B
Alignment 11 also irradiates laser beam L, is properly formed modification layer 10c.Further, since the upper surface of protrusion 3 by paste layer 32 with
The periphery remaining area 1B of the surface sides 10a of chip 10 is bonded, therefore, when the expansion of the bonding sheet 2 in segmentation step, expansion
The external force of generation can also be sufficiently transferred to the segmentation preset lines 11 of outermost circumference, and the stacked die 1c of outermost circumference also can
It is carried out similarly segmentation with other stacked die 1c.
Further, since paste bonding sheet 2 in 15 side of chip of stacked wafers 1 and chip 10 is split, therefore, for
Stacked wafers 1c after segmentation step, can maintain the in the state of of having pasted bonding sheet 2 continue to the back side 10b of chip 10 into
The above-mentioned characteristic check of row.It is required viscous when therefore, there is no need to be split in the state that bonding sheet 2 have been pasted in 10 side of chip
The transfer printing process for closing piece, realizes the raising of productivity.
In addition, the structure of the protrusion 3 of present embodiment shown in (b) of Fig. 2 is only an example, protrusion structure of the invention
As being size corresponding with the periphery remaining area 1B of stacked wafers 1, the thickness with 15 degree of chip, and upper surface has
Cementability.For example, it can be, in the paste layer 22 of bonding sheet 2 with size shape corresponding with periphery remaining area 1B
Protrusion is arranged at the mode of UV (ultraviolet light) hardening resin, after chip 10 is pasted onto on bonding sheet 2, protrusion is shone
UV is penetrated, keeps it Nian Jie with the periphery remaining area 1B of chip 10.In this case, the UV hardening resins for forming protrusion are to use
Also remain the UV hardening resins of cementability after UV irradiations, the adhesion coating 22 of 2 side of bonding sheet in order to after being irradiated by UV also
It keeps to the cementability of chip 15, preferably not UV constrictive types but the bonding sheet of pressure sensing type.Passing through UV hardening resin shapes
In the case of at protrusion, when being formed as continuous cyclic annular, there are the expansions of bonding sheet 2 to be hardened by UV in segmentation step
The case where protrusion limitation that type resin is constituted, therefore in order to expand, be arranged to dotted.In addition it is also possible to part
The paste layer 22 of bonding sheet 2 is formed thicker, and cricoid protrusion 3 is formed with material identical with paste layer 22.In arbitrary situation
Under, the upper surface for being all set as opposite with bonding sheet 2 has cementability.
In addition, the chip 10 of the above embodiment is intermediary's layer wafer, the stacked die 15 on the chip 10 and constitute layer
Folded chip 1 still, such as chip 10 is set as to form the device being made of electronic circuits such as IC, LSI on above-mentioned zone 12
Device wafer, for the stacked wafers etc. for the structure that chip 15 has been laminated on device, processing side that also can be through the invention
Method is divided into stacked die.
Claims (4)
1. a kind of processing method of stacked wafers, which has chip and the chip as intermediary's layer wafer, the chip
It is layered in respectively on each region made of being divided by multiple segmentation preset lines for intersecting of the surface of the chip, stacked wafers tool
There are the chip area for being laminated with multiple chips and the periphery remaining area around the chip area, it is outer with this in the chip area
It is formed with scale between all remaining areas, which is characterized in that
The bonding sheet pasted with the stacked wafers has:
Substrate layer;
The paste layer being disposed on the substrate layer;And
Protrusion is correspondingly formed on the periphery remaining area of the stacked wafers in the paste layer, have with it is described
The thickness of the thickness same degree of chip,
At least the upper surface of the protrusion has cementability for the chip,
The processing method of the stacked wafers includes:
Bonding sheet gluing steps paste the chip of the stacked wafers and the paste layer of the bonding sheet, and
And the periphery remaining area of the stacked wafers is pasted with the protrusion;
Divide starting point forming step, after implementing the bonding sheet gluing steps, from the back sides of the stacked wafers along with
The corresponding region of the segmentation preset lines forms segmentation starting point;And
Segmentation step is applied external force to the stacked wafers, is divided with described after implementing the segmentation starting point forming step
Point is split the chip as starting point,
The chip of the stacked wafers is made to be secured at the bonding sheet in the implementation bonding sheet gluing steps
In the paste layer and the periphery remaining area of the stacked wafers by the protrusion support in the state of, to the stacking
Chip implements the segmentation starting point forming step and the segmentation step.
2. the processing method of stacked wafers according to claim 1, which is characterized in that
In the segmentation step, external force is applied to the chip by making the bonding sheet expansion.
3. the processing method of stacked wafers according to claim 1 or 2, which is characterized in that
In the segmentation starting point forming step, the laser beam for the wavelength that there is permeability for the chip is irradiated, in the crystalline substance
Modification layer is formed inside piece.
4. the bonding sheet used in a kind of processing method of stacked wafers described in any one of claims 1 to 3, special
Sign is that the bonding sheet has:
Substrate layer;
The paste layer being disposed on the substrate layer;And
Protrusion is correspondingly formed on the periphery remaining area of the stacked wafers in the paste layer, is had and chip
Thickness same degree thickness,
At least the upper surface of the protrusion has cementability for the chip of the stacked wafers.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013-032821 | 2013-02-22 | ||
JP2013032821A JP6033116B2 (en) | 2013-02-22 | 2013-02-22 | Laminated wafer processing method and adhesive sheet |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104009001A CN104009001A (en) | 2014-08-27 |
CN104009001B true CN104009001B (en) | 2018-09-11 |
Family
ID=51369609
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410056892.7A Active CN104009001B (en) | 2013-02-22 | 2014-02-19 | The processing method and bonding sheet of stacked wafers |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP6033116B2 (en) |
CN (1) | CN104009001B (en) |
TW (1) | TWI575591B (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6190671B2 (en) * | 2013-09-05 | 2017-08-30 | 古河電気工業株式会社 | Dicing adhesive tape and method for manufacturing semiconductor device |
JP6306362B2 (en) * | 2014-02-13 | 2018-04-04 | リンテック株式会社 | Extensible sheet and laminated chip manufacturing method |
KR101740487B1 (en) * | 2015-10-20 | 2017-05-29 | 삼성디스플레이 주식회사 | Mask tension welding device for thin film deposition |
JP6746211B2 (en) * | 2016-09-21 | 2020-08-26 | 株式会社ディスコ | Wafer processing method |
JPWO2020195808A1 (en) * | 2019-03-26 | 2020-10-01 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1350329A (en) * | 2000-10-20 | 2002-05-22 | 松下电器产业株式会社 | Semiconductor devices and their method of production, and mounting method thereof |
CN1450604A (en) * | 2002-04-09 | 2003-10-22 | 松下电器产业株式会社 | Plasma working method and equipment and support frame for plasma working |
CN1677623A (en) * | 2004-04-01 | 2005-10-05 | 株式会社迪思科 | Wafer processing method |
CN101864249A (en) * | 2009-04-17 | 2010-10-20 | 古河电气工业株式会社 | Adhesive film and wafer processing tape |
CN102104021A (en) * | 2009-12-16 | 2011-06-22 | 南茂科技股份有限公司 | Wafer dicing method |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004095946A (en) * | 2002-09-02 | 2004-03-25 | Sekisui Chem Co Ltd | Method for manufacturing semiconductor chip |
JP2004335583A (en) * | 2003-05-01 | 2004-11-25 | Nippon Hoso Kyokai <Nhk> | Wafer dicing method |
JP2007123362A (en) * | 2005-10-25 | 2007-05-17 | Disco Abrasive Syst Ltd | Method of manufacturing device |
JP5641766B2 (en) * | 2010-04-22 | 2014-12-17 | 株式会社ディスコ | Wafer dividing method |
SG184786A1 (en) * | 2011-04-13 | 2012-11-29 | Asahi Engineering K K | Method for manufacturing semiconductor device, resin sealing apparatus, and semiconductor device |
JP5770677B2 (en) * | 2012-05-08 | 2015-08-26 | 株式会社ディスコ | Wafer processing method |
-
2013
- 2013-02-22 JP JP2013032821A patent/JP6033116B2/en active Active
-
2014
- 2014-01-08 TW TW103100635A patent/TWI575591B/en active
- 2014-02-19 CN CN201410056892.7A patent/CN104009001B/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1350329A (en) * | 2000-10-20 | 2002-05-22 | 松下电器产业株式会社 | Semiconductor devices and their method of production, and mounting method thereof |
CN1450604A (en) * | 2002-04-09 | 2003-10-22 | 松下电器产业株式会社 | Plasma working method and equipment and support frame for plasma working |
CN1677623A (en) * | 2004-04-01 | 2005-10-05 | 株式会社迪思科 | Wafer processing method |
CN101864249A (en) * | 2009-04-17 | 2010-10-20 | 古河电气工业株式会社 | Adhesive film and wafer processing tape |
CN102104021A (en) * | 2009-12-16 | 2011-06-22 | 南茂科技股份有限公司 | Wafer dicing method |
Also Published As
Publication number | Publication date |
---|---|
CN104009001A (en) | 2014-08-27 |
TW201436014A (en) | 2014-09-16 |
JP6033116B2 (en) | 2016-11-30 |
JP2014165233A (en) | 2014-09-08 |
TWI575591B (en) | 2017-03-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104009001B (en) | The processing method and bonding sheet of stacked wafers | |
US10872801B2 (en) | Target substrate with micro semiconductor structures | |
WO2018035668A1 (en) | Micro-led transfer method, manufacturing method and device | |
CN102386197B (en) | Image sensor chip package and method for forming the same | |
CN106129003B (en) | The processing method of chip | |
US8557635B2 (en) | Stacked semiconductor device and manufacturing method thereof | |
EP1432032A3 (en) | Semiconductor chip stack and method for manufacturing the same | |
CN106997866A (en) | The processing method of chip | |
TWI579948B (en) | Semiconductor manufacturing apparatus and manufacturing method of semiconductor device | |
JP2011066340A5 (en) | ||
JP2007266191A (en) | Wafer processing method | |
US10490531B2 (en) | Manufacturing method of semiconductor device and semiconductor device | |
JP5968150B2 (en) | Wafer processing method | |
TWI354325B (en) | ||
CN104009002B (en) | The processing method of stacked wafers | |
CN104425334B (en) | The manufacturing method and semiconductor manufacturing apparatus of semiconductor device | |
CN107993937A (en) | The supplementary structure and the wafer processing method using the structure of a kind of interim bonding technology | |
CN108630743A (en) | Semiconductor device and its manufacturing method | |
CN104282581B (en) | Resin sheet method of attaching | |
TW201929103A (en) | Package structure and manufacturing method thereof | |
TWI234234B (en) | Method of segmenting a wafer | |
CN109216216A (en) | The manufacturing method of semiconductor packages | |
CN106298651A (en) | The processing method of wafer | |
JP7208062B2 (en) | Device chip forming method | |
US10811298B2 (en) | Patterned carrier wafers and methods of making and using the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |