CN104007607B - 产生方法和信息处理装置 - Google Patents

产生方法和信息处理装置 Download PDF

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Publication number
CN104007607B
CN104007607B CN201410053642.8A CN201410053642A CN104007607B CN 104007607 B CN104007607 B CN 104007607B CN 201410053642 A CN201410053642 A CN 201410053642A CN 104007607 B CN104007607 B CN 104007607B
Authority
CN
China
Prior art keywords
pattern elements
target pattern
pattern
substrate
elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201410053642.8A
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English (en)
Chinese (zh)
Other versions
CN104007607A (zh
Inventor
荒井祯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Publication of CN104007607A publication Critical patent/CN104007607A/zh
Application granted granted Critical
Publication of CN104007607B publication Critical patent/CN104007607B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
CN201410053642.8A 2013-02-22 2014-02-18 产生方法和信息处理装置 Expired - Fee Related CN104007607B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013033870A JP6141044B2 (ja) 2013-02-22 2013-02-22 生成方法、プログラム及び情報処理装置
JP2013-033870 2013-02-22

Publications (2)

Publication Number Publication Date
CN104007607A CN104007607A (zh) 2014-08-27
CN104007607B true CN104007607B (zh) 2018-01-26

Family

ID=51368335

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410053642.8A Expired - Fee Related CN104007607B (zh) 2013-02-22 2014-02-18 产生方法和信息处理装置

Country Status (5)

Country Link
US (1) US8943446B2 (https=)
JP (1) JP6141044B2 (https=)
KR (2) KR20140105379A (https=)
CN (1) CN104007607B (https=)
TW (1) TWI536093B (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6712527B2 (ja) * 2016-09-30 2020-06-24 株式会社ブイ・テクノロジー プロキシミティ露光方法
US10318698B2 (en) * 2016-12-14 2019-06-11 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for assigning color pattern
CN114638189B (zh) * 2022-03-16 2026-02-10 东方晶源微电子科技(北京)股份有限公司 一种解决掩模版着色边界冲突的方法、装置和计算机设备

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7018753B2 (en) * 2003-05-05 2006-03-28 Lsi Logic Corporation Variable mask field exposure
JP4585197B2 (ja) * 2003-12-22 2010-11-24 ルネサスエレクトロニクス株式会社 レイアウト設計方法およびフォトマスク
JP4229829B2 (ja) * 2003-12-26 2009-02-25 Ｎｅｃエレクトロニクス株式会社 ホールパターン設計方法、およびフォトマスク
US7310797B2 (en) 2005-05-13 2007-12-18 Cadence Design Systems, Inc. Method and system for printing lithographic images with multiple exposures
US7745067B2 (en) * 2005-07-28 2010-06-29 Texas Instruments Incorporated Method for performing place-and-route of contacts and vias in technologies with forbidden pitch requirements
JP2007258366A (ja) * 2006-03-22 2007-10-04 Toshiba Corp パターン処理方法
CN101657827B (zh) * 2007-04-19 2013-03-20 D-波系统公司 用于自动图像识别的系统、方法及装置
JP4779003B2 (ja) * 2007-11-13 2011-09-21 エーエスエムエル ネザーランズ ビー．ブイ． フルチップ設計のパターン分解を行うための方法
JP5100625B2 (ja) * 2008-12-11 2012-12-19 株式会社東芝 パターンレイアウト設計方法
US8402396B2 (en) 2009-09-29 2013-03-19 The Regents Of The University Of California Layout decomposition for double patterning lithography
US8448120B2 (en) * 2011-05-09 2013-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. RC extraction for single patterning spacer technique

Also Published As

Publication number Publication date
JP6141044B2 (ja) 2017-06-07
TW201433879A (zh) 2014-09-01
KR101682336B1 (ko) 2016-12-05
US8943446B2 (en) 2015-01-27
JP2014164054A (ja) 2014-09-08
CN104007607A (zh) 2014-08-27
US20140245241A1 (en) 2014-08-28
TWI536093B (zh) 2016-06-01
KR20160096573A (ko) 2016-08-16
KR20140105379A (ko) 2014-09-01

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Granted publication date: 20180126

Termination date: 20210218