CN103944564B - 三分正交分频器 - Google Patents

三分正交分频器 Download PDF

Info

Publication number
CN103944564B
CN103944564B CN201410195693.4A CN201410195693A CN103944564B CN 103944564 B CN103944564 B CN 103944564B CN 201410195693 A CN201410195693 A CN 201410195693A CN 103944564 B CN103944564 B CN 103944564B
Authority
CN
China
Prior art keywords
signal
phase signal
circuit
delayed
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410195693.4A
Other languages
English (en)
Chinese (zh)
Other versions
CN103944564A (zh
Inventor
乔东江
弗雷德里克·博苏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN103944564A publication Critical patent/CN103944564A/zh
Application granted granted Critical
Publication of CN103944564B publication Critical patent/CN103944564B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/42—Out-of-phase gating or clocking signals applied to counter stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks
    • H03H11/265—Time-delay networks with adjustable delay

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Superheterodyne Receivers (AREA)
CN201410195693.4A 2008-08-18 2009-08-18 三分正交分频器 Active CN103944564B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/193,693 2008-08-18
US12/193,693 US7825703B2 (en) 2008-08-18 2008-08-18 Divide-by-three quadrature frequency divider
CN200980131897.9A CN102124653B (zh) 2008-08-18 2009-08-18 三分正交分频器

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN200980131897.9A Division CN102124653B (zh) 2008-08-18 2009-08-18 三分正交分频器

Publications (2)

Publication Number Publication Date
CN103944564A CN103944564A (zh) 2014-07-23
CN103944564B true CN103944564B (zh) 2017-08-25

Family

ID=41170029

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201410195693.4A Active CN103944564B (zh) 2008-08-18 2009-08-18 三分正交分频器
CN200980131897.9A Active CN102124653B (zh) 2008-08-18 2009-08-18 三分正交分频器

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN200980131897.9A Active CN102124653B (zh) 2008-08-18 2009-08-18 三分正交分频器

Country Status (11)

Country Link
US (1) US7825703B2 (https=)
EP (2) EP2327159B1 (https=)
JP (1) JP5259823B2 (https=)
KR (1) KR101246962B1 (https=)
CN (2) CN103944564B (https=)
BR (1) BRPI0917342A2 (https=)
CA (1) CA2735676C (https=)
IN (1) IN2014CN03747A (https=)
RU (1) RU2479121C2 (https=)
TW (1) TW201015859A (https=)
WO (1) WO2010022092A1 (https=)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8344765B2 (en) * 2009-07-16 2013-01-01 Qualcomm, Incorporated Frequency divider with a configurable dividing ratio
WO2012050761A2 (en) * 2010-09-30 2012-04-19 Dow Corning Corporation Process for preparing an acryloyloxysilane
US8768994B2 (en) * 2010-10-22 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Filter auto-calibration using multi-clock generator
KR101292767B1 (ko) * 2011-09-06 2013-08-02 동국대학교 산학협력단 패스 트랜지스터 및 이를 포함하는 50% 듀티 싸이클을 갖는 홀수 주파수 분주기
US8803568B2 (en) * 2011-11-28 2014-08-12 Qualcomm Incorporated Dividing a frequency by 1.5 to produce a quadrature signal
US9065449B2 (en) * 2013-10-28 2015-06-23 Avago Technologies General Ip (Singapore) Pte. Ltd. High-speed divide-by-1.5 circuit with 50 percent duty cycle
CN104734695B (zh) 2013-12-24 2018-05-04 澜起科技（上海）有限公司 信号发生器、电子系统以及产生信号的方法
US9455716B2 (en) 2014-05-28 2016-09-27 Qualcomm Incorporated Reconfigurable fractional divider
CN105391444B (zh) * 2014-09-04 2018-07-20 中芯国际集成电路制造(上海)有限公司 一种分频电路和电子装置
US20160079985A1 (en) * 2014-09-16 2016-03-17 Qualcomm Incorporated Quadrature local oscillator phase synthesis and architecture for divide-by-odd-number frequency dividers
CN104575425B (zh) * 2015-01-09 2017-04-12 深圳市华星光电技术有限公司 扫描驱动电路及其与非门逻辑运算电路
US9705664B2 (en) 2015-06-18 2017-07-11 Mediatek Singapore Pte. Ltd. Synthesizer module, RF transceiver and method therefor
US10164574B2 (en) * 2015-07-07 2018-12-25 Mediatek Inc. Method for generating a plurality of oscillating signals with different phases and associated circuit and local oscillator
US9973182B2 (en) * 2016-09-14 2018-05-15 Qualcomm Incorporated Re-timing based clock generation and residual sideband (RSB) enhancement circuit
US10374588B2 (en) 2016-10-31 2019-08-06 Mediatek Inc. Quadrature clock generating mechanism of communication system transmitter
US10116290B1 (en) * 2017-12-07 2018-10-30 Speedlink Technology Inc. RF frontend having a wideband mm wave frequency doubler
CN113348627B (zh) * 2019-01-31 2024-09-17 华为技术有限公司 一种缓冲电路、分频电路以及通信设备
US10454462B1 (en) * 2019-04-18 2019-10-22 Hong Kong Applied Science and Technology Research Institute Company Limited 50% duty cycle quadrature-in and quadrature-out (QIQO) divide-by-3 circuit
US11646919B2 (en) * 2020-01-08 2023-05-09 Mediatek Singapore Pte. Ltd. IQ generator for mixer
US11264995B1 (en) * 2020-10-26 2022-03-01 Qualcomm Incorporated System and method for maintaining local oscillator (LO) phase continuity
RU2752485C1 (ru) * 2020-12-03 2021-07-28 Акционерное общество "ПКК МИЛАНДР" Делитель частоты с переменным коэффициентом деления
CN112787659B (zh) * 2020-12-30 2024-08-16 瑞声科技（南京）有限公司 三分频器电路
CN112994682B (zh) * 2021-05-10 2021-08-03 上海灵动微电子股份有限公司 基于开关电容的时钟分频器、微控制器和锁相环电路
CN115149943B (zh) * 2022-08-31 2022-11-22 上海韬润半导体有限公司 分频电路
US12407488B2 (en) * 2023-04-27 2025-09-02 Avago Technologies International Sales Pte. Limited Quadrature divider error correction

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4366394A (en) * 1980-09-25 1982-12-28 Rockwell International Corporation Divide by three clock divider with symmetrical output
US4399326A (en) * 1981-01-12 1983-08-16 Bode Harald E W Audio signal processing system
GB9727244D0 (en) 1997-12-23 1998-02-25 Sgs Thomson Microelectronics A dividing circuit and transistor stage therefor
JP2002026726A (ja) * 2000-07-07 2002-01-25 Mitsubishi Electric Corp 半導体集積回路
US6389095B1 (en) * 2000-10-27 2002-05-14 Qualcomm, Incorporated Divide-by-three circuit
US6960962B2 (en) * 2001-01-12 2005-11-01 Qualcomm Inc. Local oscillator leakage control in direct conversion processes
US7508273B2 (en) 2003-03-19 2009-03-24 Nxp B.V. Quadrature clock divider
RU2273860C2 (ru) * 2004-04-12 2006-04-10 федеральное государственное унитарное предприятие "Государственный Рязанский приборный завод" (ФГУП ГРПЗ) Когерентный приемник рлс с цифровым устройством для амплитудной и фазовой корректировки квадратурных составляющих принимаемого сигнала
NO323203B1 (no) * 2004-09-24 2007-01-22 Texas Instr Norway As Kvadratur dele-pa-tre frekvensdeler
JP4687082B2 (ja) * 2004-11-30 2011-05-25 セイコーエプソン株式会社 電子装置および無線通信端末
US7123103B1 (en) 2005-03-31 2006-10-17 Conexant Systems, Inc. Systems and method for automatic quadrature phase imbalance compensation using a delay locked loop
JP2009017528A (ja) * 2007-06-05 2009-01-22 Seiko Epson Corp パルス発生回路及びｕｗｂ通信装置
RU70059U1 (ru) * 2007-08-13 2008-01-10 Открытое акционерное общество "Концерн "Созвездие" Цифровой синтезатор частот
JP4675422B2 (ja) * 2009-03-30 2011-04-20 日本電信電話株式会社 無線送信機

Also Published As

Publication number Publication date
KR20110055663A (ko) 2011-05-25
IN2014CN03747A (https=) 2015-09-25
US7825703B2 (en) 2010-11-02
CN103944564A (zh) 2014-07-23
RU2011110168A (ru) 2012-09-27
EP2327159A1 (en) 2011-06-01
EP2797234A1 (en) 2014-10-29
CA2735676A1 (en) 2010-02-25
CN102124653A (zh) 2011-07-13
KR101246962B1 (ko) 2013-03-25
US20100039153A1 (en) 2010-02-18
RU2479121C2 (ru) 2013-04-10
EP2797234B1 (en) 2018-12-26
BRPI0917342A2 (pt) 2015-11-17
EP2797234A8 (en) 2014-12-03
CA2735676C (en) 2014-09-16
TW201015859A (en) 2010-04-16
JP2012500596A (ja) 2012-01-05
JP5259823B2 (ja) 2013-08-07
CN102124653B (zh) 2014-10-08
WO2010022092A1 (en) 2010-02-25
EP2327159B1 (en) 2015-01-14

Similar Documents

Publication Publication Date Title
CN103944564B (zh) 三分正交分频器
CN103329441B (zh) 多频段收发机中的本振生成和分配
CN102893522B (zh) 倍频收发器
CN101960720A (zh) 用于分数-n型锁相环的动态参考频率
CN105324938B (zh) 在反馈回路中具有占空比调整的分频器
KR20160101974A (ko) 지연 고정 루프들을 이용한 로컬 오실레이터 신호 생성
US7170965B2 (en) Low noise divider module for use in a phase locked loop and other applications
CN115668774A (zh) 基于采样的乘法延迟锁相环(mdll)的校准
CN107634757A (zh) 在锁相环路中使用参考时钟抖动来降低突波
EP1248378B1 (en) Transmitter and radio communication terminal using the same
US7521974B2 (en) Translational phase locked loop using a quantized interpolated edge timed synthesizer
US20130243113A1 (en) Generating and routing a sub-harmonic of a local oscillator signal
Mehr et al. Toward solving multichannel RF-SoC integration issues through digital fractional division
WO2012093424A1 (ja) デルタシグマ変調型分数分周ｐｌｌ周波数シンセサイザおよびそれを備えた無線通信装置
JPH11505090A (ja) Ｒｆ送信機用集積回路におけるスプリアス信号の低減
CN202696580U (zh) 双调谐锁相式快跳源
US10135451B2 (en) Method and device for doubling the frequency of a reference signal of a phase locked loop
US10862461B1 (en) Techniques for generating switch control signals
US8710932B2 (en) Signal processing device and method for providing oscillating signal in the signal processing device
Peng et al. High-performance Bluetooth transmitters using two-point delta-sigma modulation
Stadelmayer Edge-Combining: A Tool from Low-Power to High-Performance/submitted by Markus Stadelmayer, M. Sc.
Zhao et al. A PLL based WSN transmitter and I/Q LO signal generator at 430–435 MHz
Kameche et al. Simulating and Designing a PLL Frequency Synthesizer for GSM Communications

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant