CN103904207A - 晶片电路 - Google Patents

晶片电路 Download PDF

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Publication number
CN103904207A
CN103904207A CN201410137106.6A CN201410137106A CN103904207A CN 103904207 A CN103904207 A CN 103904207A CN 201410137106 A CN201410137106 A CN 201410137106A CN 103904207 A CN103904207 A CN 103904207A
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China
Prior art keywords
electrode
pad
many root
root beads
beads line
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CN201410137106.6A
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English (en)
Inventor
卢长军
潘彤
余杰
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Leyard Optoelectronic Co Ltd
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Leyard Optoelectronic Co Ltd
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Publication date
Application filed by Leyard Optoelectronic Co Ltd filed Critical Leyard Optoelectronic Co Ltd
Priority to CN201410137106.6A priority Critical patent/CN103904207A/zh
Publication of CN103904207A publication Critical patent/CN103904207A/zh
Priority to US15/111,774 priority patent/US20170025376A1/en
Priority to EP14887860.6A priority patent/EP3128552A4/en
Priority to PCT/CN2014/084027 priority patent/WO2015149462A1/zh
Priority to CA2936655A priority patent/CA2936655A1/en
Priority to JP2016543228A priority patent/JP6317454B2/ja
Priority to KR1020167017046A priority patent/KR20160142276A/ko
Pending legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Led Device Packages (AREA)

Abstract

本发明公开了一种晶片电路。该晶片电路包括：晶片，固定在基板上；电极，设置在晶片上；焊盘，设置在基板上；以及多根焊线，多根焊线的第一端均连接至电极，多根焊线的第二端均连接至焊盘，其中，多根焊线为并联焊线。通过本发明，解决了相关技术中晶片电路容易发生异常的问题。

Description

晶片电路
技术领域
本发明涉及电路领域，具体而言，涉及一种晶片电路。
背景技术
晶片是发光二极管（Light Emitting Diode，简称为LED）的原材料，LED主要依靠晶片发光。晶片相当于P型材料和N型材料形成的PN结。当P型材料的空穴和N型材料的电子复合时，会以光子的形式发出能量，从而使LED发光。
在现有技术的晶片电路中，晶片上的一个电极对应一个焊盘，并且电极与焊盘之间通过一根焊线相连接而形成电路。这样，如果焊线损坏，晶片电路就会发生异常，从而晶片的PN结就不会导通，也不会产生空穴与电子的复合，进而影响LED的正常使用。
如图1所示，该晶片电路包括晶片10’、一个电极20’、一个焊盘30’和一根焊线40’，其中，电极20’设置在晶片10’上，并且该电极20’通过该焊线40’连接至该焊盘30’，焊盘30’和晶片10’均设置在基板上，这样，一旦焊线40’损坏，则整个晶片电路就会发生异常。
针对相关技术中晶片电路容易发生异常的问题，目前尚未提出有效的解决方案。
发明内容
本发明的主要目的在于提供一种晶片电路，以解决相关技术中晶片电路容易发生异常的问题。
为了实现上述目的，根据本发明，提供了一种晶片电路。该晶片电路包括：晶片，固定在基板上；电极，设置在晶片上；焊盘，设置在基板上；以及多根焊线，多根焊线的第一端均连接至电极，多根焊线的第二端均连接至焊盘，其中，多根焊线为并联焊线。
进一步地，电极为一个电极，焊盘为一个焊盘，多根焊线的第一端均连接至电极，多根焊线的第二端均连接至焊盘包括：多根焊线的第一端均连接至一个电极，多根焊线的第二端均至一个焊盘。
进一步地，电极为一个电极，焊盘为多个焊盘，多根焊线的第一端均连接至电极，多根焊线的第二端均连接至焊盘包括：多根焊线的第一端均连接至一个电极，多根焊线的第二端连接至多个焊盘中的任一焊盘。
进一步地，电极为一个电极，焊盘为多个焊盘，多根焊线的第一端均连接至电极，多根焊线的第二端均连接至焊盘包括：多根焊线的第一端均连接至一个电极，多根焊线的第二端连接至多个焊盘中的不同焊盘。
进一步地，电极包括第一电极和第二电极，焊盘包括第一焊盘和第二焊盘，多根焊线包括第一焊线和第二焊线，多根焊线的第一端均连接至电极，多根焊线的第二端均连接至焊盘包括：第一焊线的第一端连接至第一电极，第一焊线的第二端连接至第一焊盘，第二焊线的第一端连接至第二电极，第二焊线的第二端连接至第二焊盘。
进一步地，电极为多个电极，焊盘为一个焊盘，多根焊线的第一端均连接至电极，多根焊线的第二端均连接至焊盘包括：多根焊线的第一端连接至多个电极中的任一电极，多根焊线的第二端均连接至一个焊盘。
进一步地，电极为多个电极，焊盘为一个焊盘，多根焊线的第一端均连接至电极，多根焊线的第二端均连接至焊盘包括：多根焊线的第一端连接至多个电极中的不同电极，多根焊线的第二端均连接至一个焊盘。
进一步地，电极为多个电极，焊盘为多个焊盘，多根焊线的第一端均连接至电极，多根焊线的第二端均连接至焊盘包括：多根焊线的第一端连接至多个电极中的任一电极，多根焊线的第二端连接至多个焊盘中的任一焊盘。
进一步地，电极为多个电极，焊盘为多个焊盘，多根焊线的第一端均连接至电极，多根焊线的第二端均连接至焊盘包括：多根焊线的第一端连接至多个电极中的不同电极，多根焊线的第二端连接至多个焊盘中的不同焊盘。
进一步地，电极为多个电极，焊盘为多个焊盘，多根焊线的第一端均连接至电极，多根焊线的第二端均连接至焊盘包括：多根焊线的第一端连接至多个电极中的任一电极，多根焊线的第二端连接至多个焊盘中的不同焊盘。
进一步地，电极为多个电极，焊盘为多个焊盘，多根焊线的第一端均连接至电极，多根焊线的第二端均连接至焊盘包括：多根焊线的第一端连接至多个电极中的不同电极，多根焊线的第二端连接至多个焊盘中的任一焊盘。
进一步地，电极同时设置在晶片的P型材料侧或者同时设置在晶片的N型材料侧。
通过本发明，采用晶片，固定在基板上；电极，设置在晶片上；焊盘，设置在基板上；以及多根焊线，多根焊线的第一端均连接至电极，多根焊线的第二端均连接至焊盘，其中，多根焊线为并联焊线，这样，即使某根或者某几根焊线损坏，电极与焊盘之间也不会断开，解决了相关技术中晶片电路容易发生异常的问题，进而达到了降低晶片电路发生异常的概率的效果。
附图说明
构成本申请的一部分的附图用来提供对本发明的进一步理解，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1是根据相关技术的晶片电路的示意图；
图2是根据本发明实施例的晶片电路的示意图；以及
图3是根据本发明优选实施例的晶片电路的示意图。
具体实施方式
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本发明。
为了使本领域的技术人员更好的理解本发明方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分的实施例，而不是全部的实施例。基于本发明中的实施例，在本领域普通技术人员没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本发明的保护范围。
需要说明的是，本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本发明的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含。
根据本发明的实施例，提供了一种晶片电路，该晶片电路用于采用多根焊线来降低晶片电路发生异常的概率。
图2是根据本发明实施例的晶片电路的示意图。如图2所示，该晶片电路包括：晶片10、电极20、焊盘30和焊线40，其中，焊线40包括任意多根，在本实施例中以焊线40为3根进行描述。
晶片10固定在基板上。其中，可以通过胶水将晶片10固定在基板上。胶水可以是银胶或者绝缘胶。基板可以是PCB板。
电极20设置在晶片10上。具体地，电极20可以包括一个或者多个，当电极20为一个时，其可以设置在晶片10的P型材料侧或者N型材料侧；当电极20为多个时，该多个电极20可以同时设置在晶片10的P型材料侧或者同时设置在晶片10的N型材料侧。
焊盘30设置在基板上。其中，焊盘30可以为一个或者多个。当焊盘30为一个时，连接在电极20和焊盘30之间的多根焊线40必然为并联焊线。当焊盘30为多个时，多个焊盘30可以通过基板上的焊线连接在一起。这样，可以使得多个焊盘30与电极20之间的多根焊线40为并联焊线。
多根焊线40的第一端均连接至电极20，并且该多根焊线40的第二端均连接至焊盘30。其中，多根焊线40为并联焊线。在本实施例中，该三根焊线分别为焊线401、焊线402和焊线403，该三根焊线的第一端均连接至电极20，并且该3根焊线的第二端均连接至焊盘30。
在本发明实施例中，电极20可以是晶片10上仅仅设置有的一种电极，即第一种电极，此时如果电极20设置在晶片10的P型材料侧，则电极20的极性为“+”，其可以通过多根焊线30连接至基板上的“+”极，并且晶片10的N型材料侧可以直接与基板上的“-”极相连接。这样在接通电源时，晶片10的PN结可以导通，从而可以产生空穴与电子的复合，并且以光子的形式产生能量，从而可以使得LED发光。当然，此时如果电极20设置在晶片10的N型材料侧，则电极20的极性为“-”，其可以通过多根焊线30连接至基板上的“-”极，并且晶片10的P型材料侧可以直接与基板上的“+”极相连接。这样在接通电源时，晶片10的PN结可以导通，从而可以产生空穴与电子的复合，并且以光子的形式产生能量，进而可以使得LED发光。
另外，在本发明实施例中，晶片10上除了设置有电极20这一种电极（即第一种电极）之外，还可以设置有第二种电极，此时如果电极20设置在晶片10的P型材料侧，则电极20的极性为“+”，其可以通过多根焊线30连接至基板上的“+”极，并且第二种电极可以与基板上的“-”极相连接。这样在接通电源时，晶片10的PN结可以导通，从而可以产生空穴与电子的复合，并且以光子的形式产生能量，从而可以使得LED发光。当然，此时如果电极20设置在晶片10的N型材料侧，则电极20的极性为“-”，其可以通过多根焊线30连接至基板上的“-”极，并且第二种电极可以与基板上的“+”极相连接。这样在接通电源时，晶片10的PN结可以导通，从而可以产生空穴与电子的复合，并且以光子的形式产生能量，进而可以使得LED发光。
通过本发明实施例，将多根焊线40连接在电极20和焊盘30之间，这样，即使一根或者多根焊线40中的部分焊线40损坏，只要还有至少一根焊线40连接在电极20和焊盘30之间，则晶片电路就不会发生异常，从而达到了降低晶片电路发生异常的概率的效果。
需要说明的是，在本发明实施例中，电极20和焊盘30均可以为一个或者多个。如果电极20和/或焊盘30为多个，则可以避免因为电极20损坏和/或焊盘30脱落而造成晶片电路异常。通过在晶片电路中设置多根焊线40和/或多个电极20和/或多个焊盘30，可以为晶片电路提供多层保护，防止晶片电路由于焊线40损坏和/或电极损坏和/或焊盘30脱落等原因产生异常。其中，在电极20和焊盘30均可以为一个或者多个的情况下，该晶片电路中电极20和焊盘30的组合方式以及相应的连接方式可以如下：
方式一，当电极20为一个电极，并且焊盘30也为一个焊盘时，多根焊线40的第一端可以均连接至该同一个电极20上，多根焊线40的第二端可以均至该同一个焊盘40上，并且这样连接之后，多根焊线40必然为并联焊线。由于电极20与焊盘30之间通过多根焊线40连通，因此不管是否有焊线40损坏，只要电极20与焊盘30之间还存在有完好的焊线40即可保证电极20与焊盘30之间是连通的，从而可以保证晶片电路正常。
方式二，当电极20为一个电极，而焊盘30为多个焊盘时，其中，多个焊盘30分别设置在基板的不同位置，多根焊线40的第一端可以均连接至同一个电极20上，多根焊线40的第二端可以连接至上述多个焊盘30中的任一焊盘30。需要说明的是，连接在任一焊盘30上的多根焊线40为并联焊线。由于电极20与焊盘30之间通过多根焊线40连通，因此不管是否有焊线40损坏，只要电极20与焊盘30之间还存在有完好的焊线40即可保证电极20与焊盘30之间是连通的，从而可以保证晶片电路正常。同时，由于并联的多根焊线40可以连接在多个焊盘30上，这样，即使有焊盘30脱落，也不会影响整个晶片电路的正常。
方式三，当电极20为一个电极，而焊盘30为多个焊盘时，其中，多个焊盘30分别设置在基板的不同位置，多根焊线40的第一端可以均连接至同一个电极20上，多根焊线的第二端可以连接至上述多个焊盘30中的不同焊盘30。需要说明的是，连接在不同焊盘30上的多根焊线40为并联焊线。基于与方式二相同的原因（在此不再赘述），即使有焊盘30脱落，也不会影响整个晶片电路的正常。
方式四，当电极20包括第一电极201和第二电极202，焊盘30包括第一焊盘301和第二焊盘302，多根焊线40包括第一焊线404和第二焊线405时，其中，第一电极和第二电极同时设置在晶片10的P型材料侧或者N型材料侧，但是两者的位置不同，并且第一焊盘和第二焊盘分别设置在基板的不同位置上，第一焊线的第一端可以连接至第一电极，第一焊线的第二端可以连接至第一焊盘，第二焊线的第一端可以连接至第二电极，第二焊线的第二端可以连接至第二焊盘，第一焊线和第二焊线为并联焊线。由于第一电极和第一焊盘之间以及第二电极和第二焊盘之间分别连接了相互并联的第一焊线和第二焊线，因此只要第一焊线和第二焊线中有一根完好或者两者均完好，则整个晶片电路就不会产生异常。同时，由于不同的焊线连接至不同的电极和不同焊盘，因此即使有一个电极或者一个焊盘损坏，则整个晶片电路也不会产生异常。在此，电极20、焊盘30和焊线40为晶片电路提供了多层保护。如图3所示。
方式五，当电极20为多个电极，而焊盘30为一个焊盘时，多根焊线40的第一端可以连接至多个电极20中的任一电极，多根焊线40的第二端可以均连接至该同一个焊盘30上。其中，多根焊线40为并联焊线。由于电极20与焊盘30之间通过多根焊线40连通，因此不管是否有焊线40损坏，只要电极20与焊盘30之间还存在有完好的焊线40即可保证电极20与焊盘30之间是连通的，从而可以保证晶片电路正常。同时，由于并联的多根焊线40可以连接在多个电极20上，这样，即使有电极20损坏，也不会影响整个晶片电路的正常。
方式六，当电极20为多个电极，焊盘30为一个焊盘时，多根焊线40的第一端可以连接至多个电极20中的不同电极，多根焊线40的第二端可以均连接至该同一个焊盘30上。其中，多根焊线40为并联焊线。基于与方式五相同的原因（在此不再赘述），即使有电极20损坏，也不会影响整个晶片电路的正常。
方式七，当电极20为多个电极，且焊盘30也为多个焊盘时，多根焊线40的第一端可以连接至多个电极20中的任一电极，多根焊线的第二端可以连接至多个焊盘40中的任一焊盘。其中，多根焊线40为并联焊线。基于与方式二和方式五相同的原因（在此不再赘述），即使有电极20损坏，或者有焊盘30脱落，或者有焊线30损坏，也不会影响整个晶片电路的正常。
方式八，当电极20为多个电极，且焊盘30为多个焊盘时，多根焊线40的第一端连接至多个电极20中的不同电极，多根焊线40的第二端连接至多个焊盘30中的不同焊盘。其中，多根焊线40为并联焊线。基于与方式七相同的原因（在此不再赘述），即使有电极20损坏，或者有焊盘30脱落，或者有焊线30损坏，也不会影响整个晶片电路的正常。
方式九，当电极20为多个电极，且焊盘20为多个焊盘时，多根焊线40的第一端可以连接至多个电极20中的任一电极，多根焊线40的第二端可以连接至多个焊盘30中的不同焊盘。基于与方式七相同的原因（在此不再赘述），即使有电极20损坏，或者有焊盘30脱落，或者有焊线30损坏，也不会影响整个晶片电路的正常。
方式十，当电极20为多个电极，焊盘30为多个焊盘时，多根焊线40的第一端可以连接至多个电极20中的不同电极，多根焊线40的第二端可以连接至多个焊盘30中的任一焊盘。基于与方式七相同的原因（在此不再赘述），即使有电极20损坏，或者有焊盘30脱落，或者有焊线30损坏，也不会影响整个晶片电路的正常。
可选地，在本发明实施例中，当电极20为多个电极20时，该多个电极20可以同时设置在晶片10的P型材料侧或者同时设置在晶片10的N型材料侧。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (12)

1.一种晶片电路，其特征在于，包括：
晶片，固定在基板上；
电极，设置在所述晶片上；
焊盘，设置在所述基板上；以及
多根焊线，所述多根焊线的第一端均连接至所述电极，所述多根焊线的第二端均连接至所述焊盘，其中，所述多根焊线为并联焊线。
2.根据权利要求1所述的晶片电路，其特征在于，所述电极为一个电极，所述焊盘为一个焊盘，
所述多根焊线的第一端均连接至所述电极，所述多根焊线的第二端均连接至所述焊盘包括：所述多根焊线的第一端均连接至所述一个电极，所述多根焊线的第二端均至所述一个焊盘。
3.根据权利要求1所述的晶片电路，其特征在于，所述电极为一个电极，所述焊盘为多个焊盘，
所述多根焊线的第一端均连接至所述电极，所述多根焊线的第二端均连接至所述焊盘包括：所述多根焊线的第一端均连接至所述一个电极，所述多根焊线的第二端连接至所述多个焊盘中的任一焊盘。
4.根据权利要求1所述的晶片电路，其特征在于，所述电极为一个电极，所述焊盘为多个焊盘，
所述多根焊线的第一端均连接至所述电极，所述多根焊线的第二端均连接至所述焊盘包括：所述多根焊线的第一端均连接至所述一个电极，所述多根焊线的第二端连接至所述多个焊盘中的不同焊盘。
5.根据权利要求1所述的晶片电路，其特征在于，所述电极包括第一电极和第二电极，所述焊盘包括第一焊盘和第二焊盘，所述多根焊线包括第一焊线和第二焊线，
所述多根焊线的第一端均连接至所述电极，所述多根焊线的第二端均连接至所述焊盘包括：所述第一焊线的第一端连接至所述第一电极，所述第一焊线的第二端连接至所述第一焊盘，所述第二焊线的第一端连接至所述第二电极，所述第二焊线的第二端连接至所述第二焊盘。
6.根据权利要求1所述的晶片电路，其特征在于，所述电极为多个电极，所述焊盘为一个焊盘，
所述多根焊线的第一端均连接至所述电极，所述多根焊线的第二端均连接至所述焊盘包括：所述多根焊线的第一端连接至所述多个电极中的任一电极，所述多根焊线的第二端均连接至所述一个焊盘。
7.根据权利要求1所述的晶片电路，其特征在于，所述电极为多个电极，所述焊盘为一个焊盘，
所述多根焊线的第一端均连接至所述电极，所述多根焊线的第二端均连接至所述焊盘包括：所述多根焊线的第一端连接至所述多个电极中的不同电极，所述多根焊线的第二端均连接至所述一个焊盘。
8.根据权利要求1所述的晶片电路，其特征在于，所述电极为多个电极，所述焊盘为多个焊盘，
所述多根焊线的第一端均连接至所述电极，所述多根焊线的第二端均连接至所述焊盘包括：所述多根焊线的第一端连接至所述多个电极中的任一电极，所述多根焊线的第二端连接至所述多个焊盘中的任一焊盘。
9.根据权利要求1所述的晶片电路，其特征在于，所述电极为多个电极，所述焊盘为多个焊盘，
所述多根焊线的第一端均连接至所述电极，所述多根焊线的第二端均连接至所述焊盘包括：所述多根焊线的第一端连接至所述多个电极中的不同电极，所述多根焊线的第二端连接至所述多个焊盘中的不同焊盘。
10.根据权利要求1所述的晶片电路，其特征在于，所述电极为多个电极，所述焊盘为多个焊盘，
所述多根焊线的第一端均连接至所述电极，所述多根焊线的第二端均连接至所述焊盘包括：所述多根焊线的第一端连接至所述多个电极中的任一电极，所述多根焊线的第二端连接至所述多个焊盘中的不同焊盘。
11.根据权利要求1所述的晶片电路，其特征在于，所述电极为多个电极，所述焊盘为多个焊盘，
所述多根焊线的第一端均连接至所述电极，所述多根焊线的第二端均连接至所述焊盘包括：所述多根焊线的第一端连接至所述多个电极中的不同电极，所述多根焊线的第二端连接至所述多个焊盘中的任一焊盘。
12.根据权利要求5至11任一项所述的晶片电路，其特征在于，所述电极同时设置在所述晶片的P型材料侧或者同时设置在所述晶片的N型材料侧。
CN201410137106.6A 2014-04-04 2014-04-04 晶片电路 Pending CN103904207A (zh)

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PCT/CN2014/084027 WO2015149462A1 (zh) 2014-04-04 2014-08-08 晶片电路
CA2936655A CA2936655A1 (en) 2014-04-04 2014-08-08 Wafer circuit
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