CN103875038B - 减少多端口sram存储器单元中的泄漏功率的方法和设备 - Google Patents
减少多端口sram存储器单元中的泄漏功率的方法和设备 Download PDFInfo
- Publication number
- CN103875038B CN103875038B CN201280047908.7A CN201280047908A CN103875038B CN 103875038 B CN103875038 B CN 103875038B CN 201280047908 A CN201280047908 A CN 201280047908A CN 103875038 B CN103875038 B CN 103875038B
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- Prior art keywords
- memory
- write
- bit line
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/249,297 | 2011-09-30 | ||
| US13/249,297 US8824230B2 (en) | 2011-09-30 | 2011-09-30 | Method and apparatus of reducing leakage power in multiple port SRAM memory cell |
| PCT/US2012/058178 WO2013049763A1 (en) | 2011-09-30 | 2012-09-30 | Method and apparatus of reducing leakage power in multiple port sram memory cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103875038A CN103875038A (zh) | 2014-06-18 |
| CN103875038B true CN103875038B (zh) | 2017-05-03 |
Family
ID=47073525
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201280047908.7A Active CN103875038B (zh) | 2011-09-30 | 2012-09-30 | 减少多端口sram存储器单元中的泄漏功率的方法和设备 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US8824230B2 (enExample) |
| EP (1) | EP2761621B1 (enExample) |
| JP (1) | JP5914671B2 (enExample) |
| KR (1) | KR101536233B1 (enExample) |
| CN (1) | CN103875038B (enExample) |
| IN (1) | IN2014CN01829A (enExample) |
| WO (1) | WO2013049763A1 (enExample) |
Families Citing this family (34)
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| US9093135B2 (en) * | 2012-11-15 | 2015-07-28 | Nvidia Corporation | System, method, and computer program product for implementing a storage array |
| US8947967B2 (en) * | 2012-12-21 | 2015-02-03 | Advanced Micro Devices Inc. | Shared integrated sleep mode regulator for SRAM memory |
| US9007817B2 (en) * | 2013-05-06 | 2015-04-14 | Qualcomm Incorporated | Pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power, and related systems and methods |
| US9442675B2 (en) | 2013-05-08 | 2016-09-13 | Qualcomm Incorporated | Redirecting data from a defective data entry in memory to a redundant data entry prior to data access, and related systems and methods |
| US9588573B2 (en) | 2013-10-28 | 2017-03-07 | Globalfoundries Inc. | Reduced-power trace array for a processor |
| US20150310901A1 (en) * | 2014-04-24 | 2015-10-29 | Qualcomm Incorporated | Memory with a sleep mode |
| US9671855B2 (en) * | 2014-06-30 | 2017-06-06 | Micron Technology, Inc. | Apparatuses and methods of entering unselected memories into a different power mode during multi-memory operation |
| US9564441B2 (en) | 2014-09-25 | 2017-02-07 | Kilopass Technology, Inc. | Two-transistor SRAM semiconductor structure and methods of fabrication |
| US9449669B2 (en) | 2014-09-25 | 2016-09-20 | Kilopass Technology, Inc. | Cross-coupled thyristor SRAM circuits and methods of operation |
| US9741413B2 (en) | 2014-09-25 | 2017-08-22 | Kilopass Technology, Inc. | Methods of reading six-transistor cross-coupled thyristor-based SRAM memory cells |
| CN106030718A (zh) * | 2014-09-25 | 2016-10-12 | 克劳帕斯科技有限公司 | 保持和刷新闸流晶体管随机存取存储器中的数据的方法 |
| US9496021B2 (en) | 2014-09-25 | 2016-11-15 | Kilopass Technology, Inc. | Power reduction in thyristor random access memory |
| US9530482B2 (en) | 2014-09-25 | 2016-12-27 | Kilopass Technology, Inc. | Methods of retaining and refreshing data in a thyristor random access memory |
| US20160093624A1 (en) | 2014-09-25 | 2016-03-31 | Kilopass Technology, Inc. | Thyristor Volatile Random Access Memory and Methods of Manufacture |
| US9460771B2 (en) | 2014-09-25 | 2016-10-04 | Kilopass Technology, Inc. | Two-transistor thyristor SRAM circuit and methods of operation |
| US9613968B2 (en) | 2014-09-25 | 2017-04-04 | Kilopass Technology, Inc. | Cross-coupled thyristor SRAM semiconductor structures and methods of fabrication |
| EP3149735A4 (en) * | 2014-09-25 | 2018-06-13 | Kilopass Technology, Inc. | Power reduction in thyristor random access memory |
| US9564199B2 (en) | 2014-09-25 | 2017-02-07 | Kilopass Technology, Inc. | Methods of reading and writing data in a thyristor random access memory |
| US9384825B2 (en) * | 2014-09-26 | 2016-07-05 | Qualcomm Incorporated | Multi-port memory circuits |
| US10431269B2 (en) * | 2015-02-04 | 2019-10-01 | Altera Corporation | Methods and apparatus for reducing power consumption in memory circuitry by controlling precharge duration |
| KR101674803B1 (ko) | 2015-04-17 | 2016-11-22 | 경희대학교 산학협력단 | 메모리 장치 및 그 동작 방법 |
| CN105304123B (zh) * | 2015-12-04 | 2018-06-01 | 上海兆芯集成电路有限公司 | 静态随机存取存储器 |
| KR101927583B1 (ko) | 2016-04-21 | 2018-12-10 | 연세대학교 산학협력단 | 로컬 비트 라인 공유 메모리 소자 및 그 구동 방법 |
| US9761304B1 (en) | 2016-09-27 | 2017-09-12 | International Business Machines Corporation | Write-bitline control in multicore SRAM arrays |
| US9837143B1 (en) | 2016-10-12 | 2017-12-05 | International Business Machines Corporation | NAND-based write driver for SRAM |
| US10249362B2 (en) * | 2016-12-06 | 2019-04-02 | Gsi Technology, Inc. | Computational memory cell and processing array device using the memory cells for XOR and XNOR computations |
| KR102021601B1 (ko) * | 2017-09-22 | 2019-09-16 | 경북대학교 산학협력단 | 초저전압 메모리 장치 및 그 동작 방법 |
| US10762934B2 (en) * | 2018-06-28 | 2020-09-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Leakage pathway prevention in a memory storage device |
| CN113287170B (zh) * | 2019-01-05 | 2025-02-28 | 美商新思科技有限公司 | 存储数据的集成电路和存储该集成电路的数字表示的介质 |
| US20190228821A1 (en) * | 2019-03-29 | 2019-07-25 | Intel Corporation | Programmable High-Speed and Low-power Mode FPGA Memory with Configurable Floating Bitlines Scheme |
| EP4356429A4 (en) * | 2021-06-18 | 2025-08-13 | Univ Southern California | AUGMENTED MEMORY COMPUTING: A NEW PATH FOR EFFICIENT AI COMPUTING |
| CN116978425A (zh) * | 2022-04-29 | 2023-10-31 | 三星电子株式会社 | 多阵列同步随机访问存储器(sram)的全局数据线 |
| US12412623B2 (en) * | 2022-06-08 | 2025-09-09 | Arm Limited | Precharge circuitry for use with bitlines |
| US11940493B1 (en) * | 2022-09-16 | 2024-03-26 | Nvidia Corp. | Flexible one-hot decoding logic for clock controls |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004095000A (ja) * | 2002-08-29 | 2004-03-25 | Fujitsu Ltd | スタティック型半導体記憶装置およびその制御方法 |
| JP2004355760A (ja) * | 2003-05-30 | 2004-12-16 | Renesas Technology Corp | データ記憶回路 |
| JP2010510615A (ja) * | 2006-11-17 | 2010-04-02 | フリースケール セミコンダクター インコーポレイテッド | 改良形書込み動作を行う2ポートsram |
| JP2011519109A (ja) * | 2008-04-24 | 2011-06-30 | クゥアルコム・インコーポレイテッド | 電気的メモリ動作におけるダイナミック電力セービングのためのシステム及び方法 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3252666B2 (ja) * | 1995-08-14 | 2002-02-04 | 日本電気株式会社 | 半導体記憶装置 |
| JPH11261017A (ja) * | 1998-03-16 | 1999-09-24 | Fujitsu Ltd | 半導体記憶装置 |
| JPH11345486A (ja) * | 1998-06-01 | 1999-12-14 | Mitsubishi Electric Corp | セルフ・リフレッシュ制御回路を備えたdramおよびシステムlsi |
| JP3866594B2 (ja) * | 2002-03-15 | 2007-01-10 | Necエレクトロニクス株式会社 | 遅延回路と半導体記憶装置及び半導体記憶装置の制御方法 |
| US7365432B2 (en) * | 2004-08-23 | 2008-04-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory cell structure |
| US7082073B2 (en) * | 2004-12-03 | 2006-07-25 | Micron Technology, Inc. | System and method for reducing power consumption during extended refresh periods of dynamic random access memory devices |
| US20070242498A1 (en) | 2006-04-13 | 2007-10-18 | Anantha Chandrakasan | Sub-threshold static random access memory |
| US7619916B2 (en) | 2006-07-06 | 2009-11-17 | Stmicroelectronics Pvt. Ltd. | 8-T SRAM cell circuit, system and method for low leakage current |
| WO2008088135A1 (en) * | 2007-01-16 | 2008-07-24 | Chungbuk National University Industry-Academic Cooperation Foundation | Multiple valued dynamic random access memory cell and thereof array using single electron transistor |
| US7564725B2 (en) | 2007-08-31 | 2009-07-21 | Texas Instruments Incorporated | SRAM bias for read and write |
| KR101488166B1 (ko) | 2008-03-26 | 2015-02-02 | 삼성전자주식회사 | 정적 메모리 장치 및 라이트 어시시트 기능을 구비하는에스램 |
| JP2009295229A (ja) * | 2008-06-05 | 2009-12-17 | Toshiba Corp | 半導体記憶装置 |
| US7961499B2 (en) | 2009-01-22 | 2011-06-14 | Qualcomm Incorporated | Low leakage high performance static random access memory cell using dual-technology transistors |
| US7986566B2 (en) | 2009-04-01 | 2011-07-26 | Texas Instruments Incorporated | SRAM cell with read buffer controlled for low leakage current |
| US8159863B2 (en) | 2009-05-21 | 2012-04-17 | Texas Instruments Incorporated | 6T SRAM cell with single sided write |
| US8982659B2 (en) | 2009-12-23 | 2015-03-17 | Intel Corporation | Bitline floating during non-access mode for memory arrays |
| JP5621704B2 (ja) * | 2011-05-11 | 2014-11-12 | 富士通セミコンダクター株式会社 | 半導体記憶装置 |
-
2011
- 2011-09-30 US US13/249,297 patent/US8824230B2/en active Active
-
2012
- 2012-09-30 EP EP12777992.4A patent/EP2761621B1/en active Active
- 2012-09-30 WO PCT/US2012/058178 patent/WO2013049763A1/en not_active Ceased
- 2012-09-30 CN CN201280047908.7A patent/CN103875038B/zh active Active
- 2012-09-30 IN IN1829CHN2014 patent/IN2014CN01829A/en unknown
- 2012-09-30 KR KR1020147011835A patent/KR101536233B1/ko active Active
- 2012-09-30 JP JP2014533456A patent/JP5914671B2/ja active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004095000A (ja) * | 2002-08-29 | 2004-03-25 | Fujitsu Ltd | スタティック型半導体記憶装置およびその制御方法 |
| JP2004355760A (ja) * | 2003-05-30 | 2004-12-16 | Renesas Technology Corp | データ記憶回路 |
| JP2010510615A (ja) * | 2006-11-17 | 2010-04-02 | フリースケール セミコンダクター インコーポレイテッド | 改良形書込み動作を行う2ポートsram |
| JP2011519109A (ja) * | 2008-04-24 | 2011-06-30 | クゥアルコム・インコーポレイテッド | 電気的メモリ動作におけるダイナミック電力セービングのためのシステム及び方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101536233B1 (ko) | 2015-07-13 |
| JP5914671B2 (ja) | 2016-05-11 |
| US8824230B2 (en) | 2014-09-02 |
| JP2014528629A (ja) | 2014-10-27 |
| WO2013049763A1 (en) | 2013-04-04 |
| EP2761621B1 (en) | 2023-10-18 |
| CN103875038A (zh) | 2014-06-18 |
| IN2014CN01829A (enExample) | 2015-05-29 |
| KR20140079445A (ko) | 2014-06-26 |
| EP2761621A1 (en) | 2014-08-06 |
| US20130083613A1 (en) | 2013-04-04 |
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| GR01 | Patent grant | ||
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