CN103871917B - The method preparing semiconductor failure analysis sample - Google Patents
The method preparing semiconductor failure analysis sample Download PDFInfo
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- CN103871917B CN103871917B CN201210526393.0A CN201210526393A CN103871917B CN 103871917 B CN103871917 B CN 103871917B CN 201210526393 A CN201210526393 A CN 201210526393A CN 103871917 B CN103871917 B CN 103871917B
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- failure analysis
- described test
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- test section
- semiconductor failure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
- G01N1/32—Polishing; Etching
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
- G01N1/286—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q involving mechanical work, e.g. chopping, disintegrating, compacting, homogenising
- G01N2001/2873—Cutting or cleaving
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- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Biochemistry (AREA)
- General Health & Medical Sciences (AREA)
- General Physics & Mathematics (AREA)
- Immunology (AREA)
- Pathology (AREA)
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Sampling And Sample Adjustment (AREA)
Abstract
The present invention proposes a kind of method preparing semiconductor failure analysis sample, first described test chip carries out cutting form initial sample and expose the facet of described test section at described initial sample one jiao, one jiao that and then described initial sample exposes described test section facet is cut, make facet vertical with the orientation of described test section, such that it is able to measure the characteristic size of described test section accurately.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of method preparing semiconductor failure analysis sample.
Background technology
Along with the development of semiconductor processing industry, the dimensions of semiconductor devices designing and manufacturing and circuit parameter are increasingly
Little, the factor of the performance affecting semiconductor device accordingly is also more and more.Therefore, in the design process of semiconductor device,
For making the semiconductor device designed have higher reliability and effectiveness, it is generally required to according to the design of semiconductor device
Method prepares corresponding semiconductor device sample, and semiconductor device sample carries out failure analysis, and then can divide according to losing efficacy
The result of analysis, is optimized the design of semiconductor device, so that manufacture according to the design of semiconductor device
Reliability and the effectiveness of semiconductor device are sufficiently ensured.
Along with the raising of semiconductor device integrated level, the component structure forming semiconductor device becomes the complicated knot of three-dimensional
Structure, in order to obtain sufficiently large capacity in the region limited.The increase of complexity of semiconductor devices so that only by outside
The methods such as inspection or electrical property detection can not accurately analyze the root of inefficacy, and this just requires that quasiconductor decapsulates, and uses height
Level delamination treatment technology removes the coating (such as silicon layer, oxide layer) on wafer to be measured, prepares semiconductor failure analysis sample, profit
With sophisticated analytical instruments, respectively from the surface of wafer to be measured and cross-section and analysis, to expose the lamination of semiconductor device
The failure conditions of structure.
In preparing semiconductor failure analysis sample, refer to Fig. 1 and Fig. 2, prior art is prepared quasiconductor and loses
Effect analyzes the method for sample: first, it is provided that test chip 10, described test chip 10 is provided with test section (test key)
20；Then, use cutting machine (Automated micro-cleaving, also referred to as SELA) that described test chip 10 is carried out
Cutting, makes facet (tangent plane) expose a part of test section 20, to carry out failure analysis, such as, tests certain in test section 20
The characteristic size of the tangent plane of a little thin layers, or analyze the defect etc. of some thin layer.
In general, described test chip 10, by manually or mechanically obtaining, is to be obtained by wafer season crack.Due to existing
The substrate of some test chips 10 is usually<100>crystal orientation, thus, the orientation of test section 20 is as shown in figure X-direction, therefore
Crystal orientation is that the orientation of the test section 20 of<100>exists 45 degree with the direction (as shown in figure Y-direction) of wafer season crack
Angle.And, described test chip 20 is cut by cutting machine only along the direction of wafer season crack.Such as Fig. 2 institute
Showing, this results in described test section 20 and the angle of test section 20 orientation existence 45 degree that facet exposes.Measure
The characteristic size (CD) in examination district 20, just should can obtain data accurately along the direction vertical with X-direction.If measuring direction not
Being the direction vertical with X-direction, can there is certain deviation in the characteristic size measuring the test section 20 obtained.Moreover, cut
Described test chip 20 is cut by cutting mill platform only along the direction of wafer season crack, therefore easily causes described test
District 20 tangent plane ruptures, and forms coarse tangent plane, is unfavorable for that follow-up shooting is for the picture analyzed.
Summary of the invention
Present invention aim at proposing a kind of method preparing semiconductor failure analysis sample, it is possible to prepare tangent plane vertical
Semiconductor failure analysis sample in test section.
Another object of the present invention is to propose a kind of method preparing semiconductor failure analysis sample, makes for preparing partly to lead
The tangent plane of body failure analysis sample smooths.
To achieve these goals, the present invention proposes a kind of method preparing semiconductor failure analysis sample, including:
Thering is provided test chip, described test chip is provided with test section；
Described test chip is carried out cutting and forms initial sample, and expose described survey at described initial sample one jiao
The facet in examination district；
One jiao that described initial sample exposes described test section facet is cut, and makes facet and described test
The orientation in district is vertical, forms semiconductor failure analysis sample.
Further, described test chip is<100>crystal orientation.
Further, use focused ion bundle that described initial sample exposes one jiao of described test section facet to carry out
Cutting.
Further, one jiao that described initial sample exposes described test section facet is cut, described test
The length range of the facet formed after district is cut is less than 20 μm.
Further, after described test chip being carried out cutting and forms initial sample, also include: to described initial sample
Product expose the diagonal angle of one jiao, described test section and polish.
Further, the diagonal angle using either manually or mechanically mode that described initial sample exposes one jiao, described test section enters
Row polishing.
Further, described initial sample exposes the buffed surface that formed after the diagonal angle of one jiao, described test section is polished
Length range is 3mm ~ 5mm.
Further, described test chip is cuboid.
Further, the length range of described test chip is 20mm ~ 24mm, and width range is 9mm ~ 11mm.
Further, described initial sample is cuboid.
Further, the length range of described initial sample is 5mm ~ 7mm, and width range is 4.5mm ~ 5.5mm.
Further, described initial sample is exposed one jiao of described test section cut after, also include: use
Described initial sample is soaked by chemical substance, thus forms semiconductor failure analysis sample.
Further, described chemical substance is Fluohydric acid. or the mixture for hydrofluoric acid containing.
Compared with prior art, beneficial effects of the present invention major embodiment in: first described test chip is cut
Form initial sample and expose the facet of described test section at described initial sample one jiao, and then to described initial sample
Product expose described test section facet one jiao cuts, and makes facet vertical with the orientation of described test section, from
And can be with the characteristic size of test section described in accurately measure.
Accompanying drawing explanation
Fig. 1 is the plan structure schematic diagram of a test chip in prior art；
Fig. 2 is the plan structure schematic diagram of semiconductor failure analysis sample in prior art；
Fig. 3 is the flow chart that the present invention prepares the method for semiconductor failure analysis sample；
Fig. 4 to Fig. 7 is the plan structure signal of the method preparing semiconductor failure analysis sample in one embodiment of the invention
Figure.
Detailed description of the invention
In order to make it easy to understand, the present invention is conducted further description below in conjunction with specific embodiment and Fig. 3.
During semiconductor failure analysis sample carries out failure analysis, typically have three kinds of analysis methods: 1) focus on from
Son bundle (FIB), 2) transmission electron microscope (TEM), 3) sweep electron microscope (SEM).Wherein, FIB resolution is the lowest
In SEM, the analysis picture taken is fuzzyyer, can not differentiate different thin layer, be not easy to navigate to when target is not or not surface
Target；It is the most loaded down with trivial details that TEM prepares sample, is not easy to tell the thin layer of the identical material that different process is formed；SEM can be
Chemical substance is first used to soak, it is possible to tell different thin layer, it is also possible to tell the identical material of different process formation
Thin layer, the analysis picture also ratio taken is more visible, applied range.The quasiconductor that the present embodiment is preferably prepared for SEM loses
Effect analyzes sample.
Below as a example by the semiconductor failure analysis sample preparing SEM, describe the present invention in detail in conjunction with Fig. 3 to Fig. 7.This reality
Execute example and propose a kind of method preparing semiconductor failure analysis sample, including:
Step S1: providing test chip 100, described test chip 100 is provided with test section 200, as shown in Figure 4；Described survey
Examination chip 100 is<100>crystal orientation, and described test chip 100 is cuboid, and its length range is 20mm ~ 24mm, e.g.
20mm, width range is 9mm ~ 11mm, e.g. 10mm.Described test chip 100, by manually or mechanically obtaining, is by wafer certainly
So split and obtain.
Step S2: described test chip 100 is carried out cutting and forms initial sample 100 ', and in described initial sample 100 '
One jiao of (turning) place expose the facet of described test section 200, in the present embodiment, test section 200 meeting after cutting
Forming two facets, said two facet becomes an angle of 90 degrees (as shown in dotted line circle in Fig. 5)；In the present embodiment, cutting machine
The orientation of the described initial sample 100 ' cut out as shown in Fig. 5 X-direction, its with any one facet direction (such as Fig. 5
Shown in middle Y-direction) in 45 degree of angles；Described initial sample 100 ' can be square, and length range is 5mm ~ 7mm, width model
Enclose for 4.5mm ~ 5.5mm；Described initial sample 100 ' is cuboid, and in the present embodiment, length and width are 5mm.
Step S3: described initial sample 100 ' is exposed one jiao of described test section 200 facet and cuts, make to cut
Face is vertical with the orientation of test section 200 (X-direction), forms semiconductor failure analysis sample 100 ", as shown in Figure 7；?
In the present embodiment, focused ion bundle (FIB) is preferably used described initial sample 100 ' is exposed the cutting of described test section 200
Face is cut, and makes facet direction (as shown in Z-direction in Fig. 7) vertical with the orientation of test section 200 (X-direction), side
Just the characteristic size of described test section 200 is measured；The length L1 scope of the facet formed after described test section 200 is cut is
Less than 20 μm, e.g. 10 μm.Due to be use focused ion bundle described initial sample 100 ' is cut, compared to tradition
Machine cuts, focused ion bundle can be accurately controlled cut point, and be easily controlled depth of cut and dynamics, not result in
Described test section 200 facet ruptures, such that it is able to form smooth facet, follow-up can shoot become apparent from for
The photo analyzed.
Wherein, before performing step S2, it is also preferred that the left described initial sample 100 ' is exposed described test section 200 1
Polish in the diagonal angle at turning, as shown in Figure 6；Due in existing SEM board place semiconductor failure analysis sample 100 " appearance
The size and dimension of device is fixed, and needs described initial sample 100 ' to polish so that it is size diminishes, and is easily fixed on
In SEM board place semiconductor failure analysis sample 100 " container in, facilitate SEM board to fix described semiconductor failure analysis
Sample 100 ", such that it is able to described semiconductor failure analysis sample 100 " taking pictures etc. processes.Wherein it is possible to make by hand
Or the diagonal angle at the turning that described initial sample 100 ' exposes described test section 200 polished by machinery, described initial sample
Length L2 of buffed surface that product 100 ' are formed after being polished in the range of 3mm ~ 5mm, e.g. 4mm.
In the present embodiment, it be also possible to use chemical substance after execution of step S3 to described semiconductor failure analysis sample
100 " soak；Owing to chemical substance has different etching rates to the thin layer of unlike material, unlike material can be made
Thin layer is easily compartmentalized, it is simple to follow-up use SEM is to quasiconductor failure analysis sample 100 " take pictures and CD measurement
Deng；Wherein, described chemical substance for example, Fluohydric acid. or be the mixture of hydrofluoric acid containing.
These are only the preferred embodiments of the present invention, the present invention is not played any restriction effect.Belonging to any
Those skilled in the art, in the range of without departing from technical scheme, to the technical scheme that the invention discloses and
Technology contents makes the variations such as any type of equivalent or amendment, all belongs to the content without departing from technical scheme, still
Within belonging to protection scope of the present invention.
Claims (13)
1. the method preparing semiconductor failure analysis sample, including:
Thering is provided test chip, described test chip is provided with test section；
Described test chip is carried out cutting and forms initial sample, expose described test section at described initial sample one jiao
Two perpendicular facets, and the angle of the perpendicular facet of said two and the orientation of described test section is 45
Degree；
One jiao of described initial sample is cut, forms another facet, another facet described and described test section
Orientation is vertical, forms semiconductor failure analysis sample.
The method preparing semiconductor failure analysis sample the most as claimed in claim 1, it is characterised in that: described test chip is
<100>crystal orientation.
The method preparing semiconductor failure analysis sample the most as claimed in claim 2, it is characterised in that: use focused ion bundle
One jiao that described initial sample exposes described test section facet is cut.
The method preparing semiconductor failure analysis sample the most as claimed in claim 3, it is characterised in that: to described initial sample
One jiao that exposes described test section facet is cut, the length range of the facet formed after described test section is cut
For less than 20 μm.
The method preparing semiconductor failure analysis sample the most as claimed in claim 1, it is characterised in that: to described test core
After sheet carries out cutting formation initial sample, also include: the diagonal angle that described initial sample exposes one jiao, described test section enters
Row polishing.
The method preparing semiconductor failure analysis sample the most as claimed in claim 5, it is characterised in that: use either manually or mechanically
Mode exposes the diagonal angle of one jiao, described test section and polishes described initial sample.
The method preparing semiconductor failure analysis sample the most as claimed in claim 6, it is characterised in that: described initial sample is sudden and violent
The length range exposing the buffed surface formed after the diagonal angle of one jiao, described test section is polished is 3mm～5mm.
The method preparing semiconductor failure analysis sample the most as claimed in claim 1, it is characterised in that: described test chip is
Cuboid.
The method preparing semiconductor failure analysis sample the most as claimed in claim 8, it is characterised in that: described test chip
Length range is 20mm～24mm, and width range is 9mm～11mm.
The method preparing semiconductor failure analysis sample the most as claimed in claim 1, it is characterised in that: described initial sample
For cuboid.
11. methods preparing semiconductor failure analysis sample as claimed in claim 10, it is characterised in that: described initial sample
Length range be 5mm～7mm, width range is 4.5mm～5.5mm.
12. methods preparing semiconductor failure analysis sample as claimed in claim 1, it is characterised in that: to described initial sample
Product expose one jiao of described test section cut after, also include: use chemical substance that described initial sample is soaked
Bubble, thus form semiconductor failure analysis sample.
13. methods preparing semiconductor failure analysis sample as claimed in claim 12, it is characterised in that: described chemical substance
For Fluohydric acid. or be the mixture of hydrofluoric acid containing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210526393.0A CN103871917B (en) | 2012-12-07 | 2012-12-07 | The method preparing semiconductor failure analysis sample |
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| CN201210526393.0A CN103871917B (en) | 2012-12-07 | 2012-12-07 | The method preparing semiconductor failure analysis sample |
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| CN103871917A CN103871917A (en) | 2014-06-18 |
| CN103871917B true CN103871917B (en) | 2016-12-28 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104625947B (en) * | 2015-01-30 | 2018-01-26 | 武汉新芯集成电路制造有限公司 | Chip fixture apparatus and the method for preparing failure analysis sample |
| CN108827734A (en) * | 2018-08-01 | 2018-11-16 | 南京中电熊猫平板显示科技有限公司 | A kind of sample preparation apparatus and working method |
| CN109883365B (en) * | 2019-01-11 | 2021-04-02 | 深圳赛意法微电子有限公司 | Method for measuring thickness of crystal grain layer and method for judging abnormality of crystal grain layer |
| CN110031277A (en) * | 2019-04-29 | 2019-07-19 | 武汉光迅科技股份有限公司 | A kind of chip sample production method for failure analysis |
| CN115274489B (en) * | 2022-09-29 | 2022-12-09 | 合肥晶合集成电路股份有限公司 | Failure analysis method and system for chip |
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| CN1769963A (en) * | 2004-11-03 | 2006-05-10 | 均豪精密工业股份有限公司 | Defect detection apparatus and method after panel breaking |
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