CN104198241B - A kind of method for preparing TEM sample - Google Patents
A kind of method for preparing TEM sample Download PDFInfo
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- CN104198241B CN104198241B CN201410408599.2A CN201410408599A CN104198241B CN 104198241 B CN104198241 B CN 104198241B CN 201410408599 A CN201410408599 A CN 201410408599A CN 104198241 B CN104198241 B CN 104198241B
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000004458 analytical method Methods 0.000 claims abstract description 27
- 238000002360 preparation method Methods 0.000 claims abstract description 21
- 238000005498 polishing Methods 0.000 claims abstract description 16
- 238000005516 engineering process Methods 0.000 claims abstract description 10
- 239000000853 adhesive Substances 0.000 claims abstract description 6
- 230000001070 adhesive effect Effects 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 239000011241 protective layer Substances 0.000 claims description 17
- 230000000694 effects Effects 0.000 claims description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical group [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- 229920000297 Rayon Polymers 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000010276 construction Methods 0.000 description 4
- 238000010884 ion-beam technique Methods 0.000 description 4
- 239000010410 layer Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000008280 blood Substances 0.000 description 2
- 210000004369 blood Anatomy 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
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Abstract
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of method for preparing TEM sample, by behind the position for obtaining the failure analysis reference point of failpoint position and non-failed chip of chip failing, chip failing edge is polished to into the vicinity of failpoint perpendicular to the direction of selected side, and non-failed chip edge is polished to into the vicinity of failure analysis reference point perpendicular to the direction of the selected side, the front of chip failing is formed into one together with the front adhesive of non-failed chip afterwards and treats geodesic structure, and the polishing for treating geodesic structure faces up be put into FIB boards and carry out the preparation technology of TEM sample, such that it is able to quickly prepare TEM sample, and most suitable thickness can be found when high-resolution pictures are shot, guarantee the quality of high-resolution pictures.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of method for preparing TEM sample.
Background technology
At present, transmission electron microscope (TEM) is the important tool of electron micrology, and TEM can be used for detection composition half
The pattern of the film of conductor device, size and feature etc..TEM sample is put into after TEM sight chambers, the main operational principle of TEM
For：There is the phenomenons such as scattering, absorption, interference and diffraction in high-power electron beam so that formed in imaging plane and served as a contrast when penetrating TEM sample
Degree, so as to form the image of TEM sample, is subsequently observed, measured and is analyzed to the image of the TEM sample again.
In prior art, focused ion beam (FIB) board can complete the system of TEM sample in the regional area of full wafer chip
It is standby, during TEM sample is prepared using FIB, as depicted in figs. 1 and 2, wherein, 1 represents sample area to be prepared, generally
All be the plating up-protective layer 2 above the sample area to be prepared of chip, then hollow place vertically slightly dug in 2 both sides of protective layer, formed
Mark hole 3, it is progressively thinning further along 2 two sides of protective layer afterwards, until sample reaches certain thinness.For general only needs to
Take pictures transmission electron microscope (TEM) sample of individual layer failure structure, whole preparation flows only need can just to make for 40 minutes one it is perfect
Sample, more perfect TEM pictures can be photographed.But for the sandwich construction and thickness reaches more than 3 microns of taking pictures in need
Prepared by the super large height samples of structure, it is necessary to which the hollow place for slightly digging larger depth from chip surface forms mark hole, subtracting below
Thin to be less than 2 μm, because prepared by cut-away depth ratio, general TEM sample is more one times, and whole process will be very painstaking
And it is time-consuming.And the sample prepared often due to the lack of uniformity of ion beam and it is not perfect, this is people in the art
What member was hated the sight of.
The content of the invention
For above-mentioned problem, the present invention discloses a kind of method for preparing TEM sample.
A kind of method for preparing TEM sample, wherein, comprise the steps：
The chip failing and non-failed chip of semiconductor device structure are provided, in the chip failing, failure device is provided with
Part structure, and the chip failing and the non-failed chip are respectively provided with a front and relative positive some sides；
It is thinning along carrying out to the chip failing perpendicular to the positive direction, and stop at apart from the ineffective part
Structure is at the position of the first distance, to obtain position of the failpoint in the ineffective part structure on the chip failing
Put；
A failure analysis reference point on the non-failed chip is set according to the position of the failpoint, continue along perpendicular to
The positive direction non-failed chip is carried out it is thinning, and stop at apart from the failure analysis reference point be located device
Part structure is at the position of first distance；
One side is selected according to position of the failpoint on the chip failing, and along perpendicular to the selected side
Direction is polished to the chip failing, and is stopped at the position apart from the position of the failpoint for second distance, with
Form to-be-measured cell；
Along being polished to the non-failed chip with chip failing polishing direction identical direction, with formation and institute
State the reference unit that to-be-measured cell has identical graphic structure；
The thinning face of the to-be-measured cell is bonded on the thinning face of the reference unit, geodesic structure is treated to form one,
And the polishing for treating geodesic structure faces up be put into FIB boards, to carry out the preparation technology of TEM sample；
Wherein, it is described treat failpoint described in geodesic structure and the failure analysis reference point with the chip failing with it is described
The adhesive surface of non-failed chip is symmetrical with reference to being mirrored.
The method of above-mentioned preparation TEM sample, wherein, first distance is 50-150nm.
The method of above-mentioned preparation TEM sample, wherein, the second distance is 1-2 μm.
The method of above-mentioned preparation TEM sample, wherein, using grinder along the direction perpendicular to the selected side to described
Chip failing is polished, and the non-failed chip is thrown along direction identical direction is polished with the chip failing
Light.
The method of above-mentioned preparation TEM sample, wherein, the thickness of the chip failing and the non-failed chip is all higher than
3μm。
The method of above-mentioned preparation TEM sample, wherein, the thinning face of the to-be-measured cell is bonded to using viscose glue described
On the thinning face of reference unit.
The method of above-mentioned preparation TEM sample, wherein, the preparation technology of the TEM sample includes：
Protective layer is being formed on the burnishing surface above the failpoint and the failure analysis reference point；
Mark hole is formed in the both sides of the protective layer；
Continue described to treat that geodesic structure, to predetermined thickness, forms the TEM sample along the protective layer both sides are gradually thinning.
The method of above-mentioned preparation TEM sample, wherein, the predetermined thickness is 50-100nm.
The method of above-mentioned preparation TEM sample, wherein, the depth in the mark hole is 1-2 μm.
The method of above-mentioned preparation TEM sample, wherein, the material of the protective layer is platinum.
Foregoing invention has the advantage that or beneficial effect：
The method for preparing TEM sample disclosed by the invention, may be applicable to take pictures sandwich construction and thickness reach 3 μm with
On structure, by obtain chip failing failpoint position and non-failed chip failure analysis reference point position
Afterwards, chip failing is polished to into the vicinity (about 1.5 μm) of failpoint along perpendicular to the direction of selected side, and by non-failed chip
Along the vicinity (about 1.5 μm) of failure analysis reference point is polished to perpendicular to the direction of the selected side, afterwards by chip failing
Front forms one together with the front adhesive of non-failed chip and treats geodesic structure, and the polishing for treating geodesic structure is faced up is put into
FIB boards carry out the preparation technology of TEM sample, as the depth of failpoint or required structure after the anglec of rotation is up to 2
Micron, such that it is able to quickly prepare TEM sample (time is equal to conventional sample).
Additionally, importantly, as the deficiency of the uniformity of ion beam can be such that the TEM sample prepared has from top to bottom
One makes each Rotating fields from thin to thick by this point to thicker progressive after the anglec of rotation just from most thin, such that it is able to
An optimal thickness can be found when shooting high-resolution pictures, and then board, time and human cost can saved
Outside, it is ensured that the quality of high-resolution pictures, and it is corresponding to observe the failpoint and non-failed chip of chip failing simultaneously
Failure analysis reference point to be contrasted, so as to further ensure the accuracy of failure analysis.
It is concrete to illustrate
By reading the detailed description made to non-limiting example with reference to the following drawings, the present invention and its feature, outward
Shape and advantage will become more apparent.In whole accompanying drawings, identical mark indicates identical part.Not can according to than
Example draws accompanying drawing, it is preferred that emphasis is illustrate the purport of the present invention.
Fig. 1 is the structural representation of chip failing or non-failed chip；
Fig. 2 is the structural representation that TEM sample is prepared using conventional art；
Fig. 3 is along the schematic diagram being polished perpendicular to the direction of selected side by chip failing or non-failed chip；
Fig. 4 is to form the structural representation in mark hole in the both sides for treating geodesic structure up-protective layer；
Fig. 5 is the structural representation of the TEM sample prepared in the embodiment of the present invention；
Fig. 6 is the schematic flow sheet of the method for preparation TEM sample in the embodiment of the present invention.
Specific embodiment
The present invention is further illustrated with specific embodiment below in conjunction with the accompanying drawings, but not as the limit of the present invention
It is fixed.
For needing to take pictures sandwich construction and thickness reaches more than 3 μm and treats geodesic structure, from treating that knife is thick under geodesic structure front
Hollow place is dug, mark hole is formed, and is proceeded thinning, can cause to take very much as structural thickness to be measured reaches more than 3 μm, because
This is quickly ground to emphatically to be close to after failpoint lower knife and open from side and is cut the invention provides a kind of method for preparing TEM sample
Sample, as failpoint or required structure are by 2 μm of the most cut-aways of depth after the anglec of rotation, so preparing sample using the invention
The time of product can be equal to conventional preparation time, so as to greatly save board, time and human cost, additionally, using this
The method of invention, can also observe the corresponding failure analysis reference point of failpoint and non-failed chip of chip failing simultaneously to enter
Row contrast, so as to further ensure the accuracy of failure analysis.
As shown in fig. 6, present embodiments providing a kind of method for preparing TEM sample, following steps are specifically included：
Step one, there is provided the chip failing and non-failed chip of semiconductor device structure, the i.e. chip failing and non-mistake
Effect chip has identical structure and scale topography, and which differs only in, and is provided with ineffective part structure, i.e., in the chip failing
There is failpoint in the chip failing, rather than chip failing is the good chip that there is no failpoint, and chip failing and non-mistake
Effect chip is respectively provided with a front and relative positive some sides.In an embodiment of the present invention, the chip failing and non-mistake
The thickness of effect chip is all higher than 3 μm, as failpoint is can be located on any structure in chip failing semiconductor-on-insulator device architecture,
Therefore do not indicate in figure, therefore the structure of chip failing and non-failed chip can be the structure shown in Fig. 1.
Step 2, it is thinning along carrying out to chip failing perpendicular to positive direction, and stop at apart from ineffective part structure
At position for the first distance, to obtain position of the failpoint in ineffective part structure on chip failing；Preferably, this
One distance can be set according to follow-up observation requirementses, i.e., can observe that failpoint is defined, for example, if failpoint is located at grid oxygen
Change on layer, i.e., gate oxide is the device architecture of failure, then the chip failing is ground to from front (or along perpendicular to positive
Direction is thinned to) superstructure of gate oxide (for gate oxide, its superstructure is grid) stops, then this first
Thickness of the distance for grid, in an embodiment of the present invention, first distance is 50-150nm (such as 50nm, 70nm, 100nm
Or 150nm etc.).
Step 3, according to the position of failpoint set non-failed chip on a failure analysis reference point, continue along perpendicular to
The positive direction carries out thinning to non-failed chip, and to stop at the device architecture being located apart from failure analysis reference point be the
At the position of one distance.If failpoint is located on gate oxide in step 2, the failure analysis reference point is located at non-failed
On chip on the gate oxide of same position, then the non-failed chip is ground to from front (or along perpendicular to positive direction
It is thinned to) superstructure of gate oxide (for gate oxide, its superstructure is grid) stops, then first distance
For the thickness of grid.
Step 4, the position according to failpoint on chip failing select one side, and along perpendicular to the selected side
Direction is polished to chip failing, and is stopped at the position apart from the position of failpoint for second distance, to be measured to be formed
Unit；In an embodiment of the present invention, if failpoint is located on gate oxide, the concrete of gate oxide is located at according to failpoint
Position selects to polish the chip failing from which side, and to be easy to subsequently prepare TEM sample, in an embodiment of the present invention, this
Two distances are 1-2 μm (such as 1 μm, 1.2 μm, 1.5 μm or 2 μm etc.), will failpoint chip along perpendicular to the selected side
Direction is polished to the vicinity (about apart from failpoint 1.5 μm) of failpoint, by chip failing along the direction perpendicular to selected side
The structure being polished is as shown in Figure 3.
Step 5, is continued along being polished to non-failed chip with chip failing polishing direction identical direction, to be formed
There is the reference unit of identical graphic structure with to-be-measured cell；I.e. along perpendicular to chip failing in select side respective side
Direction is polished to the non-failed chip, and stops at the vicinity of failure analysis reference point (about apart from failure analysis reference
1.5 μm of point), to form reference unit；Specifically, non-failed chip edge is carried out with chip failing polishing direction identical direction
The structure of polishing can also be with reference to shown in Fig. 3.
Further, chip failing edge is polished to apart from failpoint perpendicular to the direction of the selected side using grinder
Position be 1-2 μm locate, and by non-failed chip from edge and chip failing polishing direction identical direction be polished to distance fail
The position of analysis reference point is at 1-2 μm.
The thinning face (i.e. the front of the to-be-measured cell) of to-be-measured cell is bonded to the thinning face of reference unit by step 6
On (i.e. the front of the reference unit), geodesic structure is treated to form one, and the polishing for treating geodesic structure is faced up be put into FIB boards,
To carry out the preparation technology of TEM sample, specifically, will be through front (the i.e. step 2 of the chip failing after step 4 polishing
The front that middle chip failing is thinned) and non-failed chip after step 5 polishing front (i.e. non-failed in step 3
The front that chip is thinned) it is adhesively-bonded together to form one and treats geodesic structure, and treat failpoint and failure analysis reference point in geodesic structure
It is symmetrical with reference to being mirrored with chip failing and the adhesive surface of non-failed chip, forms structure as shown in Figure 4, and will treat
The polishing of geodesic structure faces up (non-failed chip in the selected side of i.e. polished in step 4 chip failing and step 5
Selected side faces up) FIB boards are put into, carry out the preparation technology of TEM sample.
Specifically, with reference to as shown in figure 4, the thinning face of to-be-measured cell 200 is bonded to reference unit 100 using viscose glue 4
Thinning face on, and being put into after FIB boards in will face up after the polishing of geodesic structure, referring to positioned at failpoint and failure analysis
Protective layer 2 is formed on the burnishing surface of point top, it is preferred that by I beam (focused ion beam) and E beam (focusing electron beam)
Layer of metal is plated as protective layer 2 in the upper surface of the burnishing surface；After protective layer 2 both sides formed mark hole 3；Continue edge
Gradually thinning this treats that geodesic structure, to predetermined thickness, forms TEM sample, structure such as Fig. 5 institutes of the TEM sample of formation for protective layer both sides
Show.
Preferably, above-mentioned predetermined thickness is 50-100nm (such as 50nm, 60nm, 80nm or 100nm etc.).
Preferably, the depth in above-mentioned mark hole is 1-2 μm.
Preferably, the material of above-mentioned protective layer is platinum.
To sum up, the method for preparing TEM sample disclosed by the invention, may be applicable to take pictures sandwich construction and thickness reaches
More than 3 μm of structure, by the failure analysis reference point in the failpoint position of acquisition chip failing and non-failed chip
Behind position, chip failing is polished to into the vicinity (about 1.5 μm) of failpoint along perpendicular to the direction of selected side, and by non-failed
Along the vicinity (about 1.5 μm) of failure analysis reference point is polished to perpendicular to the direction of the selected side, will fail chip core afterwards
The front of piece forms one together with the front adhesive of non-failed chip and treats geodesic structure, and the polishing for treating geodesic structure is faced up puts
Entering FIB boards carries out the preparation technology of TEM sample, as the depth of failpoint or required structure after the anglec of rotation is up to
2 microns, such that it is able to quickly prepare TEM sample (time is equal to conventional sample).And as high-resolution can be being shot
An optimal thickness can be found during rate picture, and then board can saved, outside time and human cost, it is ensured that high
The quality of resolution chart, additionally, failpoint and non-failed chip that the present invention can observe chip failing are lost accordingly simultaneously
Effect analyzes reference point accordingly to be contrasted, so as to further ensure the accuracy of failure analysis.
It should be appreciated by those skilled in the art that those skilled in the art are can be with reference to prior art and above-described embodiment
The change case is realized, be will not be described here.Such change case has no effect on the flesh and blood of the present invention, and here is not superfluous
State.
Above presently preferred embodiments of the present invention is described.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure that do not describe in detail to the greatest extent are construed as giving reality with the common mode in this area
Apply；Any those of ordinary skill in the art, under without departing from technical solution of the present invention ambit, all using the disclosure above
Methods and techniques content make many possible variations and modification to technical solution of the present invention, or be revised as equivalent variations etc.
Effect embodiment, this has no effect on the flesh and blood of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation
The technical spirit of the present invention still falls within the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification
In the range of technical scheme protection.
Claims (8)
1. a kind of method for preparing TEM sample, it is characterised in that comprise the steps：
The chip failing and non-failed chip of semiconductor device structure are provided, ineffective part knot in the chip failing, is provided with
Structure, and the chip failing and the non-failed chip are respectively provided with a front and relative positive some sides；
It is thinning along carrying out to the chip failing perpendicular to the positive direction, and stop at apart from the ineffective part structure
At position for the first distance, to obtain position of the failpoint in the ineffective part structure on the chip failing, its
Described in first distance be 50-150nm；
A failure analysis reference point on the non-failed chip is set according to the position of the failpoint, is continued along perpendicular to described
Positive direction the non-failed chip is carried out it is thinning, and stop at apart from the failure analysis reference point be located device junction
Structure is at the position of first distance；
One side is selected according to position of the failpoint on the chip failing, and along the direction perpendicular to the selected side
The chip failing is polished, and is stopped at the position apart from the position of the failpoint for second distance, to be formed
To-be-measured cell, wherein the second distance is 1-2 μm；
Along being polished to the non-failed chip with chip failing polishing direction identical direction, treated with described with being formed
Survey the reference unit that unit has identical graphic structure；
The thinning face of the to-be-measured cell is bonded on the thinning face of the reference unit, geodesic structure is treated to form one, and will
The polishing for treating geodesic structure faces up and is put into FIB boards, to carry out the preparation technology of TEM sample；
Wherein, it is described to treat failpoint described in geodesic structure with the failure analysis reference point with the chip failing and the non-mistake
The adhesive surface of effect chip is symmetrical with reference to being mirrored.
2. the method for preparing TEM sample as claimed in claim 1, it is characterised in that using grinder along selected perpendicular to this
The direction of side is polished to the chip failing, and polishes direction identical direction to described non-along with the chip failing
Chip failing is polished.
3. the method for preparing TEM sample as claimed in claim 1, it is characterised in that the chip failing and the non-failed
The thickness of chip is all higher than 3 μm.
4. the as claimed in claim 1 method for preparing TEM sample, it is characterised in that using viscose glue by the to-be-measured cell
Thinning face is bonded on the thinning face of the reference unit.
5. the method for preparing TEM sample as claimed in claim 1, it is characterised in that the preparation technology bag of the TEM sample
Include：
Protective layer is being formed on the burnishing surface above the failpoint and the failure analysis reference point；
Mark hole is formed in the both sides of the protective layer；
Continue described to treat that geodesic structure, to predetermined thickness, forms the TEM sample along the protective layer both sides are gradually thinning.
6. the method for preparing TEM sample as claimed in claim 5, it is characterised in that the predetermined thickness is 50-100nm.
7. the method for preparing TEM sample as claimed in claim 5, it is characterised in that the depth in the mark hole is 1-2 μm.
8. the method for preparing TEM sample as claimed in claim 5, it is characterised in that the material of the protective layer is platinum.
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| CN201410408599.2A CN104198241B (en) | 2014-08-19 | 2014-08-19 | A kind of method for preparing TEM sample |
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| CN201410408599.2A CN104198241B (en) | 2014-08-19 | 2014-08-19 | A kind of method for preparing TEM sample |
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| CN105865861B (en) * | 2015-01-23 | 2018-09-18 | 中芯国际集成电路制造(上海)有限公司 | A method of preparing failure analysis sample |
| CN106206344B (en) * | 2015-05-08 | 2019-02-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of method of the defect of the determining contact plug being connected in memory element |
| CN105092330B (en) * | 2015-08-12 | 2017-12-22 | 上海华力微电子有限公司 | A kind of TEM sample preparation method |
| CN112201586A (en) * | 2020-09-16 | 2021-01-08 | 上海华力集成电路制造有限公司 | Wafer defect source online positioning method and positioning system thereof |
| CN112345336B (en) * | 2020-10-12 | 2023-02-03 | 上海华力集成电路制造有限公司 | Method for polishing back of ultra-small sample |
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| JP2586684B2 (en) * | 1990-04-03 | 1997-03-05 | 日本電気株式会社 | Sample preparation method for transmission electron microscope |
| TW556256B (en) * | 2002-07-08 | 2003-10-01 | Chartered Semicoductor Mfg Ltd | Method for a plan-view transmission electron microscopy sample preparation technique for via and contact characterization |
| CN103913358B (en) * | 2014-04-10 | 2017-10-27 | 武汉新芯集成电路制造有限公司 | The preparation method and failure analysis method of TEM sample |
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