CN111398325B - TEM sample preparation method - Google Patents

TEM sample preparation method Download PDF

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Publication number
CN111398325B
CN111398325B CN201910003403.4A CN201910003403A CN111398325B CN 111398325 B CN111398325 B CN 111398325B CN 201910003403 A CN201910003403 A CN 201910003403A CN 111398325 B CN111398325 B CN 111398325B
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tem sample
defect
substrate
semiconductor substrate
plane
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CN111398325A (en
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李晓丽
王金成
王佳龙
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N1/00—Sampling; Preparing specimens for investigation
    • G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
    • G01N23/22—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material
    • G01N23/2202—Preparing specimens therefor

Abstract

The application relates to a TEM sample preparation method, which comprises the following steps: determining a target position with defects on the semiconductor substrate, thinning the semiconductor substrate from the back of the semiconductor substrate to prepare a planar TEM sample, wherein the target position is positioned in the planar TEM sample; adhering the back surface of the plane TEM sample on the conductive pad by using adhesive, wherein the thickness of the adhesive is less than or equal to 50 μm; and determining the plane appearance and position of the defect, and cutting the defect position by adopting a focused ion beam to be vertical to the plane TEM sample to prepare a section TEM sample, wherein the defect is positioned on the section of the section TEM sample. The preparation method is used for preparing the section TEM sample, and can acquire defect information in the thickness direction of the semiconductor substrate, such as depth information of the defect, so that a process causing the defect is deduced, the process is improved, and the product yield is improved.

Description

TEM sample preparation method
Technical Field
The invention relates to the field of semiconductors, in particular to a TEM sample preparation method.
Background
In a semiconductor device manufacturing process, a semiconductor substrate is generally subjected to a process such as well implantation, ion implantation, annealing, or the like, and thus, the lattice arrangement in the semiconductor substrate is likely to be disordered, thereby generating defects. Meanwhile, with the size of the semiconductor device becoming smaller and smaller, the integration level of the semiconductor device becomes higher and higher, and the defects have greater and greater influence on the yield and reliability of the device. Therefore, in the failure analysis of the semiconductor device, the position of the defect of the semiconductor substrate is found, the related information of the defect is obtained, and the procedure causing the defect can be reversely deduced, so that the related procedure can be improved, the subsequent type defect is avoided, and the product yield and the reliability of the device are improved. Currently, there are two methods to obtain defect information: one is to perform chemical etching on a semiconductor substrate and observe the semiconductor substrate by using a Scanning Electron Microscope (SEM), so as to determine whether a defect exists on the semiconductor substrate and an approximate position of the defect, but the specific position and shape of the defect cannot be known; the other method is to prepare a plane TEM (Transmission Electron Microscope) sample and observe the sample by using the TEM, so that the plane position and the plane morphology of the defect can be obtained, but the defect information in the thickness direction of the semiconductor substrate, such as the depth information of the defect, cannot be obtained, and thus the failure analysis of the semiconductor device is limited.
Disclosure of Invention
In view of this, it is necessary to provide a TEM sample preparation method for a case where defect information in the thickness direction of the semiconductor substrate cannot be obtained.
A TEM sample preparation method comprising:
determining a target position with defects on a semiconductor substrate and thinning the semiconductor substrate from the back of the semiconductor substrate to prepare a planar TEM sample, wherein the target position is located in the planar TEM sample;
adhering the back surface of the plane TEM sample to a conductive pad by using adhesive glue, wherein the thickness of the adhesive glue is less than or equal to 50 micrometers; and
determining the appearance and the plane position of the defect, and cutting the defect at the plane position of the defect by adopting a focused ion beam to be vertical to the plane TEM sample to prepare a section TEM sample, wherein the defect is positioned on the section of the section TEM sample.
The TEM sample preparation method comprises the steps of firstly preparing a plane TEM sample, then cutting a section TEM sample from the plane TEM sample by using FIB (Focused Ion Beam), and enabling the defect to be located on the section of the section TEM sample, wherein the section with the defect is a vertical section. The main purpose of preparing the plane TEM sample is to scan the plane TEM sample by using an FIB machine before cutting by using the FIB machine, and generate a defect image by receiving secondary electron and secondary ion signals, so as to obtain the plane appearance and position of a defect in the plane TEM sample. And after the plane morphology and the position information of the defect are obtained, the FIB machine vertically cuts the plane TEM sample at the defect position, so that a section TEM sample with a defect section is formed. Since the size of the plane TEM sample is small, it is not convenient to directly cut the plane TEM, so the plane TEM sample needs to be fixed on the conductive pad by the adhesive. In the application, the thickness of the adhesive is controlled to be not more than 50 μm, so that even if the adhesive is filled between the conductive gasket and the plane TEM, the conductivity of the conductive gasket is basically not influenced due to the fact that the adhesive is thin, the generation rate of secondary electrons and secondary ions is not influenced, namely the quality of an image is not influenced, and the FIB can accurately acquire the appearance and the plane position of a defect. The semiconductor substrate defect section TEM sample prepared by the method has a defect section, and the section of the semiconductor substrate defect section TEM sample is observed by using a TEM, so that the information of the defect in the thickness direction of the semiconductor substrate, such as the section morphology of the defect, the depth of the defect in the semiconductor substrate and the like, can be acquired, and an analysis basis is provided for failure analysis of a semiconductor device.
In one embodiment, after the step of preparing the planar TEM sample and before the step of adhering the back surface of the planar TEM sample to the conductive pad with the adhesive, the method further comprises:
and observing the plane TEM sample, judging whether the defect exists in the plane TEM sample, and if so, executing the step of adhering the back surface of the plane TEM sample on the conductive gasket by using the adhesive.
In one embodiment, the conductive pad is a silicon wafer.
In one embodiment, the adhesive glue is a two-component epoxy adhesive.
In one embodiment, the thickness of the adhesive glue ranges from 10 μm to 50 μm.
In one embodiment, after the preparing the cross-section TEM sample, further comprises:
the cross section of the cross section TEM sample is observed and the depth of the defect is measured.
In one embodiment, the thickness of the planar TEM sample is less than or equal to
Figure GDA0003318122770000031
In one embodiment, the step of determining a defect region on a semiconductor substrate and thinning the semiconductor substrate from a back side of the semiconductor substrate to obtain a planar TEM sample specifically includes:
marking a target position with a defect on the front surface of the semiconductor substrate;
cutting the semiconductor substrate to form a substrate to be tested, and pasting the front surface of the substrate to be tested on a glass slide, wherein the target position is located at the center of the substrate to be tested;
grinding the back surface of the substrate to be detected, judging whether the substrate to be detected is ground to a target thickness, if so, stopping grinding, and grinding the substrate to be detected to the target thickness to form the plane TEM sample;
adhering a metal ring to the back of the plane TEM sample, and cutting the plane TEM sample along the outer side of the metal ring to cut off the plane TEM sample on the outer side of the metal ring, wherein the target position is located at the central position of the metal ring; and
and separating the plane TEM sample from the glass slide to obtain the plane TEM sample adhered to the metal ring.
In one embodiment, before the step of adhering the front surface of the substrate to be tested on the glass slide, the method further includes:
and soaking the substrate to be tested in hydrofluoric acid to remove the process layer on the front surface of the substrate to be tested and expose the front surface of the semiconductor substrate.
In one embodiment, the step of grinding the back surface of the substrate to be tested specifically includes:
and grinding the back of the substrate to be detected by using 320-mesh, 600-mesh, 800-mesh and 1200-mesh sandpaper in sequence, and polishing the back of the substrate to be detected by using polishing flannelette.
Drawings
FIG. 1 is a flow chart of steps in a TEM sample preparation method in an embodiment of the present application;
FIGS. 2a to 2e are schematic structural diagrams corresponding to respective steps of preparing a planar TEM sample according to an example of the present application;
FIG. 3a is a top view of a planar TEM sample after being bonded to a conductive pad in an embodiment of the present application;
FIG. 3b is a side cross-sectional view of a planar TEM sample after being bonded to a conductive pad in an embodiment of the present application;
FIG. 4 is a schematic structural diagram of a cross-sectional TEM sample in an embodiment of the present application;
FIG. 5 is a scanning electron micrograph of a front side of a planar TEM sample according to an embodiment of the present application;
FIG. 6 is a scanning electron micrograph cut from the plane TEM sample of FIG. 5 to form a cross-section of the cross-sectional TEM sample.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1, the TEM sample preparation method includes:
step S100: and determining a target position with defects on the semiconductor substrate, thinning the semiconductor substrate from the back side of the semiconductor substrate to prepare a planar TEM sample, wherein the target position is positioned in the planar TEM sample.
After a series of processes such as well implantation and annealing are performed in the semiconductor substrate, the internal lattice arrangement of the semiconductor substrate is changed, thereby generating defects in the semiconductor substrate. As shown in fig. 2a, the longitudinal direction of the semiconductor substrate 100 is defined as an X-axis, the width direction of the semiconductor substrate 100 is defined as a Y-axis, and the thickness direction of the semiconductor substrate 100 is defined as a Z-axis. In the present application, a target position 110 with a defect on a semiconductor substrate 100 is determined, the target position 110 is a two-dimensional coordinate in a two-dimensional plane formed by an X-axis and a Y-axis, that is, the target position 110 can be located only in the two-dimensional plane formed by the X-axis and the Y-axis, and the target position 110 does not include a Z-axis coordinate of the defect. Since only planar image information can be acquired when viewed by the scanner, the target position 110 is actually a projected position of the defect on the observation surface of the semiconductor substrate 100.
The semiconductor substrate 100 has a positive electrodeA front surface 100A and a back surface 100B, wherein defects are easily caused in the semiconductor substrate 100 after the semiconductor substrate 100 is subjected to the above-described process from the front surface 100A of the semiconductor substrate 100, and therefore, the defects are closer to the front surface 100A of the semiconductor substrate 100. After the target position 110 having the defect is determined, the semiconductor substrate 100 is thinned from the back surface 100B of the semiconductor substrate 100, and a planar TEM sample is prepared. In some embodiments, the semiconductor substrate 100 is gradually reduced in size during the thinning of the semiconductor substrate 100, but the semiconductor substrate 100 at the target location 110 cannot be removed, i.e., the target location 110 needs to be included in the final planar TEM sample. It should be noted that the thickness of the planar TEM sample in the Z-axis direction after thinning the semiconductor substrate 100 satisfies the TEM observation thickness, and in this embodiment, the thickness of the planar TEM sample is less than or equal to
Figure GDA0003318122770000061
And the smaller its thickness, the better the quality of the image obtained, in one embodiment the thickness of the planar TEM sample is less than or equal to
Figure GDA0003318122770000062
In an embodiment, step S100 may specifically include:
step S110: and marking a target position with a defect on the front surface of the semiconductor substrate.
In one embodiment, the target location 110 may be determined by means of a numerical address or spot for spot samples, and the approximate location of the defect in the substrate may be observed by SEM for non-spot samples and used as the target location 110. After the target location 110 is determined, the semiconductor substrate 100 may be marked at the target location 110 by a laser or FIB to facilitate identification of the target location 110 in subsequent processes. In one embodiment, the mark may be a cross mark.
Step S120: the method comprises the steps of cutting a semiconductor substrate to form a substrate to be tested, adhering the front surface of the substrate to be tested on a glass slide, and positioning a target position at the center of the substrate to be tested.
In general, the semiconductor substrate 100 directly obtained is large in size, and the size of the defect in the semiconductor substrate 100 is small, so that the entire semiconductor substrate 100 does not need to be used for analyzing the defect. In this embodiment, as shown in fig. 2b, the semiconductor substrate 100 is cut around the defect to obtain the substrate 120 to be tested including the defect region, that is, the mark in step S110 is located at the center of the substrate 120 to be tested, and then the front surface of the substrate 120 to be tested is attached to the glass slide 200, wherein the front surface of the substrate 120 to be tested is the front surface 100A of the semiconductor substrate 100. In one embodiment, the substrate 120 to be tested is square, with dimensions of length by width of about 1cm by 1 cm. In one embodiment, the slide 200 may also be square, and the slide 200 may have dimensions slightly larger than the substrate 120 to be tested, and may have dimensions of about 1.2cm × 1.2cm in length × width. In an embodiment, the front surface of the substrate 120 to be tested is adhered to the glass slide 200 by paraffin, and on the premise that the front surface and the back surface are firmly adhered, the thinner the paraffin is, the better the paraffin is, and bubbles need to be prevented from occurring between the substrate 120 to be tested and the glass slide 200.
Since it is usually necessary to obtain defect information of the semiconductor substrate 100 when performing failure analysis of a semiconductor device, process layers, such as dielectric layers, metal layers, etc., are usually formed on the front surface 100A of the semiconductor substrate 100, and therefore, the process layers on the front surface of the semiconductor substrate 100 need to be removed before the front surface of the substrate 120 to be tested is attached to the glass slide 200. In one embodiment, before dicing the semiconductor substrate, the semiconductor substrate 100 with the process layer grown on the front surface 100A is soaked in hydrofluoric acid for about 10 minutes to remove the process layer on the front surface of the semiconductor substrate 100 and expose the front surface 100A of the semiconductor substrate 100. In another embodiment, after the semiconductor substrate is cut, the substrate 130 to be tested is soaked in hydrofluoric acid for about 10 minutes to remove the process layer on the front surface of the substrate 130 to be tested and expose the front surface of the substrate 130 to be tested.
Step S130: and grinding the back surface of the substrate to be detected, judging whether the substrate to be detected is ground to a target thickness, if so, stopping grinding, and grinding the substrate to be detected to the target thickness to form a plane TEM sample.
After the front surface of the substrate 120 to be tested is adhered to the glass slide 200, the substrate 120 to be tested is supported and fixed by the glass slide 200, so that the substrate 120 to be tested is thinned from the back surface of the substrate 120 to be tested, wherein the back surface of the substrate 120 to be tested is the back surface 100A of the semiconductor substrate 100. In an embodiment, the back surface of the substrate 120 to be measured is ground to gradually thin the substrate 120 to a target thickness, and after the substrate 120 to be measured is thinned to the target thickness, the planar TEM sample 130 is formed, where the target thickness is the thickness of the planar TEM sample 130, that is, the planar TEM sample refers to a sample whose front surface of the semiconductor substrate is used as an observation surface, and whose thickness perpendicular to the front surface meets the TEM observation thickness. In general, the polishing strength of the edge of the substrate 120 to be tested is greater than that of the middle region during the polishing process, and the length and width of the substrate 120 to be tested are polished smaller and smaller during the polishing process, but it is required to ensure that the target position 110 is not polished away. As shown in fig. 2c, in an embodiment, in the process of grinding the substrate 120 to be measured, the size of the substrate 120 to be measured is gradually decreased, and since the forces on the two sides of the substrate 120 to be measured are not completely uniform, the grinding speed on one side is slightly greater than the grinding speed on the other side, and the method for determining whether the substrate 120 to be measured has been ground to the target thickness may be: and observing whether the edge of the ground substrate 120 to be detected has the colored pattern 131 under a microscope, if so, further observing whether the target position 110 is positioned on the colored pattern 131, and if so, judging that the substrate 120 to be detected is ground to the target thickness to form the planar TEM sample 130. In other embodiments, the thickness of the substrate 120 to be tested may also be measured by an instrument.
In an embodiment, the step of grinding the back surface of the substrate 120 to be tested specifically includes: the back of the substrate 120 to be tested is ground by using 320-mesh, 600-mesh, 800-mesh and 1200-mesh sandpaper in sequence, and then the back of the substrate 120 to be tested is polished by using polishing flannelette. The polishing speed can be lower than the speed of using the sand paper for grinding, the sand paper grinding with relatively high speed is firstly carried out, the substrate 120 to be measured is quickly thinned, the mesh number of the sand paper is adjusted in the grinding process, the higher the mesh number of the sand paper is, the finer the grinding is, and the smoother the surface of the grinding part is. After high-speed grinding to a certain degree, observing the substrate 120 to be detected facing a fluorescent lamp, judging whether red light is transmitted near the target position 110 in the substrate 120 to be detected, observing whether the edge of the substrate 120 to be detected has color patterns 131 under a microscope, if so, changing sand paper into polishing flannelette, reducing the speed, and continuously polishing the substrate 120 to be detected at low speed to remove chips and scratches near the target position 110 and avoid the interference of the chips and scratches on an observed image. And observing whether the target position 110 is just on the colored pattern 131 after polishing, if so, stopping grinding, and obtaining the planar TEM sample 130 as the substrate 120 to be detected which is ground to the target thickness.
Step S140: and adhering the metal ring to the back of the plane TEM sample, and cutting the plane TEM sample along the outer side of the metal ring to cut off the plane TEM sample on the outer side of the metal ring, wherein the target position is located at the central position of the metal ring.
In some embodiments, as shown in fig. 2d, to match the subsequent observation of the planar TEM sample 130, a metal ring 300 is attached to the back surface of the planar TEM sample 130, and the planar TEM sample 130 is cut along the outer side of the metal ring 300, so that the target position 110 is located at the center of the metal ring 300. In one embodiment, the metal ring 300 may be a copper ring. In an embodiment, the metal ring 300 is attached to the back of the planar TEM sample 130 by a two-component epoxy adhesive, which is also called as AB glue, and the AB glue is prepared by mixing a main agent and a hardening agent, wherein the main agent is glue a, and the hardening agent is glue B, specifically, after the glue a and the glue B are mixed to form the AB glue, the metal ring 300 is dipped in a small amount of the AB glue and attached to the back of the planar TEM sample 130, and the target position 110 is located at the center of the metal ring 300, the planar TEM sample 130 and the glass slide 200 which are attached together are together placed into a nitrogen cabinet to be air-dried for 15 minutes, so that the glue is solidified, and then the planar TEM sample 130 is cut off along the outer side of the metal ring 300 by an art designer.
Step S150: and separating the plane TEM sample from the glass slide to obtain the plane TEM sample adhered to the metal ring.
In step S140, the metal ring 300 and the slide glass 200 are attached to both sides of the obtained planar TEM sample 130, and the slide glass 200 is not required to be used in the subsequent process. As shown in fig. 2e, the slide 200 is separated from the planar TEM sample 130, i.e., the slide 200 is peeled off, resulting in the planar TEM sample 130 adhered only to the metal ring 300. In one embodiment, when the plane TEM sample 130 and the slide glass 200 are adhered by paraffin, the plane TEM sample 130 may be soaked in acetone for 20 minutes to 30 minutes to separate the plane TEM sample 130 adhered to the metal ring 300 from the slide glass 200, and then the metal ring 300 and the plane TEM sample 130 adhered together are taken out of the acetone by tweezers and dried to perform the subsequent process.
Step S200: and adhering the back surface of the plane TEM sample on the conductive pad by using an adhesive, wherein the thickness of the adhesive is less than or equal to 50 μm.
Since the planar TEM sample 130 is thin and small in size, it is difficult to perform a subsequent cutting process, and the planar TEM sample 130 needs to be fixed on a pad. In the present application, since the planar TEM sample 130 is subsequently FIB cut, the FIB bench scans the planar TEM sample 130 to obtain a scanned image of the defect before FIB cutting. The step of scanning the plane TEM sample 130 by the FIB station to obtain a scanning image of the defect is to irradiate an ion beam by the FIB station to bombard the surface of the plane TEM sample 130, generate secondary ions and secondary electrons on the plane TEM sample 130, receive the secondary ions and the secondary electrons by the FIB station to generate a scanning image according to the secondary ions and the secondary electrons, and determine the shape and the plane position of the defect from the scanning image, so as to realize accurate cutting at the defect. Therefore, the spacer in the present application needs to have a certain conductivity to ensure the generation rate of secondary electrons during scanning, thereby ensuring the quality of the scanned image. Referring to fig. 3a and 3B, in the present embodiment, the back surface 130B of the planar TEM sample 130 is adhered to the conductive pad 400 by the adhesive 500, wherein the front surface of the planar TEM sample 130 is the front surface 100A of the original semiconductor substrate 100, and the back surface 130B of the planar TEM sample is the surface opposite to the front surface 100A. In one embodiment, a silicon wafer may be used as the conductive pad 400. In the present application, the planar TEM sample 130 and the conductive pad 400 are bonded by the adhesive 500, and since the quality of the scanned image is affected by the conductivity of the conductive pad 400, and the thickness of the adhesive 500 may affect the conductivity of the conductive pad 400, in the present application, by controlling the thickness of the adhesive 500 to be less than or equal to 50 μm, specifically 10 μm to 50 μm, under the thickness dimension, the adhesive 500 has no influence on the conductivity of the conductive pad 400, not only the planar TEM sample 130 and the conductive pad 400 can be fixed well, but also the quality of the scanned image can be ensured. In one embodiment, the adhesive 500 may be AB glue. If the adhesive 500 is a double-sided tape, the surface of the double-sided tape is rough, which easily damages the plane TEM sample 130, and if the adhesive 500 is paraffin, which has poor paraffin stability, the paraffin will overflow the front surface of the plane TEM sample 130 after hot melting, which pollutes the scanning area. The AB glue has good viscosity and strong stability, only a little AB glue is needed, the thickness of the glue is controlled to be 10-50 μm, the plane TEM sample 130 and the conductive gasket 400 can be well fixed, the front surface of the plane TEM sample 130 cannot be damaged or polluted, and the quality of an FIB scanning image cannot be influenced. In a specific embodiment, a small amount of AB glue is coated on the conductive pad 400, the thickness of the AB glue is controlled to be between 10 μm and 50 μm, the back surface of the planar TEM sample 130 is attached to the conductive pad 400, and the planar TEM sample is air-dried for 15 minutes to 20 minutes. In one embodiment, when the metal ring 300 is attached to the back surface of the planar TEM sample 130, the metal ring 300 may be attached to the conductive pad 400.
In an embodiment, between step S100 and step S200, the following steps may be further included:
and observing the plane TEM sample, judging whether the defects exist in the plane TEM sample, and if so, executing the step S200.
In step S100, when the semiconductor substrate 100 is thinned, if the defect position is deep, the defect may be removed during the thinning process, and once the defect is removed, step S200 and the subsequent steps are meaningless. Therefore, step S200 may be performed after the planar TEM sample 130 is scanned before step S200 and the defect is determined to be still located in the planar TEM sample 130, and if the defect does not exist in the manufactured planar TEM sample 130, that is, the depth of the defect is greater than the thickness of the TEM sample, the defect is not suitable for analysis by the method for manufacturing the TEM sample, and the subsequent steps need to be stopped.
Step S300: determining the appearance and the plane position of the defect, and cutting the defect at the plane position of the defect by adopting a focused ion beam and vertical to the plane TEM sample to prepare a section TEM sample, wherein the defect is positioned on the section of the section TEM sample.
After the planar TEM sample 130 is fixed to the conductive spacer 400, FIB cutting of the planar TEM sample 130 can be performed. The FIB machine can scan and cut the plane TEM sample 130, before cutting, the front of the plane TEM sample 130 is scanned, the appearance and the plane position of the defect are obtained according to the scanned image, then FIB cutting is performed on the plane TEM sample 130 at the position of the defect, a small sample is cut from the plane TEM sample 130, and the defect is located in the cut section, so as to obtain the section TEM sample 131. Referring to fig. 3a and 4, the TEM sample 131 has four cut sections, the projections of which form a quadrilateral, the defect is located in one of the sections 131C, and the section 131C containing the defect is a vertical section. In one embodiment, the cross section 131C may be rectangular or inverted trapezoidal. When the cross section 131C including the defect is defined as a plane formed by the X axis and the Z axis, and the width direction of the cross section TEM sample 131 is the Y axis direction, the width b of the cross section TEM sample 131 corresponds to the thickness of the TEM sample, that is, the cross section TEM sample refers to a thickness satisfying the TEM observation with the cross section 131C having the defect as the observation plane and the thickness (width b) perpendicular to the cross section direction. In an embodiment, the width b of the cross-sectional TEM sample 131 is less than or equal to
Figure GDA0003318122770000122
The thickness h of the cross-sectional TEM sample 131 is the thickness of the planar TEM sample 130, and in one embodiment, the thickness h is less than or equal to
Figure GDA0003318122770000121
The length a of the cross-sectional TEM sample 131 is relatively long and may be in the order of micrometers, i.e., the cross-sectional TEM sample 131 may be a strip structure. The observation of the section TEM sample 131 is actually an observation of a section 131C where the section TEM sample 131 has a defect, and the width b of the section TEM sample 131 satisfies the TEM observation thickness so that a TEM scan can be performed on the section to form a clear scan image. In one embodiment, theAfter the TEM sample 131 is formed, a section 131C of the TEM sample 131 having a defect is scanned, a scanned image of the section is obtained, and the position of the defect on the section is found, so that the depth of the defect can be measured. In one embodiment, FIG. 5 is a frontal scan of a planar TEM specimen 130, wherein the topography and planar position of the defect can be obtained from the scan, wherein the defect (within the dashed box) is linear. As shown in fig. 6, which is a cross-sectional view obtained by cutting fig. 5, the defect (within the dotted line frame) is located in the cross-sectional plane, and the depth of the defect can be measured after the cross-sectional image is obtained.
According to the TEM sample preparation method, the section TEM sample can be prepared, the defect is located on the section of the section TEM sample, and the information of the defect in the thickness direction of the semiconductor substrate, such as the depth of the defect, can be obtained by observing the section of the section TEM sample, so that the preparation process of the semiconductor device causing the defect can be deduced from the obtained defect information, the process can be improved, the same problem of more products can be avoided, and the product yield can be improved.
The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A TEM sample preparation method is characterized by comprising the following steps:
determining a target position with defects on a semiconductor substrate, thinning the semiconductor substrate from the back side of the semiconductor substrate to prepare a planar TEM sample, wherein the thickness of the planar TEM sample is less than or equal to 6000A, and the target position is located in the planar TEM sample;
adhering the back surface of the plane TEM sample to a conductive pad by using adhesive glue, wherein the thickness of the adhesive glue is less than or equal to 50 micrometers; and
determining the appearance and the plane position of the defect, and cutting the defect at the plane position of the defect by adopting a focused ion beam to be vertical to the plane TEM sample to prepare a section TEM sample, wherein the defect is positioned on the section of the section TEM sample, and the depth information of the defect in the thickness direction of the semiconductor substrate can be acquired;
wherein the adhesive is a two-component epoxy resin adhesive.
2. The method of manufacturing of claim 1, further comprising, after said step of forming a planar TEM sample and before said step of attaching the back surface of said planar TEM sample to the conductive pad with an adhesive, the steps of:
and observing the plane TEM sample, judging whether the defect exists in the plane TEM sample, and if so, executing the step of adhering the back surface of the plane TEM sample on the conductive gasket by using the adhesive.
3. The method of claim 1, wherein the conductive pad is a silicon wafer.
4. The method of making of claim 1, wherein the cross-sectional TEM sample has a thickness perpendicular to the cross-sectional direction that is less than or equal to 1000 a.
5. The method of claim 1, wherein the adhesive has a thickness ranging from 10 μm to 50 μm.
6. The method of manufacturing of claim 1, further comprising, after manufacturing the cross-sectional TEM sample:
the cross section of the cross section TEM sample is observed and the depth of the defect is measured.
7. The method of manufacturing of claim 1, wherein the step of determining a defect region on a semiconductor substrate and thinning the semiconductor substrate from a back side of the semiconductor substrate to produce a planar TEM sample specifically comprises:
marking a target position with a defect on the front surface of the semiconductor substrate;
cutting the semiconductor substrate to form a substrate to be tested, and pasting the front surface of the substrate to be tested on a glass slide, wherein the target position is located at the center of the substrate to be tested;
grinding the back surface of the substrate to be detected, judging whether the substrate to be detected is ground to a target thickness, if so, stopping grinding, and grinding the substrate to be detected to the target thickness to form the plane TEM sample;
adhering a metal ring to the back of the plane TEM sample, and cutting the plane TEM sample along the outer side of the metal ring to cut off the plane TEM sample on the outer side of the metal ring, wherein the target position is located at the central position of the metal ring; and
and separating the plane TEM sample from the glass slide to obtain the plane TEM sample adhered to the metal ring.
8. The method for preparing a test device according to claim 7, further comprising, before the step of attaching the front surface of the substrate to be tested to a slide glass:
and soaking the substrate to be tested in hydrofluoric acid to remove the process layer on the front surface of the substrate to be tested and expose the front surface of the semiconductor substrate.
9. The method according to claim 7, wherein the step of grinding the back surface of the substrate to be tested specifically comprises:
and grinding the back of the substrate to be detected by using 320-mesh, 600-mesh, 800-mesh and 1200-mesh sandpaper in sequence, and then polishing the back of the substrate to be detected by using polishing flannelette.
10. The production method according to claim 7, wherein the semiconductor substrate is marked at a target position by laser or FIB.
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