CN103858172B - 用于交叉点存储器结构的选择设备 - Google Patents
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Abstract
本公开提供了一种存储器单元,其包括放置在第一导体和第二导体之间的电阻存储器元件,第一导体和第二导体被配置用来激活电阻存储器元件。存储器单元还包括与存储器元件串联放置在存储器元件和第一导体或第二导体之间的反向二极管。
Description
背景技术
交叉点存储器阵列是放置在存储器单元之上和之下正交走向的两组导体之间的存储器单元的阵列。第一组导体例如放置在存储器单元之下,可以被称作字线;而第二组导体放置在存储器单元之上,可以被称作位线。在交叉点存储器阵列中的每个存储器单元被放置在单个字线和单个位线的交叉点处。在阵列之内选择单个存储器单元用于读取或者写入存储器单元可以通过激活与那个存储器单元相关联的字线和位线实现。读取所选择的存储器单元可以通过把电压施加到字线并且测量经过所选择的存储器单元的所产生的电流实现。在读取所选择的存储器单元的过程中,可以在邻近所选择的存储器单元的存储器单元中生成泄露电流,其也被称为寄生电流或者半选电流。泄露电流加到经过所选择的存储器单元的电流,可能导致不正确的结果。
附图说明
在下面的具体实施方式中参考附图描述了某些实施例,其中:
图1是按照实施例的数据存储设备的框图;
图2是按照实施例的反向二极管的电流-电压图;
图3是按照实施例的存储器单元的电路图;
图4是按照实施例的存储器单元阵列的立体图,显示了在读取操作的过程中的主电流路径和泄露电流路径。
具体实施方式
交叉点存储器阵列通常包括选择设备,例如晶体管,其防止经过未经选择的存储器单元的泄露电流影响所选择的存储器单元的读取或写入。例如,晶体管可以与存储器单元串联放置在字线和位线之间,以通过如下方法提供隔离:通过控制门关闭未经选择的设备。然而,这样的配置在存储器阵列内消耗不动产(real estate),因此减少了在阵列中的存储器单元的密度。在一些存储器阵列中,存储器单元可以是非隔离的设备。为了减少泄露电流在这样的存储器阵列中的影响,可以使用多次采样技术来读取存储器单元。然而,使用了额外的架构上的开销来实现多次采样技术。在一些存储器阵列中,存储器单元可以被配置用来展示非线性特征,以便存储器元件自身抑制泄漏电流。
按照本技术的实施例,在交叉点阵列中的每个存储器单元包括与存储器元件串联放置在字线和位线之间的反向二极管。反向二极管用作选择设备,其减少经过与所选择的存储器单元邻近的存储器单元的泄漏电流,同时允许相对大的电流流过所选择的存储器单元。进一步的,反向二极管允许电流沿正向和反向两个方向流过存储器单元,这样能够写入双极存储器单元。通过在每个存储器单元之内合并选择设备,可以增加存储器阵列的存储器密度,并且可以消除用于实现多次采样技术的额外的电路架构。
使用反向二极管允许放松忆阻器或者其他存储器元件的非线性要求。在不展示非线性特征的其他形式的存储器中这可能是有用的。进一步的,通过将选择设备与位自身串联放置,下面的硅不动产可用于其他设备例如解码器、交换矩阵、感测和驱动电路等等。反向二极管的使用还提高消除晶体管的使用的可实现存储器密度,以在存储器单元之间提供隔离。
图1是按照实施例的数据存储设备的框图。如图1显示的,数据存储设备100可以包括以行和列布置的存储器单元102阵列。一组在这里被称为字线104的导电电极延伸到存储器单元102阵列的一侧。每条字线104与特定行的存储器单元102电接触。一组在这里被称为位线106的导电电极延伸到存储器单元102阵列的另一侧。每条位线106与特定列的存储器单元102电接触。每个存储器单元102处在一条字线104和一条位线106的交叉点。每个存储器单元102可以被选择用于写入或读取,通过激活与那个存储器单元102相关联的特定字线104和位线106。如参照图3进一步在下面讨论的,每个存储器单元102可以包括与反向二极管串联耦合的忆阻器。
数据存储设备也包括通过各自字线104耦合到存储器单元102的字线控制电路108,并且所述字线控制电路108被配置用来激活特定的字线104,用于读取或写入与字线104相关联的特定存储器单元102。例如,字线控制电路108可以包括复用器,用于选择特定的一条字线104。在为了读取或写入操作访问特定的存储器单元的过程中,所选择的位线和未经选择的位线将会由字线控制电路108设定到相同的电压。数据存储设备也包括通过各自位线106耦合到存储器单元102的位线控制电路110。位线控制电路110可以包括解复用器112、感测电路114和输入/输出(I/O)底板116。解复用器112可以被配置用来选择性地将所选择的存储器单元102的位线106耦合到感测电路114。字线控制电路108和位线控制电路110通过激活耦合到所选择的存储器单元102的对应的字线104和位线106而一致行动来访问个体存储器单元102。应当理解在这里描述的字线控制电路108和位线控制电路110是电路的示例,其可以被用在访问存储器单元102的示例性实施例中。本领域技术人员已知的其他配置可以被用于访问依照本技术的存储器单元102。
在写入操作的过程中,字线控制电路108通过把电压施加到对应于所选择的存储器单元102的特定字线104,将信息写入到所选择的存储器单元102。通过将存储器单元102耦合接地,位线控制电路110的解复用器112激活所选择的存储器单元102。电流然后流过所选择的存储器单元102,其影响存储器单元102的属性,实际上存储逻辑一或逻辑零到存储器单元102。例如,如果包括在存储器单元102中的存储器元件300是忆阻器,那么流过忆阻器的电流改变忆阻器的电阻。在接下来的读取操作过程中,可以检测电阻中的改变。
在读取操作的过程中,字线控制电路108通过将特定的电压施加到对应的字线104来激活所选择的存储器单元102,并且解复用器112将对应于所选择的存储器单元102的位线106耦合到感测电路114。由感测电路114检测到的结果电流指示了存储器单元102的状态,例如,存储器单元102对应于逻辑一还是逻辑零。读取的结果然后被发送到数据存储设备的I/O底板116。如参照图4进一步在下面解释的,读取所选择的存储器单元102可以受到在与所选择的存储器单元102邻近的存储器单元102中生成的泄露电流影响,其可以导致不正确的读取结果。在实施例中,每个存储器单元102包括反向二极管,其被配置用来减少来自邻近单元的泄露电流,从而减少在读取的过程中得到不正确结果的可能性。以这种方式,反向二极管用作选择设备,其将所选择的存储器单元102从邻近存储器单元102隔离开。
图2是按照实施例的反向二极管的电流-电压图。电流-电压图200显示了反向二极管在正向偏压和反向偏压情况下的I-V特性。术语“反向二极管”指的是相比较于正向偏置电压,对反向偏置电压展现更好的传导属性的二极管。例如,如图2所显示的,当反向二极管是正向偏压的时,经过反向二极管的电流展现如典型的稳压二极管的相同特性。换句话说,在电压阈值Vth之下时,经过反向二极管的电流保持接近于零。反向二极管在正向偏压方向不传导大量的电流,直到电压超过了电压阈值Vth。然而,当反向二极管是反向偏压的时,反向二极管差不多立即开始传导。换句话说,对于小的偏置电压,反向二极管在反向偏压方向比在正向偏压方向传导更大的电流。在实施例中,如果使用硅技术,则反向二极管的阈值电压Vth可以是大约0.5-0.7伏特。反向二极管可以使用任何合适的晶体的、多晶的或者非晶体的半导体实现,其可以是服从例如掺杂的标准制造工艺。合适的半导体材料还可以包括硅、砷化镓和锗,等等。例如,反向二极管可以通过在Si CMOS(互补金属氧化物半导体)底层电路的顶部沉积硅薄膜实现。进一步的,反向二极管可以是
在一些实施例中,反向二极管的阈值电压小于写入电压,并且大于写入电压的一半。例如,写入电压Vw1可以被用于将存储器单元102设定为代表逻辑一的电阻值,并且写入电压Vw2可以被用于将存储器单元102重置到代表逻辑零的电阻值。例如在硅基反向二极管的情况下,Vw1可以大约是1.0到2.0伏特而Vw2可以大约是-0.5到1.5伏特。应当理解在图2中显示的电压不是按比例绘制。反向二极管和存储器单元102将会在两个写入操作的过程中传导电流。在所选择的存储器单元的写入过程中,跨越邻近存储器单元的电压将会总小于写入电压的一半减去反向二极管的阈值电压(即小于Vw/2-Vth),其有效地隔离未经选择的存储器单元。换句话说,反向二极管允许相对高的电流经过所选择的存储器单元102,同时在相邻的存储器单元102中抑制流向相反方向的电流。
在存储器单元102的读取过程中,读取电压VR的量级可以小于反向二极管的电压阈值,例如,大约是反向二极管的阈值电压的一半。例如对于硅基反向二极管的情况,读取电压VR可以是在从大约0.1到0.5伏特的范围中。进一步的,在反向二极管处的电压降是可以忽略的,因为它是反向偏压的。进一步的,施加到所选择的存储器单元102的电压将是反向偏置电压,其允许电流从阴极到阳极经过反向二极管。通过在存储器单元102中将反向二极管放置在忆阻器设备之前或者之后,跨越邻近的、未经选择的存储器单元的电压将会总是小于读取电压的一半减去反向二极管的阈值电压(即,小于VR/2-Vth),其有效地隔离未经选择的存储器单元。换句话说,反向二极管允许相对高的电流通过所选择的存储器单元102,同时在邻近的存储器单元102中抑制流向相反方向的电流。
图3是按照实施例的存储器单元的电路图。如图3所显示的,每个存储器单元102可以包括存储器元件300和反向二极管302,反向二极管302放置在对应的字线104和位线106之间与存储器单元300串联。存储器元件300可以是电阻存储器元件,例如忆阻器、相变材料电阻器、导电桥电阻器、基于过渡金属氧化物的电阻器或者任何电阻变化存储器的实施例。如这里使用的,术语“电阻存储器元件”是指这样的存储器元件:其中存储器元件的逻辑状态(例如,它存储一还是零)由存储器元件的电阻指示。在电阻存储器元件中,由存储器元件展示的电阻可以被改变,例如通过让电流流过电阻存储器元件或者让电阻存储器元件处于磁场中。
反向二极管302的极性可以被定向,以便所选择的存储器单元102的反向二极管302在读取操作的过程中将是反向偏压的,同时,至少一些邻近存储器单元102的反向二极管302在小于反向二极管302的电压阈值的电压级别处将是正向偏压的。以这种方式,在读取操作的过程中,反向二极管302使电流能够经过所选择的存储器单元102,同时抑制泄露电流经过邻近单元。在实施例中,反向二极管302可以由能够在低温下沉淀的材料制成,例如非晶硅和微晶硅等。以这种方式,反向二极管302可以通过将非晶硅、微晶硅或者其一些组合放置在已经形成的存储器元件300之上制成,而不会消极影响存储器元件300。参照图4可以更好地理解将反向二极管302与每个存储器元件300串联放置的效果。
图4是按照实施例的存储器单元阵列的立体图,显示了在读取操作的过程中的主电流路径和泄露电流路径。如图4所显示的,存储器单元阵列包括存储器单元102的矩阵,其电耦合到标记为WL1-WL5的字线104和标记为BL1-BL4的位线106。进一步的,所选择的存储器单元400已经由字线控制电路108和位线控制电路110激活用来读取所选择的存储器单元400。所选择的存储器单元400处在字线WL2和位线BL3的交叉点。如图4所显示的,通过将读取电压VR施加到所选择的存储器单元400的字线104上并且将所选择的存储器单元400的位线106耦合到感测电路114,来读取所选择的存储器单元400。为所选择的存储器单元400测量的电流指示所选择的存储器单元400的逻辑状态,换句话说,所选择的存储器单元400是存储逻辑一还是零。作为非限制性的示例,感测电路114可以包括:感测放大器,耦合到位线106的电流到电压转换器402,以及耦合到电流到电压转换器402的输出的比较器404。电流到电压转换器402的输出电压与经过所选择的存储器单元400的电流是成比例的。比较器404对电流到电压转换器402的输出电压和阈值电压进行比较,以判定所选择的存储器单元400的逻辑状态。
图4也显示了由将电压施加到所选择的存储器单元400的字线104造成的经过存储器单元阵列的电流路径。通过所选择的存储器单元102的主电流路径用实线箭头显示。泄露电流的路径由虚线箭头显示,并且沿着经过三个邻近的存储器单元102(称为存储器单元A406、存储器单元B408和存储器单元C410)的路径。如虚线显示的,在所选择的存储器单元400的字线104上的电压趋于提升泄漏电流,其沿着这样的路径:从所选择的字线104经过邻近的存储器单元A406到邻近的位线106,沿着邻近的位线106到存储器单元B408,经过存储器单元B408到邻近的字线104,沿着所述邻近的字线104到邻近的存储器单元C410,并且经过存储器单元C410到所选择的位线106。沿着这条路径的任何泄露电流将会加到经过所选择的存储器单元400的主电流。尽管显示了单条泄露路径,但应当理解对其他邻近的存储器单元102将会存在相似的泄漏路径。
基于显示的泄露路径,可以看出,被放置在邻近位线106和邻近字线104的交叉点处的存储器单元B408与所选择的存储器单元400相比,具有相反的电压极性。因此,当所选择的存储器单元400的反向二极管302(图3)是反向偏压的时,邻近存储器单元B408的反向二极管302将会是正向偏压的。进一步的,读取电压VR的量级小于每个反向二极管302的电压阈值。因此,存储器单元B408的反向二极管302有效地阻挡大量电流经过邻近的存储器单元B并且抑制泄露电流。同时,所选择的存储器单元400的反向偏压的反向二极管302允许电流经过所选择的存储器单元400。
Claims (10)
1.一种存储器单元,包括:
电阻存储器元件,其放置在第一导体和第二导体之间,所述第一导体和所述第二导体被配置用来激活所述电阻存储器元件;以及
反向二极管,其与存储器元件串联放置在所述存储器元件和所述第一导体或者第二导体之间,
其中所述电阻存储器元件被配置成通过跨越所述第一导体和所述第二导体施加电压而被读取,所述电压反向偏置所述反向二极管并且小于所述反向二极管的阈值电压,
其中所述反向二极管被配置用来展示小于写入电压量级并且大于所述写入电压量级的一半的阈值电压。
2.如权利要求1所述的存储器单元,其中所述电阻存储器元件包括以下中的至少一个:忆阻器、相变材料电阻器、导电桥电阻器、基于过渡金属氧化物的电阻器。
3.如权利要求1所述的存储器单元,其中所述反向二极管包括非晶硅、微晶硅或其组合。
4.一种数据存储设备,包括
存储器单元阵列,其包括多个存储器单元;
字线,其放置在所述存储器单元阵列的第一侧,并且电耦合到所述多个存储器单元;以及
位线,其放置在所述存储器单元阵列的第二侧,与所述字线正交,并且电耦合到所述多个存储器单元,
其中在所述多个存储器单元中的每个存储器单元处在一个所述字线和一个所述位线的交叉点;
其中所述多个存储器单元中的每个包括:
电阻存储器元件,其放置在一个所述字线和一个所述位线之间;以及
反向二极管,其与存储器元件串联放置在所述存储器元件和所述字线或者位线之间,
其中所述多个存储器单元中的所选择的存储器单元被配置成通过跨越对应于所述所选择的存储器单元的字线和位线施加电压而被读取,所述电压反向偏置所述所选择的存储器单元的反向二极管,并且所述电压的量级小于所述所选择的存储器单元的所述反向二极管的阈值电压,
其中所述反向二极管被配置用来展示小于写入电压量级并且大于所述写入电压量级的一半的阈值电压。
5.如权利要求4所述的数据存储设备,其中所述电阻存储器元件包括以下中的至少一个:忆阻器、相变材料电阻器、导电桥电阻器、基于过渡金属氧化物的电阻器。
6.如权利要求4所述的数据存储设备,其中所述多个存储器单元中的所选择的存储器单元被配置成通过跨越对应于所述所选择的存储器单元的字线和位线施加电压而被读取,所述电压反向偏置所述所选择的存储器单元的反向二极管,并且所述电压正向偏置在泄露电流路径中的至少一个所述存储器单元的反向二极管。
7.如权利要求4所述的数据存储设备,其中所述反向二极管包括:非晶硅、微晶硅或其组合。
8.一种形成存储器单元的方法,包括:
在两个电极之间放置电阻存储器元件;
在两个电极之间放置与所述电阻存储器元件串联的反向二极管,
其中所述电阻存储器元件被配置成通过跨越所述两个电极施加电压而被读取,所述电压反向偏置所述反向二极管并且小于所述反向二极管的阈值电压,
其中所述反向二极管被配置用来展示小于写入电压量级并且大于所述写入电压量级的一半的阈值电压。
9.如权利要求8所述的方法,其中放置所述电阻存储器元件包括:形成忆阻器。
10.如权利要求8所述的方法,其中放置所述反向二极管包括:在所述电阻存储器元件上形成包括非晶硅、微晶硅或其组合的反向二极管。
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US20160148681A1 (en) * | 2014-11-20 | 2016-05-26 | Infineon Technologies Ag | Parallel forming of memory cells |
US9934852B2 (en) | 2015-01-23 | 2018-04-03 | Hewlett Packard Enterprise Development Lp | Sensing an output signal in a crossbar array based on a time delay between arrival of a target output and a sneak output |
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