WO2016153513A1

WO2016153513A1 - Code comparators

Info

Publication number: WO2016153513A1
Application number: PCT/US2015/022666
Authority: WO
Inventors: Ning GE; Jianhua Yang; Zhiyong Li; R. Stanley Williams
Original assignee: Hewlett Packard Enterprise Development Lp
Priority date: 2015-03-26
Filing date: 2015-03-26
Publication date: 2016-09-29

Abstract

A code comparator has a processor and a memristor array having a plurality of row lines, a plurality of column lines, and a plurality of memristors. The processor is to assign a row voltage value to the row lines, where the row voltage value corresponds to a first code, and a column voltage value to the column lines, where the column voltage value corresponds to a second code. The processor is to cause a voltage to be applied to the row lines according to the row voltage values and a voltage to be applied to the column line that is according to the column voltage values. A state of the memristor changes when the voltage applied to the row line differs from the voltage applied to the column line. The processor is to compare the first code with the second code based on the states of the memristors.

Description

CODE COMPARATORS

BACKGROUND

[0001 ] Memristors are passive two terminal devices that can be programmed to different resistive states by applying a programming energy, such as a voltage. Large crossbar arrays of memory devices can be used in a variety of applications, including random access memory, non-volatile solid state memory, programmable logic, signal processing control systems, pattern recognition, and other applications.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The following detailed description references the drawings, wherein:

[0003] FIG. 1 A is a block diagram of an example code comparator; [0004] FIG. 1 B is a diagram of an example memristor array; [0005] FIG. 2 is a diagram of an example code comparator;

[0006] FIG. 3 is a block diagram of an example system for comparing a first code with a second code; and

[0007] FIG. 4 is a flowchart of an example method for comparing a first code with a second code.

DETAILED DESCRIPTION

[0008] For simplicity and illustrative purposes, the present disclosure is described by referring mainly to examples thereof. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It should be apparent, however, that the present disclosure may be practiced without limitation to these specific details. In other instances, some methods and structures have not been described in detail so as not to unnecessarily obscure the present disclosure. As used herein, the terms "a" and "an" are intended to denote at least one of a particular element, the term "includes" means includes but not limited to, the term "including" means including but not limited to, and the term "based on" means based at least in part on.

[0009] With the rapid growth in electronic communication, encryption and security has become increasingly important particularly in the presence of third parties. Digital signatures are a method for increasing security. A digital signature is a mathematical scheme for demonstrating authenticity of a digital message or document. Digital signatures and other security protocols may utilize frequent code checks to verify authenticable encryptions.

[0010] Memristors are devices that may be used as components in a wide range of electronic circuits, such as memories, switches, radio frequency circuits, and logic circuits and systems. A crossbar array of memristors may be used to store bits of information, 1 or 0. The resistance of a memristor may be changed by applying an electrical stimulus, such as a voltage or a current, through the memristor. Generally, at least one channel may be formed that is capable of being switched between two states— one in which the channel forms an electrically conductive path ("ON") and one in which the channel forms a less conductive path ("OFF"). In some other cases, conductive paths represent "OFF" and less conductive paths represent "ON". In such a manner, memristors may be switched between at least two resistance states.

[001 1 ] Examples disclosed herein provide for code comparators for comparing a first code with a second code. In example implementations, a code comparator may include a processor and a memristor array having a plurality of row lines, a plurality of column lines, and a plurality of memristors coupled between the row lines and the column lines. The example code comparator assigns a row voltage value to the plurality of row lines corresponding to a first code. The example code comparator assigns a column voltage value to the plurality of column lines according to a second code. The example code comparator causes a voltage to be applied to row lines according to the row voltage values and a voltage to be applied to column lines according to the column voltage values. The resistance state of a memristor of the array may change if there is a net voltage across it. Accordingly, the example code comparator may compare the first code with the second code based on the states of the memristors.

[0012] Referring now to the drawings, FIG. 1A depicts an example code comparator 100, which may include a processor 1 10 and a memristor array 120. Processor 1 10 and memristor array 120 may communicate via a connection. For example, processor 1 10 and memristor array 120 may be attached to an integrated circuit, which provides a connection between the two components. It should be understood that the code comparator depicted in FIG. 1A may include additional components and that some of the components described herein may be removed or modified without departing from the scope of code comparator 100.

[0013] Processor 1 10 may be one or more central processing units (CPUs), semiconductor-based microprocessors, and/or other hardware devices suitable for executing instructions for comparing codes. As an alternative or in addition to retrieving and executing instructions, processor 1 10 may include one or more electronic circuits that include electronic components for performing the functionality described herein.

[0014] Memristor array 120 may be a configuration of sets of parallel crossing lines with memristors and/or other components coupled between intersections of lines. For example, memristor array 120 may have a first plurality of parallel lines referred to as row lines intersecting another plurality of parallel lines referred to as column lines, where memristors serve as cross-points of the lines. Each memristor of memristor array 120 may be coupled between a unique combination of a row line and a column line. In other words, no memristors share both a row line and a column line. As used herein, components may be coupled by forming an electrical connection between the components. For example, memristors may be coupled to lines by forming a direct, surface contact or by other forms of physical connection.

[0015] A memristor may be a device that may be programed to different resistive states by applying a voltage or current. Furthermore, a memristor may "memorize" its last resistance even if the applied voltage or current is removed. In such a manner, a memristor may store digital data. In some examples, a sufficiently high current compliance may be set on the memnstors to enable the resistance states of the memristors to be switched in response to the application of a voltage.

[0016] A memristor may be bipolar or unipolar. Bipolar memristors may depend on the polarity of an applied voltage. Specifically, bipolar memristors may be switched from a first state to a second state by application of a voltage of a first polarity, while they may be switched from the second state to the first state by application of a voltage of a second polarity. Unipolar memristors, on the other hand, may depend on the amplitude of an applied voltage.

[0017] In the examples provided herein, the memristors may have unipolar behavior. In some implementations, memristors may have nonpolar switching behavior. Nonpolar memristors may be unipolar memristors which may exhibit amplitude-based switching with both positive and negative voltages. In some examples, the positive voltage range and the negative voltage range that promote switching of a nonpolar memristor may be symmetrical with respective to each other.

[0018] To compare a first code with a second code, processor 1 10 may assign a row voltage value to at least one of the plurality of row lines. The row voltage may correspond to the first code, which for purposes of illustration may be the key code to which other codes are compared. For example, a digital code string may be assigned to the rows as two separate voltage values. For example, a row line corresponding to a digital "0" may be assigned a first row voltage, while a row line corresponding to a digital "1 " may be assigned a second row voltage. In some examples, the first row voltage may be below the switching voltage of the memristor, and the second row voltage may be above the switching voltage.

[0019] In some examples, the first code may be an analog code. Using analog values may allow increased security. For example, values in a bit string can be represented with more than two discrete voltage values as would be needed when using digital values. For example, for a bit string with digital value of 101 1 , the analog voltage for each value can be 15V, 0V, 10V, and 5V, while the digital form may normally be standardized voltage such as 5V, 0V, 5V, and 5V. In such examples, the difference between each voltage value may be larger than the switching voltage of the memristor. For example, the minimum difference between the voltage values provided in the above example is 5V, which may be larger than the switching voltage of the memristor.

[0020] Processor 1 10 may assign a column voltage value to at least one of the plurality of column lines. The column voltage may correspond to the second code, which for purposes of illustration may be the code to be compared with the key code of the first code. A digital code string may be assigned to the columns as two separate voltage values. For example, a column line corresponding to a digital "0" may be assigned a first column voltage, while a column line corresponding to a digital "1 " may be assigned a second row voltage. In some examples, the first column voltage may be below the switching voltage of the memristor, and the second column voltage may be above the switching voltage. Similarly in some examples, the second code may be an analog code.

[0021 ] In response to the row lines and column lines having been assigned voltage values according to the first code and the second code, respectively, processor 1 10 may cause a voltage to be applied to each line that is assigned a value. Specifically, processor 1 10 may cause a row voltage to be applied to each row according to the row voltage values assigned. Similarly, processor 1 10 may cause a column voltage to be applied to each column according to the column voltage values assigned.

[0022] When the row voltage value of a row line matches the column voltage value of the corresponding column line, the memristors will have no or minimum total voltage across it due to equipotential. Accordingly, the memristor will not be switched because the total voltage across it is below its switching voltage. However, if the voltages do not match, then the memristor may be switched. For example, if a row voltage of a memristor is 0V and the column voltage of the same memristor is 5V, the memristor will be switched. In such examples, a unipolar or nonpolar memristors may be used to allow switching regardless of the polarity of the voltage. A memristor being switched may indicate a mismatch between a bit of the first code and the corresponding bit of the second code.

[0023] To compare the two codes, processor 1 10 may compare the first code with the second code based on the states of the memristors of memristor array 120. For example, a state change of one or more memristors of the array 120 may indicate a code mismatch because the total current through memristor array 120 is changed from the total current through the array before the memristor state switch. In some implementations, processor 120 is to cause a read voltage to be applied across memristor array 120 to determine the total current across the array resulting from the applied read voltage.

[0024] In some examples, processor 1 10 may cause a reset voltage to be applied to one or both of the plurality of row lines and the plurality of column lines. Application of the reset voltage may cause all of the memristors in the memristor array 120 to be in a common resistance state. In such examples, memristors of the memristor array 120 are recoverable and may be used multiple times for comparing codes.

[0025] In some other examples, the memristors of memristor array 120 are not resettable. For example, memristor in such instances may only be switched one time, and its resistance state may not be reset. This may provide further security features to the code comparator 100. For example, code comparator 100 may prevent brute force forgery attack, which may be useful in such high security applications, such as one time digital keys.

[0026] In some examples, processor 1 10 may implement the memristor array 120 as an accelerator to accelerate comparing the first code with the second code. That is, the processor 100 may implement the memristor array 120 to compare the codes in a manner that is relatively faster and more efficient than if the processor 1 10 itself was to compare the codes itself. In this regard, the memristor array 120 may be implemented as an accelerator of the processor 1 10, in which the memristor array 120 is implemented solely in the comparing of the first code and the second code.

[0027] Although not shown in FIG. 1A, the code comparator 100 may include a memory, which may be, for instance, a volatile or non-volatile memory, such as dynamic random access memory (DRAM), electrically erasable programmable read-only memory (EEPROM), magnetoresistive random access memory (MRAM), or the like. In this example, the machine readable instructions, for instance, corresponding to the operations disclosed herein, may be stored in the memory. According to an example, the memory (not shown) is a second memristor array on which the processor is to store data. In this example, the memristor array 120, which may operate solely as an accelerator, may be fabricated with the second memristor array, which may operate as a memory for the processor 120.

[0028] FIG. 1 B depicts an example memristor array 150. Memristor array 150 may be a configuration of parallel and perpendicular lines with memristors and other components coupled between lines at cross-points. Memristor array 150 may include a plurality of row lines 160, a plurality of column lines 170, and a plurality of memristors 180. Each memristor may be coupled between a unique combination of one row line and one column line. In other words, no memristor share both a row line and a column line. Memristor array 150 may be used in a variety of applications, including in code comparators disclosed herein, such as code comparator 100 of FIG. 1A.

[0029] Row lines 160 may be electrically conducting lines that carry current throughout memristor array 150. In some examples, row lines 160 may be in parallel to each other, generally with equal spacing. Row lines 160 may sometimes be referred to as bit lines. Depending on orientation, row lines 160 may alternatively be referred to as word lines. Similarly, column lines 170 may be conducting lines that run nonparallel to row lines 160. Column lines 170 may be referred to as word lines in some conventions. In other orientations, column lines 170 may refer to bit lines. Row lines 160 and column lines 170 may be made of conducting materials, such as platinum (Pt), tantalum (Ta), hafnium (Hf), zirconium (Zr), aluminum (Al), cobalt (Co), nickel (Ni), iron (Fe), niobium (Nb), molybdenum (Mo), tungsten (W), copper (Cu), titanium (Ti), tantalum nitrides (TaN_x), titanium nitrides (TiN_x), WN₂, NbN, MoN, TiSi₂, TiSi, Ti₅Si₃, TaSi₂, WSi₂, NbSi₂, V₃Si, electrically doped Si polycrystalline, electrically doped Ge polycrystalline, and combinations thereof. Row lines 160 and column lines 170 may serve as electrodes that deliver voltage and current to the memory cells 330.

[0030] Memristors 180 may be coupled between row lines 160 and column lines 170. In some implementations, a memristor 180 may have a resistance that changes with an applied voltage or current. Furthermore, memristor 180 may "memorize" its last resistance. In this manner, each memristor 180 may be set to at least two states. Furthermore in some examples, other components may be coupled with memristors 180. For example, each memristor may be coupled in series with a transistor and/or a selector. [0031 ] FIG. 2 depicts an example code comparator 200. It should be understood that the code comparator 200 depicted in FIG. 2 may include additional components and that some of the components described herein may be removed and/or modified without departing from a scope of the code comparator 200.

[0032] As shown in FIG. 2, code comparator 200 may include similar features as code comparator 100 depicted in FIG. 1A. Particularly, the code comparator 200 may include a processor 210 and a memristor array 220. The code comparator 200 is also depicted as including a voltage source 230 and a current reader 240 connected to the processor 1 10. In some examples, processor 210, memristor 220, voltage source 230, and current reader 240 may be provided and connected on a substrate.

[0033] As also shown, the memristor array 220 may have a diagonal cross-bar architecture, which includes a plurality of row lines 222a-222n and a plurality column lines 224a-224n. The variable "n" may represent an integer value greater than one. Each of the row lines 222a-222n and the column lines 224a-224n may be an electrically conductive wire, an electrode, or the like.

[0034] The memristor array 220 is also depicted as having a plurality of memristors 226 electrically connected to pairs of row lines 222a-222n and column lines 224a-224n. That is, a first memristor 226 is depicted as being electrically connected to the first row line 222a and the first column line 224a, a second memristor 226 is depicted as being electrically connected to the second row line 222b and the second column line 224b, and an nth memristor 226 is depicted as being electrically connected to the nth row line 222n and the nth column line 224n. In some examples, memristors 226 may be provided at each of the junctions of the row lines 222a-222n and the column lines 224a-224n. In other examples, the memristor array 220 includes the memristors 226 as depicted in FIG. 2.

[0035] The voltage source 230, which may be connected to a power supply (not shown), is also depicted as being connected to each of the row lines 222a-222n and the column lines 224a-224n. The connections between the voltage source 230 and the row inputs 222a-222n and the column inputs 224a-224n are shown as dotted lines to distinguish those lines from the row lines 222a-222n and the column lines 224a-224n. Processor 210 may control or otherwise cause the voltage source 230 to apply voltages at multiple levels to row lines 222a-222n and column lines 224a-224n. The multiple levels of voltages may include a resetting voltage, a read voltage, a voltage according to a row voltage value, and a voltage according to a column voltage value.

[0036] The processor 210 may control the voltage source 230 to supply different levels of voltages to row lines 222a-222n and column lines 224a-224n based upon the row voltage values and the column voltage values, respectively. The row voltage values in turn are based on a first code, and the column voltage values are based on a second code.

[0037] In some examples, each of the memristors 226 may be a unipolar memristor. That is, switching of the memristors 226 may depend on the amplitude of an applied voltage. In addition, the resistance states of the unipolar memristors 226 may be set and reset at the same polarity of the applied voltage. Moreover, states of the memristors 226 may be changed when there is a difference in potential across the memristors 226. That is, if the same voltage is applied to the first row line 222a and the first column line 224a, there will be an equal potential across the memristor 226 that is connected to the first row line 222a and the first column line 222b and thus, no electrical field will be generated across the memristor 226. In this instance, the state of the memristor 226 will not be changed. However, if a first voltage is applied to the first row line 222a and a second voltage is applied to the first column line 224a, there will be a difference in potential across the memristor 226, and thus, the state of the memristor 226 may be changed.

[0038] As discussed above, the different states of the memristors 226 correspond to different resistances in the memristors 226. That is, a memristor 226 in one state may have a different resistance as compared with a memristor 226 in another state. The states of the memristors 226 may thus affect the total current across the memristor array 220. Following application of the row voltages and column voltages through the memristor array 220 to compare the first code and the second code, processor 210 may cause voltage source 230 to apply a read voltage across memristor array 220. As the read voltage is applied, current reader 240 may determine the total current across the memristors 226 resulting from the applied read voltage.

[0039] Processor 120 may compare the first code with the second code based upon the determined total current. For example, of the total current across memristor array 220 is different than the total current across the array before the code comparison operations, then one of the memristors 226 may have been switched, indicating a code mismatch. In such a manner, the first code may be compared with the second code.

[0040] FIG. 3 depicts an example system 300 for comparing a first code with a second code. System 300 may be, for example, a IC, a hardware accelerator, a cloud server, a local area network server, a web server, a mainframe, a mobile computing device, a notebook or desktop computer, any other suitable electronic device, or a combination of devices, such as ones connected by a cloud or internet network, that perform the functions described herein. In the example shown in FIG. 3, system 300 includes a processor 310, a non-transitory machine-readable storage medium 320 encoded with instructions to compare codes, and a memristor array 330.

[0041 ] Processor 310 may be one or more central processing units (CPUs), semiconductor-based microprocessors, and/or other hardware devices suitable for retrieval and execution of instructions stored in machine-readable storage medium 320. Processor 310 may fetch, decode, and execute instructions 321 , 322, 323, 324, 325, 326, and 327 to implement the procedures described herein. As an alternative or in addition to retrieving and executing instructions, processor 310 may include one or more electronic circuits that include electronic components for performing the functionality of one or more of instructions 321 , 322, 323, 324, 325, 326, and 327.

[0042] Memristor array 330 may be analogous to memristor array 120 of FIG. 1A, and may be a configuration of sets of parallel crossing lines with memristors coupled between intersections of lines. Memristors may be switched between resistance states and may be bipolar or unipolar.

[0043] Machine-readable storage medium 320 may be any electronic, magnetic, optical, or other physical storage device that contains or stores executable instructions. Thus, machine-readable storage medium 320 may be, for example, Random Access Memory (RAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a storage device, an optical disc, and the like. Storage medium 320 may be a non-transitory storage medium, where the term "non-transitory" does not encompass transitory propagating signals. As described in detail below, machine-readable storage medium 320 may be encoded with row voltage value instructions 321 , column voltage value instructions 322, row line voltage instructions 323, column line voltage instructions 324, read voltage instruction 325, code comparison instructions 326, and reset voltage instructions 327.

[0044] Machine-readable storage medium 320 may include row voltage value instructions 321 . Row voltage value instructions 321 may assign a row voltage value to at least one of the plurality of row lines. The row voltage value may correspond to the first code.

[0045] Machine-readable storage medium 320 may include column voltage value instructions 322. Column voltage value instructions 322 may assign a column voltage value to at least one of the plurality of column lines. The column voltage value may correspond to the second code.

[0046] Machine-readable storage medium 320 may include row line voltage instructions 323. Row line voltage instructions 323 may cause a voltage to be applied to each row line that is assigned a value. Specifically, Row line voltage instructions 323 may cause a row voltage to be applied to each row according to the row voltage values assigned by row voltage value instructions 321 .

[0047] Machine-readable storage medium 320 may include column line voltage instructions 324. Column line voltage instructions 324 may cause a voltage to be applied to each column line that is assigned a value. Specifically, Column line voltage instructions 324 may cause a column voltage to be applied to each column according to the column voltage values assigned by column voltage value instructions 322.

[0048] Machine-readable storage medium 320 may include read voltage instructions 325. Read voltage instructions 325 cause a read voltage to be applied across memristor array 330 to determine the total current across the array resulting from the applied read voltage.

[0049] Machine-readable storage medium 320 may also include code comparison instructions 326. For example, a state change of one or more memristors of the array 330 may indicate a code mismatch because the total current through memristor array 330 is changed from before the memristor state switch. Code comparison instructions 326 may compare the first code with the second code based on the total current across memristor array 330.

[0050] Machine-readable storage medium 320 may also include reset voltage instructions 327. Reset voltage instructions 327 may cause a reset voltage to be applied to one or both of the plurality of row lines and the plurality of column lines. Application of the reset voltage may cause all of the memristors in the memristor array 330 to be in a common resistance state.

[0051 ] FIG. 4 depicts an example method 400 for comparing a first code with a second code. Although execution of method 400 is described below with reference to code comparator 100 of FIG. 1A, other suitable components for execution of method 500 should be apparent.

[0052] In an operation 410, processor 1 10 may cause a reset voltage to be applied to one or both of the plurality of row lines and the plurality of column lines of memristor array 120. Application of the reset voltage may cause all of the memristors in the memristor array 120 to be in a common resistance state.

[0053] In an operation 420, processor 1 10 may assign a row voltage value to at least one of the plurality of row lines. The row voltage value may correspond to the first code.

[0054] In an operation 430, processor 1 10 may assign a column voltage value to at least one of the plurality of column lines. The row column value may correspond to the second code.

[0055] In an operation 440, processor 1 10 may cause a voltage to be applied to each row line that is assigned a value. Specifically, processor 1 10 may cause a row voltage to be applied to each row according to the row voltage values assigned in operation 420.

[0056] In an operation 450, processor 1 10 may cause a voltage to be applied to each column line that is assigned a value. Specifically, processor 1 10 may cause a column voltage to be applied to each column according to the column voltage values assigned in operation 430. [0057] Operation 440 and operation 450 may be operated simultaneously. In other words, processor 1 10 may simultaneously cause the row voltages to be applied to the row lines and the column voltages to be applied to the column lines. When the voltages are applied simultaneously, voltages of the same value may result in no net voltage due to equipotential. If the voltages are not applied simultaneously, one or more memristors may be erroneously switched.

[0058] In an operation 460, processor 1 10 may cause a read voltage to be applied across memristor array 120 to determine the total current across the array resulting from the read voltage applied.

[0059] In an operation 470, processor 1 10 may compare the first code with the second code based on the total current across memristor array 330.

Claims

CLAIMS What is claimed is:

1 . A code comparator, comprising:

a first memristor array comprising a plurality of row lines, a plurality of column lines, and a plurality of memristors, wherein each of the memristors is coupled between a unique combination of a row line and a column line; and

a processor to:

assign a row voltage value to at least one of the plurality of row lines, wherein the row voltage value corresponds to a first code;

assign a column voltage value to at least one of the plurality of column lines, wherein the column voltage value corresponds to a second code;

cause a voltage to be applied to each row line that is assigned a row voltage value according to the row voltage values;

cause a voltage to be applied to each column line that is assigned a column voltage value according to the column voltage values, wherein the state of the memristor is changed when the voltage applied to a particular row line differs from the voltage applied to the connected column line; and

compare the first code with the second code based on the states of the memristors.

2. The code comparator of claim 1 , wherein the plurality of memristors comprises unipolar switching memristors arranged in a diagonal crossbar architecture.

3. The code comparator of claim 2, wherein the plurality of memristors comprises nonpolar switching memristors.

4. The code comparator of claim 1 , wherein the processor is to cause a read voltage to be applied across the plurality of memristors to determine a total current across the plurality of memristors resulting from the applied read voltage.

5. The code comparator of claim 1 , wherein the memristors of the plurality of memristors have sufficiently high current compliances to enable states of the memristors to be switched.

6. The code comparator of claim 1 , wherein the processor is further to cause a reset voltage to be applied to one or both of the plurality of row lines and the plurality of column lines, wherein application of the reset voltage is to cause all of memristors to be in a common resistance state.

7. The code comparator of claim 1 , wherein the memristors of the plurality of memristors are not resettable.

8. The code comparator of claim 1 , further comprising a second memristor array, wherein the first memristor array functions as an accelerator for the processor to accelerate code comparisons and wherein the processor is to store data in the second memristor array.

9. A method for comparing a first code with a second code, comprising:

assigning a row voltage value to at least one of a plurality of row lines of a memristor array, wherein the row voltage value corresponds to a first code and wherein the memristor array comprises the plurality of row lines, a plurality of column lines, and a plurality of memristors, wherein each of the memristors is coupled between a unique combination of a row line and a column line;

assigning a column voltage value to at least one of the plurality of column lines, wherein the column voltage value corresponds to a second code;

causing a voltage to be applied to each row line that is assigned a row voltage value according to the row voltage values;

causing a voltage to be applied to each column line that is assigned a column voltage value according to the column voltage values, wherein the state of the memristor is changed when the voltage applied to a particular row line differs from the voltage applied to the connected column line; and

causing a read voltage to be applied across the plurality of memristors to determine a total current across the plurality of memristors resulting from the applied read voltage.

10. The method of claim 9, further comprising comparing the first code with the second code based on the total current across the plurality of memristors resulting from the applied read voltage.

1 1 . The method of claim 9, further comprising causing a reset voltage to be applied to one or both of the plurality of row lines and the plurality of column lines, wherein application of the reset voltage is to cause all of memristors to be in a common resistance state.

12. The method of claim 9, wherein the memristors of the plurality of memristors are not resettable.

13. A system for comparing a first code with a second code, comprising:

a processor to:

cause a voltage to be applied to each column line that is assigned a column voltage value according to the column voltage values, wherein the state of the memristor is changed when the voltage applied to a particular row line differs from the voltage applied to the connected column line;

cause a read voltage to be applied across the plurality of memristors to determine a total current across the plurality of memristors resulting from the applied read voltage; and

compare the first code with the second code based on the total current across the plurality of memristors resulting from the applied read voltage.

14. The system of claim 14, wherein the processor is further to cause a reset voltage to be applied to one or both of the plurality of row lines and the plurality of column lines, wherein application of the reset voltage is to cause all of memristors to be in a common resistance state.

15. The system of claim 14, wherein the memristors of the plurality of memristors are not resettable.