CN103811491B - A kind of tabilized current power supply integrated chip and manufacture method - Google Patents
A kind of tabilized current power supply integrated chip and manufacture method Download PDFInfo
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- CN103811491B CN103811491B CN201410064490.1A CN201410064490A CN103811491B CN 103811491 B CN103811491 B CN 103811491B CN 201410064490 A CN201410064490 A CN 201410064490A CN 103811491 B CN103811491 B CN 103811491B
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Abstract
The present invention relates to a kind of tabilized current power supply integrated chip and manufacture method, it comprises as N
-the monocrystalline silicon N of doped region
-type polished silicon wafer, at described N
-the back side of doped region is provided with N
+heavily doped region, at described N
-the front of doped region is provided with triode Q2, current regulator diode CRD, triode Q1 and resistance R, the N of described resistance R
+one end of doped region and the N of triode Q2
+doped region is connected, simultaneously as the negative electrode of constant-current source integrated chip, the other end respectively with the N of triode Q1
+the P doped region of doped region, triode Q2 is connected; The P doped region of described triode Q1 is connected with the P doped region of current regulator diode CRD, the P doped region of triode Q2, the N doped region of triode Q2 respectively; The N doped region of described current regulator diode CRD respectively with P doped region, the 2nd N of current regulator diode CRD
+doped region is connected; Described N
+heavily doped region is as the anode of constant-current source integrated chip.
Description
Technical field
The present invention relates to a kind of integrated chip, particularly a kind of tabilized current power supply integrated chip and manufacture method.Belong to integrated chip technology field.
Background technology
Constant-current source is the power supply that can provide constant current to load, is widely used in electronic circuit, particularly the rise of LED illumination in recent years, and its constant current drive scheme has promoted low cost, the development of highly reliable constant-current source device especially.Mainly form the difference of device at present according to constant-current source circuit, can be divided three classes: transistor constant current source (see Figure 14), technotron constant-current source (see Figure 15), integrated operational amplifier constant current source.Three kinds of schemes have pluses and minuses different separately, and transistor constant current source continuous current is adjustable, but dynamic electric resistor is relatively little, constant current poor-performing; Field effect constant current tube constant current better performances, but chip area utilance low (continuous current size and chip area ratio), continuous current is non-adjustable, chip yield low (requiring higher to the technological level of manufacturing process); Although integrated operational amplifier constant current source better performances, manufacturing process is complicated, and cost is higher, and transistor constant current source and integrated operational amplifier constant current source are generally the circuit that independent entry device forms, and reliability is relatively low.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, a kind of tabilized current power supply integrated chip and manufacture method are provided, improve constant current performance, realize the Serial regulation of continuous current size, manufacturing process is relatively simple simultaneously, and be all integrated on one piece of chip because of each assembly, therefore achieve high reliability, low cost.
The object of the present invention is achieved like this: a kind of tabilized current power supply integrated chip, it comprises as N
-the silicon substrate monocrystalline N of doped region
-type polished silicon wafer; At described N
-the back side of doped region is provided with N
+heavily doped region; At described N
-the front of doped region is provided with a P of triode Q2
-2nd P of doped region and current regulator diode CRD
-doped region; At a described P
-to adulterate in doped region formation the one N doped region, at described 2nd P
-the 2nd N doped region is stated in formation of adulterating in doped region; A described N doped region forms a P doped region, at a P
-doped region forms the 2nd P doped region, at described 2nd P
-doped region forms the 3rd P doped region and the 4th P doped region, at the N of silicon substrate
-doped region is formed respectively the 5th P doped region of triode Q1 and the 6th P doped region of resistance R; A described P doped region forms a N
+doped region, at the N of silicon substrate
-doped region forms the 2nd N
+doped region, the 5th P doped region forms the 3rd N
+doped region, the 6th P doped region of resistance R forms the 4th N
+doped region; 4th N of described resistance R
+one end of doped region and a N
+doped region is connected, simultaneously as the negative electrode of constant-current source integrated chip; Described 4th N
+the other end of doped region respectively with the 3rd N
+doped region, a P doped region are connected; Described 5th P doped region is connected with the 4th P doped region, the 2nd P doped region, a N doped region respectively; Described 2nd N doped region respectively with the 3rd P doped region, the 2nd N
+doped region is connected; Described N
+heavily doped region is as the anode of constant-current source integrated chip.
Exchange doping type N, P type of doped region, namely N-type becomes P type, and P type becomes N-type, and described silicon substrate front is anode, and the back side is negative electrode.
At described resistance R front SiO
2film is provided with a polysilicon strip, makes polysilicon strip form resistance R, adopt polysilicon resistance can regulate the temperature characterisitic of its resistance easily.
A manufacture method for above-mentioned tabilized current power supply integrated chip, said method comprising the steps of:
Step one, get a slice monocrystalline silicon N
-type polished silicon wafer, as N
-doped region silicon substrate;
Step 2, at N
-the back side heavy doping of doped region silicon substrate forms N
+heavily doped region;
Step 3, at N
-the synchronous P forming triode Q2 on doped region
-2nd P of doped region and current regulator diode CRD
-doped region;
Step 4, a P at triode Q2
-to adulterate in doped region formation the one N doped region, at the 2nd P of current regulator diode CRD
-to adulterate in doped region formation the 2nd N doped region;
Step 5, on a N doped region of triode Q2 formed a P doped region, at a P
-doped region forms the 2nd P doped region; At the 2nd P of current regulator diode CRD
-doped region forms the 3rd P doped region and the 4th P doped region, at the N of silicon substrate
-doped region is formed respectively the 5th P doped region of triode Q1 and the 6th P doped region of resistance R;
Step 6, on a P doped region of triode Q2 formed a N
+doped region, at the N of silicon substrate
-doped region forms the 2nd N
+doped region; The 5th P doped region of triode Q1 forms the 3rd N
+doped region; The 6th P doped region of resistance R forms the 4th N
+doped region;
Step 7, in a N doped region, the 2nd N doped region, a P doped region, the 2nd P doped region, the 3rd P doped region, the 4th P doped region, the 5th P doped region, a N
+doped region, the 2nd N
+doped region, the 3rd N
+the SiO of doped region
2on etch fairlead window, at the 4th N of resistance R
+the SiO of doped region
2on etch two ports of two fairlead windows as resistance R, the 4th N of resistance R
+one of them fairlead of doped region and a N of triode Q2
+doped region is connected, simultaneously as the negative electrode of constant-current source integrated chip; 4th N of resistance R
+another fairlead of doped region and the 3rd N of triode Q1
+the one P doped region of doped region, triode Q2 is connected; The 5th P doped region of triode Q1 is connected with the 2nd P doped region of the 4th P doped region of current regulator diode CRD, triode Q2, a N doped region of triode Q2; The 2nd N doped region of current regulator diode CRD and the 3rd P doped region of current regulator diode CRD, the 2nd N
+doped region is connected; N
-the back side N of doped region silicon substrate
+heavily doped region is as the anode of constant-current source integrated chip.
A step is added, at the SiO in described resistance R front between step 6 and step 7
2deposit one deck polysilicon membrane on film also adulterates, then etching forms the polysilicon strip needed, and then deposit one deck SiO
2film, as the insulating medium layer between polysilicon and lower single metal line, finally makes polysilicon strip form resistance R, adopts polysilicon resistance can regulate the temperature characterisitic of its resistance easily.
Compared with prior art, the present invention has following beneficial effect:
In circuit design:
1, conventional transistor constant current source, its triode Q1 base drive adopts resistance drive scheme, due to the linear relationship of resistor current and voltage, make the voltage clamping poor effect on continuous current adjusting resistance R1, make constant-current characteristics poor, the resistor current on the base drive resistance R2 of another aspect triode Q1 further makes constant-current characteristics be deteriorated; And in the present invention, the current regulator diode CRD that triode Q1 base drive have employed electric current less drives, because the electric current of current regulator diode own immobilizes, therefore the voltage clamping effect on current adjustment resistor R1 is better, the continuous current of current regulator diode self also can not have a negative impact to total constant current dynamic electric resistor, therefore the circuit arrangement that the present invention adopts has larger constant current dynamic electric resistor, and constant-current characteristics is better.
2, continuous current size of the present invention is determined by the resistance size of resistance R substantially, therefore by adjusting the size adjustment continuous current size of resistance, and change resistance size by the mode that outer meeting resistance is in parallel with resistance R, thus the Serial regulation realized continuous current size, this is the ability not available for conventional junction field current regulator diode.
On integrated technique:
1, current regulator diode CRD have employed junction field structure, and on process structure with bipolarity triode process compatible, greatly simplify technical process, and by reduce P
-its operating voltage of the surface dopant concentration of doped region, and then improve voltage power supply scope of the present invention;
2, the design of whole chip is all the N at same silicon substrate
-doped region is formed, and processing step is simple, and less demanding to the working ability of manufacturing process, 4,5 inch silicon production-line technique abilities can meet batch production requirements;
3, from constant-current source circuit principle of the present invention, the continuous current of current regulator diode CRD is only greater than the base current of triode Q1, and circuit can normally work, as long as the h of therefore triode Q1
fEenough large, the chip area of current regulator diode CRD can be less.And the junction field tubular construction current regulator diode of routine, due to preferably continuous current temperature coefficient will be obtained, the thickness of raceway groove can not be excessive, under identical continuous current, junction field tubular construction current regulative diode chip area is much larger than chip area of the present invention, and actual flow experimental data is more than two or three times.And the ability of continuous current size of the present invention determines primarily of triode Q1, constant current temperature coefficient is that the emitter of negative temperature coefficient and triode Q2 and the negative temperature coefficient of base stage forward conduction voltage match by adjusting resistance R1, thus reduces constant current temperature coefficient.Therefore the present invention is much smaller than conventional junction field current regulator diode on chip area, greatly reduces chip cost;
4, the present invention can directly adopt silicon single-crystal polishing plate to process, significantly lower than the field effect current regulator diode structure (silicon epitaxial material price is generally 2 ~ 3 times of silicon single-crystal polishing plate) adopting epitaxy technique to manufacture on silicon sheet material cost;
5, the continuous current size of conventional junction field current regulator diode is controlled by channel thickness, and channel thickness is seriously limited by epitaxy layer thickness uniformity, grid region junction depth uniformity, require very high to the technological ability manufactured, under the technological level of the silicon production line of 4,5 inch, rate of finished products is general less than 60%, and continuous current size of the present invention is determined by the resistance size of resistance R substantially, technology controlling and process is comparatively simple, and under identical manufacturing technology level, rate of finished products easily can reach more than 90%.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of tabilized current power supply integrated chip that in the present invention, embodiment one relates to.
Fig. 2 ~ Fig. 8 is the manufacturing process flow diagram of a kind of tabilized current power supply integrated chip that in the present invention, embodiment one relates to.
Fig. 9 is the application schematic diagram of a kind of tabilized current power supply integrated chip that in the present invention, embodiment one relates to.
Figure 10 is the structural representation of a kind of tabilized current power supply integrated chip that in the present invention, embodiment two relates to.
Figure 11 ~ Figure 12 is the manufacturing process flow diagram of a kind of tabilized current power supply integrated chip that in the present invention, embodiment three relates to.
Figure 13 is the circuit theory diagrams of a kind of tabilized current power supply integrated chip of the present invention.
Figure 14 is typical transistors constant-current source circuit schematic diagram.
Figure 15 is typical junction field constant-current source sectional structure chart.
Wherein:
N
-doped region 1
N
+heavily doped region 2
One P
-doped region 3
2nd P
-doped region 4
One N doped region 5
2nd N doped region 6
One P doped region 7
2nd P doped region 8
3rd P doped region 9
4th P doped region 10
5th P doped region 11
6th P doped region 12
One N
+doped region 13
2nd N
+doped region 14
3rd N
+doped region 15
4th N
+doped region 16
Polysilicon strip 17.
Embodiment
The tabilized current power supply integrated chip proposed the present invention below in conjunction with concrete example and manufacture method thereof are described in further detail.And it should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses the ratio of non-precision, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Embodiment one:
See Fig. 1, the present invention relates to a kind of tabilized current power supply integrated chip, it comprises as N
-the monocrystalline silicon N of doped region 1
-type polished silicon wafer; At described N
-the back side of doped region 1 is provided with N
+heavily doped region 2; At described N
-the front of doped region 1 is provided with a P of triode Q2
-2nd P of doped region 3 and current regulator diode CRD
-doped region 4; At a described P
-to adulterate in doped region 3 formation the one N doped region 5, at described 2nd P
-the 2nd N doped region 6 is stated in formation of adulterating in doped region 4; A described N doped region 5 forms a P doped region 7, at a P
-doped region 3 forms the 2nd P doped region 8, at described 2nd P
-doped region 4 forms the 3rd P doped region 9 and the 4th P doped region 10, at the N of silicon substrate
-doped region 1 is formed respectively the 5th P doped region 11 of triode Q1 and the 6th P doped region 12 of resistance R; A described P doped region 7 forms a N
+doped region 13, at the N of silicon substrate
-doped region 1 forms the 2nd N
+doped region 14, the 5th P doped region 11 forms the 3rd N
+doped region 15, the 6th P doped region 12 of resistance R forms the 4th N
+doped region 16; 4th N of described resistance R
+one end of doped region 16 and a N
+doped region 13 is connected, simultaneously as the negative electrode of constant-current source integrated chip; Described 4th N
+the other end of doped region 16 respectively with the 3rd N
+doped region 15, a P doped region 7 are connected; Described 5th P doped region 11 is connected with the 4th P doped region 10, the 2nd P doped region 8, a N doped region 5 respectively; Described 2nd N doped region 6 respectively with the 3rd P doped region 9, the 2nd N
+doped region 14 is connected; Described N
+heavily doped region 2 is as the anode of constant-current source integrated chip.
The present invention relates to a kind of manufacture method of constant-current source integrated chip, described method comprises the steps:
Step one, as shown in Figure 2, get one piece of monocrystalline silicon N
-type polished silicon wafer, forms the N of silicon substrate
-doped region 1, by N
-doped region 1 silicon substrate is placed in oxidation boiler tube, is the SiO of 0.5 μm ~ 1.5 μm at front (burnishing surface) growth thickness
2protective layer;
Step 2, as shown in Figure 3, adopts the mode injecting phosphorus or phosphorus oxychloride pre-deposited at N
-the silicon substrate back side, doped region 1 forms phosphorus pre-doping layer, i.e. N
+heavily doped region 2, then carries out dopant redistribution diffusion in diffusion furnace tube, requires that distribution diffusion rear surface doping content is at 1E18/cm again
3above, be beneficial to electrode metal and silicon forms ohmic contact, then spread junction depth and determine according to back side metallization technology, as long as usually just can meet the demands more than 5 μm, need to ensure the N after spreading again simultaneously
-layer thickness is more than 20 μm, so that the formation of front side of silicon wafer structure;
Step 3, as shown in Figure 4, at N
-the SiO in silicon substrate front, doped region 1
2on etch a P
-doped region 3 and the 2nd P
-the doping window of doped region 4, the mode injecting boron is adopted to adulterate, implantation dosage is at 5E12 ~ 1E14, then in diffusion furnace tube, dopant redistribution diffusion is carried out, junction depth controls between 5 ~ 20 μm, doping content and junction depth mainly require to determine according to the puncture voltage of CRD, then the SiO of synchronous growth about 0.5 μm in the process of the diffusion that distributes
2, as the masking layer of lower step impurity doping;
Step 4, as shown in Figure 5, at a P of triode Q2
-the SiO of doped region 3
2on etch the doping window of a N doped region 5; At the 2nd P of current regulator diode CRD
-the SiO of doped region 4
2on etch the doping window of the 2nd N doped region 6, then adopt the mode injecting phosphorus to adulterate, implantation dosage, at 1E14 ~ 2E15, then carries out dopant redistribution diffusion in diffusion furnace tube, and junction depth finally controls to make N doped region and P
-the junction depth difference of both doped regions is between 1 ~ 5 μm, and the continuous current size of concrete Main Basis current regulator diode CRD controls, the SiO of synchronous growth about 0.5 μm in the process of diffusion that distributes again
2, as the masking layer of lower step impurity doping;
Step 5, as shown in Figure 6, at the SiO of a N doped region 5 of triode Q2
2on etch the doping window of a P doped region 7, at a P of triode Q2
-the SiO of doped region
2on etch the doping window of the 2nd P doped region 8, at the 2nd P of current regulator diode CRD
-the SiO of doped region 4
2on etch the doping window of the 3rd P doped region 9 and the 4th P doped region 10; At N
-the SiO of doped region 1 silicon substrate
2on etch the 5th P doped region 11 of triode Q1 and the doping window of the 6th P doped region 12 of resistance R; Then adopt the mode injecting boron to carry out impurity pre-doping, implantation dosage can between 1E14 ~ 3E15; Then in diffusion furnace tube, family carries out dopant redistribution diffusion, and junction depth finally controls to make the junction depth difference of the P doped region of triode Q2 and a N doped region between 2 ~ 5 μm, then the SiO of synchronous growth about 0.5 μm in the process of the diffusion that distributes
2, as the masking layer of lower step impurity doping;
Step 6, as shown in Figure 7, at the oxide layer SiO of a P doped region 7 of triode Q2
2on etch a N
+the doping window of doped region 13, at N
-the SiO of doped region 1 silicon substrate
2on etch at the 2nd N
+the doping window of doped region 14, at the SiO of the 5th P doped region 711 of triode Q1
2on etch the 3rd N
+the doping window of doped region 15, at the SiO of the 6th P doped region 12 of resistance R
2on etch the 4th N
+the doping window of doped region 16; Then adopt the mode injecting phosphorus to carry out impurity pre-doping, implantation dosage can between 5E15 ~ 2E16, and then in diffusion furnace tube, family carries out dopant redistribution diffusion, and junction depth finally controls the h making triode Q1, triode Q2
fEbetween 100 ~ 500, then the SiO of synchronous growth about 0.5 μm in the process of the diffusion that distributes
2, described SiO
2film is as the insulating medium layer of lower single metal line;
Step 7, as shown in Figure 8, in a N doped region 5, the 2nd N doped region 6, a P doped region 7, the 2nd P doped region 8, the 3rd P doped region 9, the 4th P doped region 10, the 5th P doped region 11, a N
+doped region 13, the 2nd N
+doped region 14, the 3rd N
+the SiO of doped region 15
2above etch fairlead window respectively, at the 4th N of resistance R
+the SiO of doped region 16
2on etch two ports of two fairlead windows as resistance R, then adopt electron beam evaporation Al or sputtering Al mode depositing metal Al, last chemical wet etching metal A l forms the metal connecting line of each assembly, and concrete annexation is: the 4th N of resistance R
+one of them fairlead of doped region 16 and a N of triode Q2
+doped region 13 is connected, simultaneously as the negative electrode of constant-current source integrated chip; 4th N of resistance R
+another fairlead of doped region 16 and the 3rd N of triode Q1
+the one P doped region 7 of doped region 15, triode Q2 is connected; The 5th P doped region 11 of triode Q1 is connected with the 2nd P doped region 8 of the 4th P doped region 10 of current regulator diode CRD, triode Q2, a N doped region 5 of triode Q2; The 2nd N doped region 6 of current regulator diode CRD and the 2nd P doped region 9 of current regulator diode CRD, the 2nd N
+doped region 14 is connected; N
-the back side N of doped region 1 silicon substrate
+heavily doped region 2 finally adopts the mode deposit backplate metal of electron beam evaporation or sputtering, as titanium, nickel, silver etc. adopt multi-layer metal structure as the anode of constant-current source integrated chip.So far, the chip manufacturing proces of the present embodiment one constant-current source integrated chip terminates.
Be illustrated in figure 9 the present invention's typical chip plane layout application schematic diagram.For the present invention, independent package lead pin can be carried out to the two end electrodes of resistance R after chip package, at outside outer meeting resistance, be formed in parallel with resistance R in logic, thus by adjusting the size of outer meeting resistance, realize the linear regulation of constant-current source integrated chip continuous current.
Embodiment two, as shown in Figure 10, the difference of the present embodiment and embodiment one is, doped region doping type N, P type is exchanged, namely N-type becomes P type, and P type becomes N-type, still identical in structure, the function of final realization is also identical, just corresponding polarity of electrode is contrary, and namely the front of silicon substrate is anode, and the back side is negative electrode.Corresponding to manufacture method, be also only that impurity type and embodiment one are exchanged, technological requirement is identical.
The main distinction of embodiment three, this example and example one and example two is, to assembly resistance R employing is wherein polysilicon resistance, and example one and example three adopt is silicon N trap or P trap resistance, adopt polysilicon resistance, the temperature characterisitic of its resistance can be regulated easily, thus the satisfactory constant-current source constant current temperature characterisitic of final acquisition.This kind of situation ought to be the equivalent feature of the claims in the present invention.Corresponding to manufacture method, this example is identical with the front step one ~ step 6 of example one, and difference is:
Step 7, as shown in figure 11, at the front SiO of silicon substrate
2the polysilicon membrane of upper employing chemical vapor deposition mode deposit one deck 0.6 μm of thickness, thickness can change according to required polysilicon resistance resistance size, resistance temperature characterisitic, then the mode injecting phosphorus is adopted to adulterate to polysilicon, implantation dosage can between 1E14 ~ 1E16, specifically can according to required polysilicon resistance resistance size, resistance temperature characterisitic is actual determines, then polysilicon is etched, etch the polysilicon strip (Poly) 17 of needs, and then adopt the SiO of chemical vapor deposition mode deposit a layer thickness between 0.2 μm ~ 1 μm
2film is as the insulating medium layer between polysilicon and lower single metal line, finally adopt diffusion furnace tube to carry out annealing to polysilicon resistance to activate, annealing temperature can between 800 DEG C ~ 1150 DEG C, annealing time can at 10min ~ 120min, concrete temperature and time can according to required polysilicon resistance resistance size, resistance temperature characterisitic demand is actual determines.
Step 8, as shown in figure 12, in a N doped region 5, the 2nd N doped region 6, a P doped region 7, the 2nd P doped region 8, the 3rd P doped region 9, the 4th P doped region 10, the 5th P doped region 11, a N
+doped region 13, the 2nd N
+doped region 14, the 3rd N
+the SiO of doped region 15
2above etch fairlead window respectively, at the SiO of polysilicon strip 17
2on etch two ports of two fairleads as resistance R, then the mode depositing metal Al of electron beam evaporation Al or sputtering Al is adopted, last chemical wet etching Al forms the metal connecting line of each assembly, and concrete annexation is: one of them fairlead of the polysilicon strip 17 of resistance R and a N of triode Q2
+doped region 13 is connected, simultaneously as the negative electrode of constant-current source integrated chip; Another fairlead of the polysilicon strip 17 of resistance R and the 3rd N of triode Q1
+the one P doped region 7 of doped region 15, triode Q2 is connected; The 5th P doped region 11 of triode Q1 is connected with the 2nd P doped region 8 of the 4th P doped region 10 of current regulator diode CRD, triode Q2, a N doped region 5 of triode Q2; The 2nd N doped region 6 of current regulator diode CRD and the 2nd P doped region 9 of current regulator diode CRD, the 2nd N
+doped region 14 is connected; The back side N of silicon substrate
+heavily doped region 2 finally adopts the mode deposit backplate metal of electron beam evaporation or sputtering, as titanium, nickel, silver etc. adopt multi-layer metal structure as the anode of constant-current source integrated chip.So far, the chip manufacturing proces of the present embodiment three constant-current source integrated chip terminates.
Claims (5)
1. a tabilized current power supply integrated chip, is characterized in that it comprises as N
-the monocrystalline silicon N of doped region (1)
-type polished silicon wafer, at described N
-the back side of doped region (1) is provided with N
+heavily doped region (2), at described N
-the front of doped region (1) is provided with a P of triode Q2
-2nd P of doped region (3) and current regulator diode CRD
-doped region (4), at a described P
-doped region (3) upper doping formation the one N doped region (5), at described 2nd P
-doped region (4) upper doping formation the 2nd N doped region (6), the upper formation the one P doped region (7) in a described N doped region (5), at a P
-the upper formation the 2nd P doped region (8) in doped region (3), at described 2nd P
-the upper formation the 3rd P doped region (9) in doped region (4) and the 4th P doped region (10), at the N of silicon substrate
-doped region (1) is formed respectively the 5th P doped region (11) of triode (Q1) and the 6th P doped region (12) of resistance R, upper formation the one N in a described P doped region (7)
+doped region (13); At the N of silicon substrate
-upper formation the 2nd N in doped region (1)
+doped region (14); Upper formation the 3rd N in the 5th P doped region (11)
+doped region (15); Upper formation the 4th N in the 6th P doped region (12) of resistance R
+doped region (16), the 4th N of described resistance R
+one end of doped region (16) and a N
+doped region (13) is connected, simultaneously as the negative electrode of constant-current source integrated chip; Described 4th N
+the other end of doped region (16) respectively with the 3rd N
+doped region (15), a P doped region (7) are connected; Described 5th P doped region (11) is connected with the 4th P doped region (1210), the 2nd P doped region (8), a N doped region (5) respectively; Described 2nd N doped region (6) respectively with the 3rd P doped region (9), the 2nd N
+doped region (14) is connected; Described N
+heavily doped region (2) is as the anode of constant-current source integrated chip.
2. a kind of tabilized current power supply integrated chip according to claim 1, it is characterized in that exchanging doped region doping type N, P type, namely N-type becomes P type, and P type becomes N-type, and the front of described silicon substrate is anode, and the back side is negative electrode.
3. a kind of tabilized current power supply integrated chip according to claim 1 and 2, is characterized in that the SiO in described resistance R front
2film is provided with a polysilicon strip (17), makes polysilicon strip form resistance R, adopt polysilicon resistance can regulate the temperature characterisitic of its resistance easily.
4. a manufacture method for tabilized current power supply integrated chip as claimed in claim 1, is characterized in that said method comprising the steps of:
Step one, get a slice monocrystalline silicon N
-type polished silicon wafer, as N
-doped region silicon substrate;
Step 2, at N
-the back side heavy doping of doped region silicon substrate forms N
+heavily doped region;
Step 3, at N
-the synchronous P forming triode Q2 on doped region
-2nd P of doped region and current regulator diode CRD
-doped region;
Step 4, a P at triode Q2
-to adulterate in doped region formation the one N doped region, at the 2nd P of current regulator diode CRD
-to adulterate in doped region formation the 2nd N doped region;
Step 5, on a N doped region of triode Q2 formed a P doped region, at a P
-doped region forms the 2nd P doped region; At the 2nd P of current regulator diode CRD
-doped region forms the 3rd P doped region and the 4th P doped region, at the N of silicon substrate
-doped region is formed respectively the 5th P doped region of triode Q1 and the 6th P doped region of resistance R;
Step 6, on a P doped region of triode Q2 formed a N
+doped region, at the N of silicon substrate
-doped region forms the 2nd N
+doped region; The 5th P doped region of triode Q1 forms the 3rd N
+doped region; The 6th P doped region of resistance R forms the 4th N
+doped region;
Step 7, in a N doped region, the 2nd N doped region, a P doped region, the 2nd P doped region, the 3rd P doped region, the 4th P doped region, the 5th P doped region, a N
+doped region, the 2nd N
+doped region, the 3rd N
+the SiO of doped region
2on etch fairlead window, wherein the 4th N of resistance R
+doped region etches two ports of two fairlead windows as resistance R, the 4th N of resistance R
+one of them fairlead of doped region and a N of triode Q2
+doped region is connected, simultaneously as the negative electrode of constant-current source integrated chip; 4th N of resistance R
+another fairlead of doped region and the 3rd N of triode Q1
+the one P doped region of doped region, triode Q2 is connected; The 5th P doped region of triode Q1 is connected with the 2nd P doped region of the 4th P doped region of current regulator diode CRD, triode Q2, a N doped region of triode Q2; The 2nd N doped region of current regulator diode CRD and the 2nd P doped region of current regulator diode CRD, the 2nd N
+doped region is connected; N
-the back side N of doped region silicon substrate
+heavily doped region is as the anode of constant-current source integrated chip.
5. the manufacture method of a kind of tabilized current power supply integrated chip according to claim 4, is characterized in that between step 6 and step 7, add a step, at the SiO in described resistance R front
2film etches the polysilicon strip of needs, then deposit one deck SiO
2film, as the insulating medium layer between polysilicon and lower single metal line, makes polysilicon strip form resistance R, adopts polysilicon resistance can regulate the temperature characterisitic of its resistance easily.
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| CN113114196B (en) * | 2021-04-29 | 2023-10-13 | 全球能源互联网研究院有限公司 | Photoelectric amplification integrated triode chip |
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| CN1812097A (en) * | 2005-01-27 | 2006-08-02 | 杨越培 | Semiconductor device |
| CN101668365A (en) * | 2008-09-05 | 2010-03-10 | 李旭明 | Constant-current source driver circuit and device |
| CN102421224A (en) * | 2011-09-05 | 2012-04-18 | 电子科技大学 | Self-feedback linear constant current device for driving LED (light-emitting diode) |
| CN203733798U (en) * | 2014-02-26 | 2014-07-23 | 江阴新顺微电子有限公司 | Adjustable constant-current source integrated chip |
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| CN1812097A (en) * | 2005-01-27 | 2006-08-02 | 杨越培 | Semiconductor device |
| CN101668365A (en) * | 2008-09-05 | 2010-03-10 | 李旭明 | Constant-current source driver circuit and device |
| CN102421224A (en) * | 2011-09-05 | 2012-04-18 | 电子科技大学 | Self-feedback linear constant current device for driving LED (light-emitting diode) |
| CN203733798U (en) * | 2014-02-26 | 2014-07-23 | 江阴新顺微电子有限公司 | Adjustable constant-current source integrated chip |
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