CN103762218A - 阵列基板及其制造方法和显示装置 - Google Patents

阵列基板及其制造方法和显示装置 Download PDF

Info

Publication number
CN103762218A
CN103762218A CN201410021348.9A CN201410021348A CN103762218A CN 103762218 A CN103762218 A CN 103762218A CN 201410021348 A CN201410021348 A CN 201410021348A CN 103762218 A CN103762218 A CN 103762218A
Authority
CN
China
Prior art keywords
source
drain electrode
layer
film transistor
active layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410021348.9A
Other languages
English (en)
Inventor
张家祥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Beijing BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201410021348.9A priority Critical patent/CN103762218A/zh
Publication of CN103762218A publication Critical patent/CN103762218A/zh
Priority to PCT/CN2014/082426 priority patent/WO2015106552A1/zh
Priority to US14/420,217 priority patent/US9653484B2/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本发明公开了一种阵列基板及其制造方法和显示装置。该阵列基板包括衬底基板和形成于衬底基板上的栅线、数据线、像素电极和薄膜晶体管，所述薄膜晶体管包括栅极、有源层和源漏极图形，所述源漏极图形和所述有源层连接，所述像素电极和所述有源层连接。本发明中将源极和漏极设置成一个源漏极图形，减小了薄膜晶体管的面积，从而提高了像素的开口率；本发明中将源极和漏极设置成一个源漏极图形，增大了薄膜晶体管沟道的宽长比W/L，提高了薄膜晶体管的充电电流，从而提高了薄膜晶体管的充电能力。

Description

阵列基板及其制造方法和显示装置
技术领域
本发明涉及显示技术领域，特别涉及一种阵列基板及其制造方法和显示装置。
背景技术
液晶显示器是目前常用的平板显示器，其中薄膜晶体管液晶显示器（Thin Film Transistor Liquid Crystal Display，简称：TFT-LCD）是液晶显示器中的主流产品。
其中，阵列基板是薄膜晶体管液晶显示器的重要部件。现有技术中，阵列基板包括：衬底基板和形成于衬底基板上的栅线和数据线，栅线和数据线限定出像素单元，像素单元包括：薄膜晶体管和像素电极，薄膜晶体管包括：栅极、有源层、源极和漏极，像素电极与漏极电连接。目前，薄膜晶体管的沟道通常采用U型、L型或者一字型设计。图1为现有技术中阵列基板的源漏极金属层的结构示意图，如图1所示，源漏极金属层包括：数据线211、源极212和漏极213，也就是说，数据线211、源极212和漏极213同层设置。其中，数据线211和源极212一体成型，漏极213和像素电极连接，且源极212和漏极213分离设置。如图1所示，薄膜晶体管的沟道的宽度为W，薄膜晶体管的沟道的长度为L，其中，宽度W为源极212或者漏极213的宽度，长度L为源极212和漏极213之间的距离。
但是，现有技术中的阵列基板存在如下问题：
1）由于源极和漏极分离设置，导致薄膜晶体管的面积较大，从而降低了像素的开口率；
2）由于源极和漏极分离设置，导致薄膜晶体管沟道的宽长比W/L较小，降低了薄膜晶体管的充电电流，从而降低了薄膜晶体管充电能力。
发明内容
本发明提供一种阵列基板及其制造方法和显示装置，用于提高像素的开口率和提高薄膜晶体管的充电能力。
为实现上述目的，本发明提供了一种阵列基板，包括衬底基板和形成于衬底基板上的栅线、数据线、像素电极和薄膜晶体管，所述薄膜晶体管包括栅极、有源层和源漏极图形，所述源漏极图形和所述有源层连接，所述像素电极和所述有源层连接。
可选地，所述源漏极图形为所述薄膜晶体管的源极和漏极连接而形成的一体结构。
可选地，所述源漏极图形为环形结构。
可选地，所述有源层之上形成有刻蚀阻挡层，所述源漏极图形形成于所述刻蚀阻挡层之上且所述源漏极图形之上形成有保护层，所述像素电极形成于所述保护层之上，所述刻蚀阻挡层和所述保护层上设置有过孔，所述像素电极填充于所述过孔内以与有源层连接。
可选地，所述刻蚀阻挡层的宽度比所述有源层的宽度小至少1μm。
可选地，所述源漏极图形的外环的宽度大于或者等于所述有源层的宽度。
可选地，所述源漏极图形的内环的宽度小于所述刻蚀阻挡层的宽度。
可选地，所述过孔的宽度小于所述源漏极图形的内环的宽度。
可选地，所述薄膜晶体管的充电电流Ion二μeff(εinsε0/tins(W/L)(Vgs-Vth)Vds，其中，μeff为电子迁移率，εins为相对介电常数，ε0为绝对介电常数，tins为充电时间，Vgs为栅源电压，Vth为阈值电压，Vds为漏源电压，宽度W为所述源漏极图形的中间环的周长，长度L为所述过孔的边缘与所述源漏极图形的内环之间的距离。
为实现上述目的，本发明提供了一种显示装置，包括：上述阵列基板。
为实现上述目的，本发明提供了一种阵列基板的制造方法，包括在衬底基板的上方形成栅线、数据线、薄膜晶体管和像素电极的步骤，所述形成薄膜晶体管的步骤包括形成栅极、有源层和源漏极图形的步骤，所述源漏极图形和所述有源层连接，所述像素电极和所述有源层连接。
可选地，所述在衬底基板的上方形成栅线、数据线、薄膜晶体管和像素电极的步骤具体包括如下步骤：
在衬底基板上形成栅极金属层，通过对栅极金属层进行构图工艺形成栅线和栅极；
在栅线和栅极之上形成栅绝缘层；
在栅绝缘层上形成有源材料层，通过对有源材料层进行构图工艺形成有源层；
在有源层上形成刻蚀阻挡材料层，通过对刻蚀阻挡材料层进行构图工艺形成刻蚀阻挡层；
在刻蚀阻挡层上形成源漏极金属层，通过对源漏极金属层进行构图工艺形成源漏极图形和数据线；
在源漏极图形和数据线上形成保护层；
对保护层和刻蚀阻挡层进行构图工艺形成过孔；
在保护层上形成像素电极材料层，对像素电极材料层进行构图工艺形成像素电极，该像素电极填充于过孔内。
本发明具有以下有益效果：
本发明提供的阵列基板及其制造方法和显示装置的技术方案中，薄膜晶体管包括栅极、有源层和源漏极图形，源漏极图形和有源层连接，像素电极和有源层连接，本发明中将源极和漏极设置成一个源漏极图形，减小了薄膜晶体管的面积，从而提高了像素的开口率；本发明中将源极和漏极设置成一个源漏极图形，增大了薄膜晶体管沟道的宽长比W/L，提高了薄膜晶体管的充电电流，从而提高了薄膜晶体管的充电能力。
附图说明
图1为现有技术中阵列基板的源漏极金属层的结构示意图；
图2为本发明实施例一提供的一种阵列基板的结构示意图；
图3为图2中A-A向剖视图；
图4为图2中B-B向剖视图；
图5为图2中源漏极图形的结构示意图；
图6为本发明实施例三提供的一种阵列基板的制造方法的流程图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的阵列基板及其制造方法和显示装置进行详细描述。
图2为本发明实施例一提供的一种阵列基板的结构示意图，图3为图2中A-A向剖视图，图4为图2中B-B向剖视图，如图2、图3和图4所示，该阵列基板包括：衬底基板11和形成于衬底基板11上的栅线12、数据线13、薄膜晶体管15和像素电极16，薄膜晶体管15包括：栅极151、有源层152和源漏极图形153，源漏极图形153和有源层152连接，像素电极16和有源层152连接。
本实施例中，栅极151和栅线12连接，且栅极151和栅线12一体成型；源漏极图形153和数据线13连接，且源漏极图形153和数据线13一体成型。栅极151和栅线12形成于衬底基板11上，有源层152形成于栅极151的上方，源漏极图形153形成于有源层152之上。进一步地，栅极151和栅线12之上还形成有栅绝缘层20，有源层152形成于栅极151上方的栅绝缘层20之上。
本实施例中，有源层152为氧化物半导体层，优选地，该氧化物半导体层的材料为IGZO；像素电极16的材料为透明导电材料，优选地，该透明导电材料为ITO；优选地，刻蚀阻挡层的材料为SiO2。
其中，源漏极图形153为薄膜晶体管的源极和漏极连接而形成的一体结构。图5为图2中源漏极图形的结构示意图，如图5所示，优选地，源漏极图形153为环形结构。
可选地，有源层152之上形成有刻蚀阻挡层17，源漏极图形153形成于刻蚀阻挡层17之上且源漏极图形153之上形成有保护层18，像素电极16形成于保护层18之上，刻蚀阻挡层17和保护层18上设置有过孔19，像素电极16填充于过孔19内以与有源层152连接。优选地，过孔19与源漏极图形153可同心设置。
其中，部分源漏极图形153位于刻蚀阻挡层17之上，而部分源漏极图形153位于有源层152之上以实现与有源层152连接。如图3所示，为使得源漏极图形153与有源层152连接，刻蚀阻挡层17的宽度d1需小于有源层152的宽度d2；优选地，刻蚀阻挡层17的宽度d1比有源层152的宽度d2小至少1μm，从而增大源漏极图形153与有源层152的接触面积，进而使得源漏极图形153与有源层152能够良好的接触。
如图4所示，为保证源漏极图形153与有源层152能够良好的接触，源漏极图形153的外环的宽度d3大于或者等于有源层152的宽度d4。本实施例中，优选地，源漏极图形153的外环的宽度d3等于有源层152的宽度d4。
如图3所示，优选地，源漏极图形153的内环的宽度d5小于刻蚀阻挡层17的宽度d1，从而有效避免了形成源漏极图形153时使用的刻蚀液对有源层152产生影响。
如图3所示，过孔19的宽度d6小于源漏极图形153的内环的宽度d5，从而防止位于过孔19内的像素电极16与源漏极图形153搭接而导通。
本实施例提供的阵列基板中，当栅线12向栅极151提供栅极信号时，薄膜晶体管15开启，源漏极图形153通过有源层152与像素电极16导通；此时，数据线13提供的数据信号通过源漏极图形153和有源层152输出至像素电极16，从而实现了对像素电极16的充电。
薄膜晶体管15的充电电流Ion二μeff(εinsε0/tins)(W/L)(Vgs-Vth)Vds，中，μeff为电子迁移率，εins为相对介电常数，ε0为绝对介电常数，tins为充电时间，Vgs为栅源电压，Vth为阈值电压，Vds为漏源电压。其中，如图5所示，宽度W为源漏极图形153的中间环的周长；如图4所示，长度L为过孔19的边缘与源漏极图形153的内环之间的距离。与现有技术相比，由于W是源漏极图形153的中间环的周长，因此与现有技术相比，W得到了较大提高；本实施例中可通过调节过孔19的尺寸而减小L，因此与现有技术相比本实施例可减小L，从而增大宽长比W/L。从上述充电电流Ion的公式可以看出，在μeff、εins、ε0、tins、Vgs、Vth和Vds不变的前提下，本实施例提高了W且减小了L，提高了薄膜晶体管15的充电电流Ion，从而提高了薄膜晶体管15的充电能力。
本实施例提供的阵列基板中，薄膜晶体管包括栅极、有源层和源漏极图形，源漏极图形和有源层连接，像素电极和有源层连接，本实施例中将源极和漏极设置成一个源漏极图形，减小了薄膜晶体管的面积，从而提高了像素的开口率；本实施例中将源极和漏极设置成一个源漏极图形，增大了薄膜晶体管沟道的宽长比W/L，提高了薄膜晶体管的充电电流，从而提高了薄膜晶体管的充电能力。本实施例可通过调节过孔的尺寸而调节沟道的长度，从而可根据生产需要灵活的设置沟道的尺寸。
本发明实施例二提供了一种显示装置，该显示装置可包括：阵列基板。其中，阵列基板可采用上述实施例一提供的阵列基板，此处不再赘述。
本实施例提供的显示装置中，薄膜晶体管包括栅极、有源层和源漏极图形，源漏极图形和有源层连接，像素电极和有源层连接，本实施例中将源极和漏极设置成一个源漏极图形，减小了薄膜晶体管的面积，从而提高了像素的开口率；本实施例中将源极和漏极设置成一个源漏极图形，增大了薄膜晶体管沟道的宽长比W/L，提高了薄膜晶体管的充电电流，从而缩短了薄膜晶体管的充电能力。本实施例可通过调节过孔的尺寸而调节沟道的长度，从而可根据生产需要灵活的设置沟道的尺寸。
本发明实施例三提供了一种阵列基板的制造方法，该方法包括：在衬底基板的上方形成栅线、数据线、薄膜晶体管和像素电极的步骤，其中，形成薄膜晶体管的步骤包括形成栅极、有源层和源漏极图形的步骤，所述源漏极图形和所述有源层连接，所述像素电极和所述有源层连接。
图6为本发明实施例三提供的一种阵列基板的制造方法的流程图，如图6所示，该方法包括：
步骤1011、在衬底基板上形成栅极金属层，通过对栅极金属层进行构图工艺形成栅线和栅极。
本实施例中，构图工艺可包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离。
步骤1012、在栅线和栅极之上形成栅绝缘层。
步骤1013、在栅绝缘层上形成有源材料层，通过对有源材料层进行构图工艺形成有源层。
本步骤中，构图工艺中的刻蚀为湿法刻蚀。
步骤1014、在有源层上形成刻蚀阻挡材料层，通过对刻蚀阻挡材料层进行构图工艺形成刻蚀阻挡层。
本步骤中，构图工艺中的刻蚀为干法刻蚀。
步骤1015、在刻蚀阻挡层上形成源漏极金属层，通过对源漏极金属层进行构图工艺形成源漏极图形和数据线。
本步骤中，构图工艺中的刻蚀为湿法刻蚀。优选地，源漏极图形为环形结构。
步骤1016、在源漏极图形和数据线上形成保护层。
步骤1017、对保护层和刻蚀阻挡层进行构图工艺形成过孔。
步骤1018、在保护层上形成像素电极材料层，对像素电极材料层进行构图工艺形成像素电极，该像素电极填充于过孔内以与有源层连接。
本实施例提供的阵列基板的制造方法可用于制造上述实施例一提供的阵列基板，对阵列基板的具体描述可参见上述实施例一。
本实施例提供的阵列基板的制造方法制造出的阵列基板中，薄膜晶体管包括栅极、有源层和源漏极图形，源漏极图形和有源层连接，像素电极和有源层连接，本实施例中将源极和漏极设置成一个源漏极图形，减小了薄膜晶体管的面积，从而提高了像素的开口率；本实施例中将源极和漏极设置成一个源漏极图形，增大了薄膜晶体管沟道的宽长比W/L，提高了薄膜晶体管的充电电流，从而提高了薄膜晶体管的的充电能力。本实施例可通过调节过孔的尺寸而调节沟道的长度，从而可根据生产需要灵活的设置沟道的尺寸。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (12)

1.一种阵列基板，包括衬底基板和形成于衬底基板上的栅线、数据线、像素电极和薄膜晶体管，其特征在于，所述薄膜晶体管包括栅极、有源层和源漏极图形，所述源漏极图形和所述有源层连接，所述像素电极和所述有源层连接。
2.根据权利要求1所述的阵列基板，其特征在于，所述源漏极图形为所述薄膜晶体管的源极和漏极连接而形成的一体结构。
3.根据权利要求2所述的阵列基板，其特征在于，所述源漏极图形为环形结构。
4.根据权利要求3所述的阵列基板，其特征在于，所述有源层之上形成有刻蚀阻挡层，所述源漏极图形形成于所述刻蚀阻挡层之上且所述源漏极图形之上形成有保护层，所述像素电极形成于所述保护层之上，所述刻蚀阻挡层和所述保护层上设置有过孔，所述像素电极填充于所述过孔内以与有源层连接。
5.根据权利要求4所述的阵列基板，其特征在于，所述刻蚀阻挡层的宽度比所述有源层的宽度小至少1μm。
6.根据权利要求3所述的阵列基板，其特征在于，所述源漏极图形的外环的宽度大于或者等于所述有源层的宽度。
7.根据权利要求4所述的阵列基板，其特征在于，所述源漏极图形的内环的宽度小于所述刻蚀阻挡层的宽度。
8.根据权利要求4所述的阵列基板，其特征在于，所述过孔的宽度小于所述源漏极图形的内环的宽度。
9.根据权利要求4所述的阵列基板，其特征在于，所述薄膜晶体管的充电电流Ion＝ueff(εinsε0/tins)(W/L)(Vgs-Vth)Vds，其中，μeff为电子迁移率，εins为相对介电常数，ε0为绝对介电常数，tins为充电时间，Vgs为栅源电压，Vth为阈值电压，Vds为漏源电压，宽度W为所述源漏极图形的中间环的周长，长度L为所述过孔的边缘与所述源漏极图形的内环之间的距离。
10.一种显示装置，其特征在于，包括：上述权利要求1至9任一所述的阵列基板。
11.一种阵列基板的制造方法，包括在衬底基板的上方形成栅线、数据线、薄膜晶体管和像素电极的步骤，其特征在于，所述形成薄膜晶体管的步骤包括形成栅极、有源层和源漏极图形的步骤，所述源漏极图形和所述有源层连接，所述像素电极和所述有源层连接。
12.根据权利要求11所述的阵列基板的制造方法，其特征在于，所述在衬底基板的上方形成栅线、数据线、薄膜晶体管和像素电极的步骤具体包括如下步骤：
在衬底基板上形成栅极金属层，通过对栅极金属层进行构图工艺形成栅线和栅极；
在栅线和栅极之上形成栅绝缘层；
在栅绝缘层上形成有源材料层，通过对有源材料层进行构图工艺形成有源层；
在有源层上形成刻蚀阻挡材料层，通过对刻蚀阻挡材料层进行构图工艺形成刻蚀阻挡层；
在刻蚀阻挡层上形成源漏极金属层，通过对源漏极金属层进行构图工艺形成源漏极图形和数据线；
在源漏极图形和数据线上形成保护层；
对保护层和刻蚀阻挡层进行构图工艺形成过孔；
在保护层上形成像素电极材料层，对像素电极材料层进行构图工艺形成像素电极，该像素电极填充于过孔内。
CN201410021348.9A 2014-01-16 2014-01-16 阵列基板及其制造方法和显示装置 Pending CN103762218A (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201410021348.9A CN103762218A (zh) 2014-01-16 2014-01-16 阵列基板及其制造方法和显示装置
PCT/CN2014/082426 WO2015106552A1 (zh) 2014-01-16 2014-07-17 阵列基板及其制造方法和显示装置、薄膜晶体管及其制造方法
US14/420,217 US9653484B2 (en) 2014-01-16 2014-07-17 Array substrate and manufacturing method thereof, display device, thin-film transistor (TFT) and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410021348.9A CN103762218A (zh) 2014-01-16 2014-01-16 阵列基板及其制造方法和显示装置

Publications (1)

Publication Number Publication Date
CN103762218A true CN103762218A (zh) 2014-04-30

Family

ID=50529429

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410021348.9A Pending CN103762218A (zh) 2014-01-16 2014-01-16 阵列基板及其制造方法和显示装置

Country Status (3)

Country Link
US (1) US9653484B2 (zh)
CN (1) CN103762218A (zh)
WO (1) WO2015106552A1 (zh)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015106552A1 (zh) * 2014-01-16 2015-07-23 京东方科技集团股份有限公司 阵列基板及其制造方法和显示装置、薄膜晶体管及其制造方法
CN105405401A (zh) * 2015-11-11 2016-03-16 友达光电股份有限公司 像素电路
WO2016070574A1 (zh) * 2014-11-05 2016-05-12 京东方科技集团股份有限公司 一种金属氧化物薄膜晶体管及其制备方法、阵列基板
US20160190157A1 (en) * 2014-12-30 2016-06-30 Shenzhen China Star Optoelectronics Technology Co. Ltd. Pixel structure and manufacturing method thereof
WO2016123931A1 (zh) * 2015-02-06 2016-08-11 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、显示基板和显示装置
CN106206426A (zh) * 2016-08-01 2016-12-07 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN107045239A (zh) * 2017-04-05 2017-08-15 合肥京东方光电科技有限公司 阵列基板及其制作方法、显示面板及显示装置
WO2018099052A1 (zh) * 2016-12-01 2018-06-07 京东方科技集团股份有限公司 阵列基板的制备方法、阵列基板及显示装置
WO2018149139A1 (zh) * 2017-02-16 2018-08-23 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示基板及显示装置
CN109509440A (zh) * 2018-07-02 2019-03-22 惠科股份有限公司 显示面板及液晶显示面板的制造方法
US11244970B2 (en) 2017-05-12 2022-02-08 Boe Technology Group Co., Ltd. Thin film transistor, array substrate, display apparatus, and method of fabricating thin film transistor

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106684125B (zh) * 2015-11-05 2020-05-08 群创光电股份有限公司 显示设备
CN108493216B (zh) * 2018-03-21 2021-04-27 福建华佳彩有限公司 一种tft阵列基板、显示装置及tft阵列基板的制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101078843A (zh) * 2006-05-23 2007-11-28 京东方科技集团股份有限公司 一种tft lcd阵列基板结构及其制造方法
CN101174651A (zh) * 2007-12-10 2008-05-07 友达光电股份有限公司 像素结构、薄膜晶体管及其制作方法
CN101750825A (zh) * 2008-12-18 2010-06-23 乐金显示有限公司 用于显示设备的阵列基板及其制造方法
CN103094354A (zh) * 2013-01-28 2013-05-08 合肥京东方光电科技有限公司 阵列基板及其制造方法、显示装置
CN103489921A (zh) * 2013-09-29 2014-01-01 合肥京东方光电科技有限公司 一种薄膜晶体管及其制造方法、阵列基板及显示装置
US20140008645A1 (en) * 2012-07-06 2014-01-09 Lg Display Co., Ltd. Thin film transistor substrate having metal oxide and method for manufacturing

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100850613B1 (ko) * 2004-08-24 2008-08-05 샤프 가부시키가이샤 액티브 매트릭스 기판 및 그것을 구비한 표시 장치
JP4622630B2 (ja) 2005-03-31 2011-02-02 凸版印刷株式会社 薄膜トランジスタの製造方法
CN102088025A (zh) * 2009-12-02 2011-06-08 群康科技(深圳)有限公司 薄膜晶体管基板及其制造方法
CN103762218A (zh) 2014-01-16 2014-04-30 北京京东方光电科技有限公司 阵列基板及其制造方法和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101078843A (zh) * 2006-05-23 2007-11-28 京东方科技集团股份有限公司 一种tft lcd阵列基板结构及其制造方法
CN101174651A (zh) * 2007-12-10 2008-05-07 友达光电股份有限公司 像素结构、薄膜晶体管及其制作方法
CN101750825A (zh) * 2008-12-18 2010-06-23 乐金显示有限公司 用于显示设备的阵列基板及其制造方法
US20140008645A1 (en) * 2012-07-06 2014-01-09 Lg Display Co., Ltd. Thin film transistor substrate having metal oxide and method for manufacturing
CN103094354A (zh) * 2013-01-28 2013-05-08 合肥京东方光电科技有限公司 阵列基板及其制造方法、显示装置
CN103489921A (zh) * 2013-09-29 2014-01-01 合肥京东方光电科技有限公司 一种薄膜晶体管及其制造方法、阵列基板及显示装置

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9653484B2 (en) 2014-01-16 2017-05-16 Boe Technology Group Co., Ltd. Array substrate and manufacturing method thereof, display device, thin-film transistor (TFT) and manufacturing method thereof
WO2015106552A1 (zh) * 2014-01-16 2015-07-23 京东方科技集团股份有限公司 阵列基板及其制造方法和显示装置、薄膜晶体管及其制造方法
US9818883B2 (en) 2014-11-05 2017-11-14 Boe Technology Group Co., Ltd. Metal oxide thin film transistor and preparation method thereof, as well as array substrate
WO2016070574A1 (zh) * 2014-11-05 2016-05-12 京东方科技集团股份有限公司 一种金属氧化物薄膜晶体管及其制备方法、阵列基板
US20160190157A1 (en) * 2014-12-30 2016-06-30 Shenzhen China Star Optoelectronics Technology Co. Ltd. Pixel structure and manufacturing method thereof
WO2016123931A1 (zh) * 2015-02-06 2016-08-11 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、显示基板和显示装置
US10043916B2 (en) 2015-02-06 2018-08-07 Boe Technology Group Co., Ltd. Thin-film transistor having channel structure with increased width-length ratio
CN105405401A (zh) * 2015-11-11 2016-03-16 友达光电股份有限公司 像素电路
CN106206426A (zh) * 2016-08-01 2016-12-07 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN106206426B (zh) * 2016-08-01 2019-03-01 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
WO2018099052A1 (zh) * 2016-12-01 2018-06-07 京东方科技集团股份有限公司 阵列基板的制备方法、阵列基板及显示装置
US10490670B2 (en) 2016-12-01 2019-11-26 Boe Technology Group Co., Ltd. Manufacturing method of array substrate, array substrate with active layer being above first electrode, and display device
WO2018149139A1 (zh) * 2017-02-16 2018-08-23 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示基板及显示装置
CN107045239A (zh) * 2017-04-05 2017-08-15 合肥京东方光电科技有限公司 阵列基板及其制作方法、显示面板及显示装置
US11244970B2 (en) 2017-05-12 2022-02-08 Boe Technology Group Co., Ltd. Thin film transistor, array substrate, display apparatus, and method of fabricating thin film transistor
CN108878515B (zh) * 2017-05-12 2022-02-25 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板
CN109509440A (zh) * 2018-07-02 2019-03-22 惠科股份有限公司 显示面板及液晶显示面板的制造方法

Also Published As

Publication number Publication date
WO2015106552A1 (zh) 2015-07-23
US9653484B2 (en) 2017-05-16
US20160027807A1 (en) 2016-01-28

Similar Documents

Publication Publication Date Title
CN103762218A (zh) 阵列基板及其制造方法和显示装置
US10991827B2 (en) Structure of oxide thin film transistor
CN102683353B (zh) 用于显示设备的阵列基板及其制造方法
CN102636927A (zh) 阵列基板及其制造方法
CN103730414B (zh) 薄膜晶体管基板的制造方法
CN103456739A (zh) 阵列基板及其制造方法和显示装置
CN105655291A (zh) 一种阵列基板的制作方法、阵列基板和显示面板
CN104241299A (zh) 氧化物半导体tft基板的制作方法及结构
CN104393051A (zh) 一种薄膜晶体管及其制备方法、阵列基板
CN103474439B (zh) 一种显示装置、阵列基板及其制作方法
WO2017156885A1 (zh) 薄膜晶体管、阵列基板及其制作和驱动方法、显示装置
CN104810375B (zh) 一种阵列基板及其制作方法和一种显示装置
CN108122759B (zh) 薄膜晶体管及其制作方法、阵列基板及显示装置
CN203932068U (zh) 一种薄膜晶体管、阵列基板和显示装置
CN105304720A (zh) 薄膜晶体管
CN105206617B (zh) 阵列基板的制造方法
CN105242435A (zh) 阵列基板及制作方法、液晶显示面板
CN103839950B (zh) Tft‑lcd阵列基板及其制造方法
KR101831080B1 (ko) 박막 트랜지스터 기판의 제조 방법 및 이를 이용하여 제조된 박막 트랜지스터 기판
CN110224031A (zh) 改善金属氧化物tft特性的结构与其制作方法
US8614444B2 (en) Top-gate transistor array substrate
CN205810822U (zh) 薄膜晶体管及显示面板
KR101829805B1 (ko) 산화물 반도체 트랜지스터 및 이의 제조 방법
CN105762161B (zh) 光感测阵列的光感测单元的制造方法及其结构
CN203941905U (zh) 一种薄膜晶体管、阵列基板及显示装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20140430