CN103746694A - Slope conversion circuit applied to two-step type integral analog-to-digital converter - Google Patents

Abstract

The invention belongs to the technical field of semiconductors and integrated circuits, in particular to a slope conversion circuit applied to a two-step integral analog-to-digital converter. The slope conversion circuit of the present invention includes an operational amplifier, a pair of sampling capacitors, a pair of parasitic balancing capacitors and six switches. In the first step of high-level analog-to-digital conversion, the input ramp signal is directly output, and is sampled and held by the operational amplifier and the first sampling capacitor at the same time; in the second step of low-level analog-to-digital conversion, the input ramp signal is input to the positive input terminal of the operational amplifier , the operational amplifier transmits the voltage change of its positive input terminal to the floating plate of the second sampling capacitor with a gain of one, and superimposes it with the holding voltage of the first step here as the output of the ramp conversion circuit. The invention can effectively eliminate the gain error caused by the parasitic capacitance in the transfer process of the voltage change of the analog-to-digital converter, and improve the precision and speed.

Description

A Slope Conversion Circuit Applied to Two-step Integral Analog-to-Digital Converter

technical field

The invention belongs to the technical field of semiconductors and integrated circuits, and in particular relates to a slope conversion circuit applied to a two-step integral analog-to-digital converter in an integrated circuit.

Background technique

Due to its simple structure, low power consumption, and high precision, the integral analog-to-digital converter has very obvious advantages in the low-speed field, especially in the application of multi-channel parallel analog-to-digital converters, the integral analog-to-digital converter is even more Widely used for its excellent channel-to-channel consistency. But the conversion time of the traditional B-bit integral analog-to-digital converter is 2 ^B clock cycles, which limits the improvement of its accuracy. Therefore, the integral analog-to-digital converter changes from a traditional one-step structure to a two-step structure, and changes the relationship between conversion time and accuracy from an exponential relationship (2 ^B ) to an exponential relationship (2 ^M +2 ^N , where M +N=B), thus shortening the conversion time. The two-step structure further includes: a two-step multi-slope single-slope structure, a two-step multi-slope multi-slope structure and a two-step single-slope single-slope structure. The two-step single-slope single-slope structure eliminates the matching and power consumption problems of the multi-slope structure, so it can reduce the conversion time more effectively in medium-to-high-precision analog-to-digital conversion applications.

In the known circuit, the principle of the two-step single-slope single-slope integral analog-to-digital converter is shown in FIG. and a ramp signal generator 105 (usually implemented with a digital-to-analog converter). The conversion process is divided into two steps: the high M bit and the low N bit: the first step is to convert the high M bit, the high M bit of the counting and controller 104 starts counting from zero, and the ramp signal generator 105 outputs a ladder ramp signal, and the ramp signal The signal to be quantized input by the analog-to-digital converter is respectively input to the two input terminals of the comparator 102. When the output of the comparator 102 is reversed, the latch and adder 103 latches the value (m) of the count and controller 104 at this time , completing the conversion of the high bit M; at the same time, the traditional ramp conversion circuit 101 samples and stores the corresponding ramp signal. In the second step, the low-order N bits are converted, and the low-order N of the counting and controller 104 starts counting from zero, and the ramp signal generator 105 outputs a ladder ramp signal (its step size is 1/2 ^N of the first step), the traditional ramp Conversion circuit 101 inputs this ramp signal and the voltage value stored in the first step to the positive end of comparator 102 after being superimposed, and when comparator 102 reverses again, latch and adder 103 latch count and the value of controller 104 ( n), complete the conversion of the lower N bits, and calculate the result of the analog-to-digital conversion D=2 ^N m+n.

During the conversion process, the conventional ramp conversion circuit 101 has a great influence on the performance of the entire analog-to-digital converter. First of all, the switches S ₁₁ , S ₁₂ , and S ₁₃ in the ramp conversion circuit will have two non-ideal factors, charge injection and clock feedthrough, which will cause the voltage stored in the voltage storage circuit to deviate from the ideal value, thereby affecting performance of the analog-to-digital converter. This problem can be solved by the known low level ramp extension method. Secondly, due to the parasitic capacitance of node D, it will cause the first step to switch to the second step, and during the conversion process of the second step, when the voltage change of node E is transmitted to node D, the gain of the voltage change is less than 1; but this gain error does not exist in the first conversion step, which eventually causes the nonlinearity of the analog-to-digital converter. Since non-monotonicity occurs when the gain is less than 1, and missing codes occur when the gain is greater than 1, the conventional ramp conversion circuit 101 will cause non-monotonic characteristics of the ADC.

Contents of the invention

Aiming at the problems existing in the prior art of the two-step single-slope single-slope integral analog-to-digital converter, the present invention provides a slope conversion circuit to solve the problem of the first two-step single-slope single-slope integral analog-to-digital converter In the process of switching from the first step to the second step, and the voltage change caused by the second step operation is transmitted to the output of the slope conversion circuit, the problem of gain error due to parasitic capacitance.

The slope conversion circuit provided by the present invention, as shown in Figure 3, includes: an operational amplifier A1, a pair of sampling capacitors _CH1 and _CH2 , a pair of parasitic balancing capacitors C _M1 and C _M2 , six switches _S1 , _S2 , S ₃ , S ₄ , S ₅ , S ₆ . On the one hand, the input slope signal is connected to the output terminal of the slope conversion circuit through switches _S1 and _S6 in turn, and on the other hand, it is connected to the positive input terminal of the operational amplifier through switch _S2 ; the positive input terminal of the operational amplifier is connected to the reference terminal through switch _S3 The level is connected; the negative input terminal of the operational amplifier is connected to the output terminal of the operational amplifier through the switch _S4 on the one hand, and connected to the output terminal of the operational amplifier through the first sampling capacitor C _H1 and the switch _S5 on the other hand; The output terminal of the amplifier is connected to the output terminal of the slope conversion circuit through the switch _S5 and the second sampling capacitor _CH2 in turn; the two plates of the second sampling capacitor _CH2 are connected through the switch _S6 ; the first parasitic balancing capacitor C _M1 One plate of C M2 is grounded, and the other plate is connected to the negative input terminal of the operational amplifier; one plate of the second parasitic balancing capacitor C _M2 is grounded, and the other plate is connected to the output terminal of the slope conversion circuit.

In the above scheme, the two sampling capacitors are matched equally. The two parasitic balancing capacitors have capacitance values greater than or equal to zero, and are used to adjust the equivalent ground parasitic capacitances of the negative input terminal (X) of the operational amplifier and the output terminal (A) of the slope conversion circuit respectively, so that the above two nodes (X and A) have equal capacitance to ground. The sum of the sampling capacitance and the ground capacitance is called the total capacitance, and the total capacitances of the above two nodes (X and A) are respectively called the first total capacitance and the second total capacitance. Therefore, the first total capacitance and the second total capacitance are equal.

In the above solution, the operational amplifier, the first sampling capacitor C _H1 and the switches _S4 and _S5 constitute a sample-and-hold circuit with a capacitance inversion structure. The operational amplifier is controlled by switches S ₂ , S ₃ , S ₄ and S ₅ , and works successively in sampling mode, holding mode and following mode in one analog-to-digital conversion cycle: in sampling mode, S ₄ is on, S ₅ is off, The negative input terminal of the operational amplifier is connected with the output terminal of the operational amplifier, one plate of the first sampling capacitor _CH1 is connected with the negative input terminal of the operational amplifier, and the other plate samples the input ramp signal; in the hold mode and follow mode, S ₄ is turned off, S ₅ is turned on, and the other plate of the first sampling capacitor _CH1 is connected to the output terminal of the operational amplifier; the positive input terminal of the operational amplifier is connected to the reference level through the conducted S ₃ in the sampling mode and the holding mode Connected, and connected to the input ramp signal through the conduction of _S2 in the following mode.

In the above scheme, the input mode of the input ramp signal in the ramp conversion circuit is controlled by three switches (S ₁ , S ₂ and S ₆ ):

(1) When the first step of high-order analog-to-digital conversion starts, S ₁ and S ₆ are turned on, S ₂ is turned off, and the input ramp signal is connected to the output of the ramp conversion circuit, which is directly used as the output signal of the ramp conversion circuit; the input ramp signal is simultaneously It is sampled by the first sampling capacitor _CH1 ; the two plates of the second sampling capacitor _CH2 are short-circuited to the output of the slope conversion circuit by the switch _S6 .

(2) The sampling process of the first high-bit analog-to-digital conversion continues until the input ramp signal is just greater than the input signal of the analog-to-digital converter. Both S ₁ and S ₂ are turned off, and the input ramp signal is no longer input to the ramp conversion circuit. At this time, the operational amplifier enters the holding mode, and its output holding voltage is the voltage value of the last sampled input ramp signal; after the second sampling capacitor _CH2 is stable at the output of the operational amplifier, the switch _S6 between the two plates is closed One of the plates is connected to the output terminal of the operational amplifier, and the other plate is floating and used as the output of the slope conversion circuit; at this time, the voltages of the two plates of the second sampling capacitor _CH2 are holding voltages.

(3) In the second step of low-level analog-to-digital conversion, S ₁ is turned off, S ₂ is turned on, and the input ramp signal is input to the positive input terminal of the operational amplifier, and the operational amplifier in the following mode transmits the voltage change of the positive input terminal of the operational amplifier to the The output terminal of the operational amplifier; according to the principle of charge conservation, it is further transmitted to the floating plate of the second sampling capacitor _CH2 , and is superimposed on the first step holding voltage here as the output signal of the slope conversion circuit.

In the above scheme, the voltage change of the positive input terminal of the operational amplifier is generated by the following two operations: (1) When the operational amplifier enters the following mode from the hold mode, the positive input terminal is switched from the reference level to the initial level of the ramp signal input in the second step. (2) When the operational amplifier works in follower mode, the voltage of the ramp signal input in the second step changes.

In the above scheme, the voltage change at the positive input terminal of the operational amplifier is transferred to the output terminal of the slope conversion circuit through two cascaded transfer functions: (1) The first stage is the operational amplifier in follower mode to transfer the voltage change at the positive input terminal of the operational amplifier to To the output terminal of the operational amplifier, the gain of the first stage transfer function is equal to the ratio of the first total capacitance to the first sampling capacitance; (2) The second stage is the output terminal of the operational amplifier output voltage change transmission ramp conversion circuit, the second The gain of the stage transfer function is equal to the ratio of the second sampling capacitance to the second total capacitance. Since the above two sampling capacitors and the two total capacitors are respectively equal, the gains of the above two stages are reciprocals of each other; and the gains of the two stages are multiplied to form the total gain, so the total gain of the voltage change transfer function of the slope conversion circuit is equal to one.

When the above solution is implemented, due to capacitance matching and other reasons, the above two sampling capacitors and the two total capacitors have capacitance deviations, but the total gain is only determined by their respective relative deviations. This relative deviation is implemented in integrated circuits. Both can be controlled within ±1%, so the overall gain is still very close to unity.

The beneficial effect of the present invention is that it can effectively eliminate the gain error caused by the parasitic capacitance of the voltage change at the input terminal of the slope conversion circuit transmitted to the output terminal, the voltage change is switched from the first step to the second step, and the second step caused by the conversion process. At the same time, the sample-and-hold circuit part adopts the sample-and-hold circuit with the traditional capacitor flipping structure, which retains the sampling timing of the lower plate, and can effectively eliminate the nonlinear error introduced by switch injection and feedthrough. Based on the above improvement effects, the present invention can effectively improve the precision and speed of the two-step integral analog-to-digital converter.

Description of drawings

Fig. 1 is a schematic diagram of a known two-step single-slope single-slope integrating analog-to-digital converter adopting a traditional slope conversion circuit, where the dotted box is the equivalent parasitic capacitance to ground introduced by the connection line and the load on the node.

FIG. 2 is a known timing diagram for controlling a conventional ramp conversion circuit.

FIG. 3 is a ramp conversion circuit for a two-step single-slope single-slope integral analog-to-digital converter of the present invention.

Fig. 4 is the slope conversion circuit for the two-step single-slope single-slope integral analog-to-digital converter of the present invention. In order to describe the principle, the equivalent parasitic capacitance to ground introduced by the connection line and the load on the node in the dotted line box is added .

FIG. 5 is a timing diagram for controlling the slope conversion circuit of the present invention.

Detailed ways

For ease of understanding, the present invention will be described in detail below in conjunction with specific drawings and embodiments. It should be noted that Fig. 3 and Fig. 5 are only examples of implementation of the present invention, and the form and details of specific implementation within the scope of claims of the present invention are not limited to Fig. 3 and Fig. 5 . For anyone who is familiar with integrated circuit design technology, it can be known that the examples of Fig. 3 and Fig. 5 described in the present invention can make various amendments and changes within the scope of the present invention according to the description herein, and these amendments and changes are also included in the present invention In the range.

Fig. 1 is the circuit schematic diagram of known two-step integral type analog-to-digital converter, including: traditional slope conversion circuit 101, comparator 102, latch and adder 103, counting and controller 104, and slope signal generator 105. In Figure 1, V _IN is the input signal to be quantized, V _ramp,in is the input ramp signal, V _ramp,out is the output ramp signal, and D<B-1,0> is the output B-bit digital code. The three switches complete the two-step conversion under the control of the timing signals shown in Figure 2. There are gain errors in both cases. The first case is that when the first high-level conversion is performed until the input ramp signal is just greater than the signal to be quantized, S ₁₃ is turned off. At this time, the ramp signal is still input by S ₁₁ , causing the node D voltage to change ΔV _D , so that the node The E voltage change ΔV _E , due to the parasitic capacitance C _PE of the node E to the ground, will cause the gain of the transfer function to be less than 1, expressed as follows:

.

The second case is that when the first step is switched to the second step and the second step is low-level conversion, the voltage change ΔV E of node _E causes the voltage change ΔV _D of node D, because there is a parasitic capacitance C _PD at point D to ground , will result in a transfer function gain less than 1, expressed as follows:

。

.

The first case can be avoided by turning off S ₁₁ immediately after turning off S ₁₃ in a traditional ramp switching circuit, but the gain error generated in the second case cannot be eliminated by changing the timing only. This gain error will cause the analog-to-digital conversion result to appear non-monotonic. On the other hand, since the above gain is determined by the absolute value of the capacitor, and the absolute value has a deviation of 20% to 30% when the integrated circuit is implemented, the gain variation range is relatively large. The slope conversion circuit of the present invention will replace the traditional slope conversion circuit 101 to solve the above-mentioned problem of gain error.

Fig. 3 is an embodiment of the slope conversion circuit applied to the two-step integral analog-to-digital converter of the present invention. Fig. 4 is for the convenience of the following description. The equivalent ground parasitic capacitance introduced by the line and (or) load. The slope conversion circuit includes: an operational amplifier A1, a pair of sampling capacitors _CH1 and _CH2 , a pair of parasitic balancing capacitors C _M1 and C _M2 , six switches S ₁ , S ₂ , S ₃ , S ₄ , S ₅ , S ₆ . V _{ramp, in} is the input ramp signal, V _{ramp, out} is the output ramp signal. The two sampling capacitors should be matched equally and have a nominal value of _CH , namely: _CH1 = _CH2 = _CH . One end of a pair of parasitic balancing capacitors (C _M1 and C _M2 ) is grounded, and the other end is respectively connected to the negative input terminal (X) of the operational amplifier and the output terminal (A) of the slope conversion circuit, which is used to adjust the operational amplifier in Figure 4 The equivalent ground-to-ground parasitic capacitance C _P1 of the negative input terminal (X) and the equivalent ground-to-ground parasitic capacitance C _P2 of the slope conversion circuit output terminal (A) make the above two nodes have equal ground-to-ground capacitance and the nominal value is C _P , namely: C _P1 +C _M1 = C _P2 +C _M2 =C _P . The sum of the sampling capacitance and the capacitance to ground is called the total capacitance ( _CH + C _P ), so the above two nodes have the same total capacitance.

FIG. 5 is an embodiment of the timing sequence applicable to the slope conversion circuit of the present invention, which is used to control the six switches in FIG. 3 , so as to control the operation mode of the operational amplifier and the access mode of the input ramp signal. An analog-to-digital conversion cycle consists of the first step of high M-bit conversion and the second step of low N-bit conversion; in the first step of high M-bit conversion, the operational amplifier works successively in sampling mode and hold mode, and in the second step of low N-bit conversion The operational amplifier works in follower mode. Note that _S6 turn-off can occur at any time after the holdover voltage has stabilized and before the end of holdover mode.

According to FIG. 4 and FIG. 5 , the specific principle of eliminating the gain error by the slope conversion circuit of the present invention can be described as follows. The voltage change ΔV _B at the positive input terminal (B) of the operational amplifier caused by the first-to-second-step switching and the second-step conversion of the analog-to-digital converter is transferred to its output by the operational amplifier in follower mode (Y), resulting in ΔV _Y , because there is a ground capacitance (C _P1 +C _M1 ) at the negative input terminal (X) of the operational amplifier, the gain of the transfer function is greater than 1, expressed as:

。

.

According to the principle of charge conservation, ΔV _Y will continue to be transmitted to the output terminal of the slope conversion circuit, and the resulting voltage change is ΔV _A , because the floating plate (A) of the sampling capacitor (C _H2 ) has a ground capacitance (C _P2 + C _M2 ), then the gain of the transfer function is less than 1, expressed as:

。

.

So the overall gain of the transfer function for the voltage change is,

.

Ideally, as above, C _H1 =C _H2 = _CH and C _P1 +C _M1 =C _P2 +C _M2 =C _P , so the gains of the two stages are reciprocals of each other, so the total gain of the voltage change is 1. However, in the implementation process, there are small deviations ΔC _H and ΔC _P due to capacitance matching and other reasons, and the total gain is as follows:

.

Since ΔC _H / _CH and ΔC _P /C _P are relative deviations, both can be controlled at about ±1% when implemented in an integrated circuit, so the total gain is still very close to 1.

Claims (5)

1. a slope change-over circuit that is applied to two-step integral analogue-to-digital converter, is characterized in that comprising: an operational amplifier (A1), a pair of sampling capacitance (C _h1and C _h2), a pair of parasitic balancing capacitance (C _m1and C _m2) and six switch (S ₁, S ₂, S ₃, S ₄, S ₅, S ₆); Input ramp signal is on the one hand successively through the first switch (S ₁) and the 6th switch (S ₆) be connected to the output of slope change-over circuit, on the other hand by second switch (S ₂) be connected to the positive input terminal of operational amplifier; The positive input terminal of operational amplifier is by the 3rd switch (S ₃) be connected with reference level; The negative input end of operational amplifier, on the one hand by the 4th switch (S ₄) be connected to the output of operational amplifier, on the other hand successively through the first sampling capacitance (C _h1) and the 5th switch (S ₅), be connected to the output of operational amplifier; The output of operational amplifier is successively through the 5th switch (S ₅) and the second sampling capacitance (C _h2), be connected to the output of slope change-over circuit; The second sampling capacitance (C _h2) two pole plates by the 6th switch (S ₆) be connected; The first parasitic balancing capacitance (C _m1) a pole plate ground connection, another pole plate is connected with the negative input end of operational amplifier; The second parasitic balancing capacitance (C _m2) a pole plate ground connection, another pole plate is connected with the output of slope change-over circuit.

2. the slope change-over circuit that is applied to two-step integral analogue-to-digital converter according to claim 1, is characterized in that:

Two sampling capacitance couplings equate; Two parasitic balancing capacitances, for the equivalence that the regulates operational amplifier negative input end equivalence parasitic capacitance over the ground of parasitic capacitance and slope change-over circuit output over the ground, make described input and described output have equal direct-to-ground capacitance; Sampling capacitance and direct-to-ground capacitance sum are called total capacitance, and the total capacitance of above-mentioned input and output is called the first total capacitance and the second total capacitance; So the first total capacitance and the second total capacitance equate.

3. the slope change-over circuit that is applied to two-step integral analogue-to-digital converter according to claim 1, it is characterized in that: when the high-order analog-to-digital conversion of the first step starts, input ramp signal is directly linked the output of slope change-over circuit by switch, input ramp signal simultaneously and sampled by the first sampling capacitance, two pole plates of the second sampling capacitance are shorted to the output of slope change-over circuit by switch.

4. the slope change-over circuit that is applied to two-step integral analogue-to-digital converter according to claim 3, is characterized in that: the input mode of input ramp signal in the change-over circuit of slope is by first, second and the 6th (S ₁, S ₂and S ₆) three switches control:

(1) when the high-order analog-to-digital conversion of the first step starts, the first switch (S ₁) and the 6th switch (S ₆) conducting, second switch (S ₂) turn-off, input ramp signal is connected to the output of slope change-over circuit, the direct output signal as slope change-over circuit; Input ramp signal is simultaneously by the first sampling capacitance (C _h1) sampling; The second sampling capacitance (C _h2) two pole plates by the 6th switch (S ₆) be shorted to the output of slope change-over circuit;

(2) the high-order analog-to-digital sampling process of the first step is continued until that input ramp signal finishes while being just greater than the input signal of analog to digital converter, the first switch (S ₁) and second switch (S ₂) all turn-off, input ramp signal is no longer input in the change-over circuit of slope; Now operational amplifier enters Holdover mode, and its output keeps the magnitude of voltage that voltage is the input ramp signal that finally samples; The second sampling capacitance (C _h2) after operational amplifier output foundation is stable, the 6th switch (S between two pole plates ₆) turn-off, one of them pole plate is connected with operational amplifier output terminal, and another pole plate floats sky and does the output of slope change-over circuit; The second sampling capacitance (C now _h2) voltage of two pole plates is maintenance voltage;

(3) during second step low level analog-to-digital conversion, the first switch (S ₁) turn-off second switch (S ₂) conducting, input ramp signal is input to the positive input terminal of operational amplifier, and now operational amplifier is in follow the mode, and operational amplifier is delivered to the change in voltage of operational amplifier positive input terminal the output of operational amplifier; According to principle of charge conservation, be more further delivered to the second sampling capacitance (C _h2) floating empty pole plate on, and keep on voltage, as the output signal of slope change-over circuit in this first step that is added to.

5. according to the slope change-over circuit that is applied to two-step integral analogue-to-digital converter described in claim 2 or 4, it is characterized in that: the change in voltage of operational amplifier positive input terminal is delivered to the output of slope change-over circuit by the transfer function of two cascades:

(1) first order is that operational amplifier in follow the mode is delivered to the change in voltage of operational amplifier positive input terminal the output of operational amplifier, and the gain of first order transfer function equals the ratio of the first total capacitance and the first sampling capacitance;

(2) second level is the output that the change in voltage of operational amplifier output terminal is transmitted slope change-over circuit, and the gain of second level transfer function equals the ratio of the second sampling capacitance and the second total capacitance;

Because above-mentioned two sampling capacitances are equal respectively with two total capacitances, above-mentioned two stage gains are reciprocal each other; And two stage gains are multiplied each other for overall gain, so the overall gain of the change in voltage transfer function of above-mentioned slope change-over circuit equals one.

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