CN104506194B - For arranging the shared active slope conversion circuit of parallel two-step analog-digital converter - Google Patents
For arranging the shared active slope conversion circuit of parallel two-step analog-digital converter Download PDFInfo
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- CN104506194B CN104506194B CN201410753991.0A CN201410753991A CN104506194B CN 104506194 B CN104506194 B CN 104506194B CN 201410753991 A CN201410753991 A CN 201410753991A CN 104506194 B CN104506194 B CN 104506194B
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Abstract
The invention belongs to row parallel architecture analog-digital converter technical field, the specially one shared active slope conversion circuit for being used for row parallel architecture two-step analog-digital converter.The shared active slope conversion circuit of the present invention includes active switch capacitance module and passive switch capacitance module two parts.Active switch capacitor module is made up of an operational amplifier, the sampling capacitance of one, a parasitic balancing capacitance and six switches, and its working condition is unrelated with measured signal；Passive switch capacitance module is made up of a sampling capacitance, a parasitic balancing capacitance and a switch, and its working condition is decided by measured signal.When shared active slope conversion circuit is applied to row parallel architecture, an active switch capacitor module is shared by the parallel passive switch capacitance module of row.The present invention can effectively reduce the power consumption and area of row parallel architecture two-step analog-digital converter.
Description
Technical field
The invention belongs to row parallel architecture analog-digital converter technical field, and in particular to integrated circuit be used for arrange parallel frame
The slope conversion circuit of structure two-step analog-digital converter.
Background technology
In known circuits, two-step list ramp single-slope integral analogue-to-digital converter principle is as shown in figure 1, its effect
It is by measured signal VINIt is quantified as B bit digitals output D<B-1,0>.It is by traditional slope conversion circuit 110, comparator 120, lock
Deposit and adder 130, counting and controller 140 and ramp signal generator 150（Generally realized with digital analog converter）.By
In traditional slope conversion circuit 110 be a passive circuit, so herein referred to as passive slope conversion circuit.It is by an electricity
Hold C11And SD、SE、SRThree switch compositions, its course of work are as follows：In the high M positions conversion of the first step, ramp signal generator
The 150 big stepped-slope signals of output pass through SDWith C11Top crown D is connected, and directly with measured signal VINEntered by comparator 120
Row compares, when 120 output switching activity of comparator, C11Top crown D is sampled and is stored ramp signal at that time；The low N positions of second step turn
Change, the small stepped-slope signal that ramp signal generator 150 exports（1/2 when its ladder height is the first stepN）Pass through SEWith
C11Bottom crown E be connected, according to law of conservation of charge, on the top crown D of floating, the voltage change and first on bottom crown E
Step storage voltage is overlapped, then compared with measured signal is in comparator 120.
The shortcomings that passive slope conversion circuit, is：Due to parasitic capacitance C at pole plate D during second stepPDPresence, cause pole
Voltage change at plate E can not be delivered to pole plate D in a manner of gain is one, so as to cause gain error, work as CPD/C11Enough
It will cause the non-linear of analog-to-digital conversion when big.
The problem of for above-mentioned gain error,《Change electricity in a kind of slope applied to two-step integral analogue-to-digital converter
Road》（China, publication number：CN103746694A, publication date：On April 23rd, 2014）Propose a kind of comprising operational amplifier
Slope conversion circuit, because it is an active circuit, so herein referred to as active slope conversion circuit.It can be divided into
One active switch capacitor module and a passive switch capacitance module two parts, as shown in Figure 2：Active switch capacitor module bag
Include operational amplifier A 0, sampling capacitance CHX, parasitic balancing capacitance CMXWith S01、S02、S03、S04、S05Five switches；Passive switch electricity
Molar block includes sampling capacitance CHA, parasitic balancing capacitance CMAWith S01、S06Two switches.For the transmission function of voltage change, have
The gain of source slope converter is equal to the product of two module gains, because the gain of two modules in the ideal case is fallen each other
Number, so active slope transducer gain is constantly equal to one.
The shortcomings that above-mentioned active slope conversion circuit, is：At the time of active switch capacitor module enters latch mode and institute
The voltage of holding is all the function of measured signal, therefore its course of work is related to measured signal.This shortcoming is applied at it
Just highlighted during row parallel architecture：Active switch capacitor module comprising operational amplifier must be a pair with measured signal 1
Should, cause active switch capacitor number of modules to be necessarily equal to columns（The measured signal number inputted parallel）.So, on the one hand significantly
The power consumption and area of row parallel architecture are added, on the other hand, has tightened up the pact to operational amplifier precision, speed and power consumption
Beam, add the design difficulty of operational amplifier.
The content of the invention
When being applied to row parallel architecture for above-mentioned active slope conversion circuit, the problem of existing power consumption and area, this
Invention provides a kind of shared active slope conversion circuit, the course of work and the letter to be measured of active switch capacitor module therein
It is number unrelated, the shared of active switch capacitor module is realized, so as to which power consumption when solving the application of row parallel architecture and area are asked
Topic.
Shared active slope conversion circuit provided by the invention, as shown in figure 3, including an active switch capacitor module
310 and N number of passive switch capacitance module 320.K, K=1,2 ..., N；
Active switch capacitor module includes 1, sampling capacitance C of an operational amplifier AH0, a parasitic balancing capacitance
CM0With six switch S2、S3、S4、S5、S6、S7；The passive switch capacitance module 320.K includes a sampling capacitance CHK, one
Parasitic balancing capacitance CMKWith a switch S1K, K=1,2 ..., N；
The active switch capacitor module 310 includes the first datum input VREFP, the second datum input VREFNWith
Ramp input VRAThree inputs, and an output end VAO；Ramp input VRAV is inputted with the first datumREFPLead to respectively
Cross second switch S2With the 3rd switch S3It is connected to the positive input terminal B of operational amplifier A 1；Second datum inputs VREFN, lead to
Cross the 6th switch S6With the 0th sampling capacitance CH0The negative input end X of operational amplifier is connected to, while passes through the 6th switch S6With
7th switch S7It is connected to output end VAO；The negative input end X of operational amplifier A 1, pass through the 4th switch S4It is connected to operation amplifier
Device A1 output end O, while negative input end X passes through the 0th sampling capacitance C successivelyH0With the 5th switch S5It is connected to operational amplifier
Output end O, again by the 0th parasitic balancing capacitance CM0It is connected to ground；
The passive switch capacitance module 320.K includes ramp input VRPKV is inputted with reference to pole plateCHKTwo inputs,
An and slope output VROK；Ramp input VRPKSwitch S is arranged by K1KIt is connected to slope output VROK, K row sampling capacitances
CHKA pole plate connection with slope output VROKIt is connected, referred to as exports pole plate, another pole plate and reference pole plate input VCHK
It is connected, referred to as with reference to pole plate；K-th parasitism balancing capacitance CMKA pole plate and slope output VROKIt is connected, another pole plate connects
It is connected to ground；
When the shared active slope conversion circuit composition N row parallel architectures, including a ramp input and it is N number of tiltedly
Slope exports；The ramp input V of the active switch capacitor moduleRAWith the ramp input V of N number of passive switch capacitance moduleRP1~VRPN
It is joined directly together, the ramp input V as the N row parallel architectureRIN；The slope output V of N row passive switch capacitance modulesRO1 ~
VRONSlope output end as the N row parallel architecture；320.1 ~ 320.N of N row passive switch capacitance modules reference pole plate is defeated
Enter VCH1~VCHNIt is joined directly together, referred to as shared node Z；The output end V of the active switch capacitor moduleAOIt is direct with shared node Z
It is connected, so as to be shared by N number of passive switch capacitance module.
In the present invention, the shared active slope conversion circuit course of work of N row parallel architectures is as follows：
（1）When first step high position analog-to-digital conversion starts：Active switch capacitor module is configured as sampling configuration；Second ginseng
Examine level VREFNOn the one hand it is connected by the switch of conducting with shared node Z, on the other hand by active switch capacitor module samples；
Ramp input VRINPass through the N row switches S of conducting11~S1NRespectively with N row slope output end VRO1~VRONIt is connected, directly as each
The output of row；
（2）In first step high position analog-digital conversion process：N row passive switch capacitance modules are operated independently of each other,
Ramp input signal VRINOnce higher than the measured signal of K row, K row switches S1KDisconnect immediately, the moment instantaneous slope is defeated
Enter the K row output pole plates V that level is stored in floatingROKOn, the voltage is the function of K row measured signals, is designated as VRL(K)；
（3）At the end of first step high position analog-to-digital conversion：Active switch capacitor module is configured as latch mode, and computing is put
Big device A1 output end O is connected by the switch of conducting with shared node Z；Connect the second datum VREFNWith shared node Z
Switch off, the second datum VREFNFirst latched by operational amplifier A 1 after, then the output end O through operational amplifier A 1 with
Shared node Z is connected；
（4）In second step low level analog-to-digital conversion：Active switch capacitor module is configured as follow the mode, ramp input
VRINPass through the second switch S of conducting2It is connected with the positive input terminal B of operational amplifier A 1 in active switch capacitor module, slope is defeated
Enter VRINCaused voltage change is delivered to shared by input B, the output end O of operational amplifier of operational amplifier successively
Node Z；Then, according to principle of charge conservation, in each row sampling capacitance CHKOutput pole plate on the level V that is kept with itRL
(K) it is superimposed, output V is arranged as KROK。
In the present invention, the course of work in active switch capacitor module is unrelated with measured signal：In first step high position modulus
It is configured as sampling configuration during conversion, to the second datum VREFNSampled；It is configured as at the end of the first step
Latch mode, to the second datum VREFNKept；In second step low level analog-to-digital conversion, it is configured as follow the mode,
To common ramp input VRINFollowed.And the course of work of passive switch capacitance module is then related to measured signal, it is opened
It is measured signal function to turn off magnitude of voltage at the time of opening and preserved.
In the present invention, in N number of passive switch capacitance module and its shared active switch capacitor module, parasitism balance
Electric capacity CMK（K=0,1,2,…,N）Parasitic capacitance is added over the ground with the node, is obtained the total capacitance over the ground of the node, is designated as CGK（K
=0,1,2,…,N）；The sampling capacitance of modules is in equal proportions with total capacitance over the ground, i.e. CH0/CG0=CHK/CGK（K=1,2,…,
N）, make voltage change by gain be from ramp input end V in a manner of oneRINIt is delivered to the slope output end V of each rowRO1 ~VRON。
It is a kind of by the active switch capacitor module unrelated to signal and related with signal the beneficial effects of the invention are as follows providing
Passive switch capacitance module composition shared active slope conversion circuit, when it is applied to row parallel architecture, one has
Source switch capacitance module can be shared by several passive switch capacitance modules；Put because active switch capacitor module includes computing
Big device and electric capacity, therefore effectively reduce the power consumption and area of row parallel architecture, also reduce the design difficulty of operational amplifier.
Brief description of the drawings
Fig. 1 is that the known two-step list ramp single-slope integral analogue-to-digital converter using passive slope conversion circuit is former
Reason figure.
Fig. 2 is known active slope conversion circuit.
Fig. 3 is the shared active slope conversion circuit of row parallel architecture of the present invention.
Fig. 4 is the shared active slope conversion circuit of row parallel architecture of the present invention, in order to describe principle, adds node
On by line and load introduce equivalent parasitic capacitance over the ground, represented with grey font and lines.
Fig. 5 is the timing diagram of the shared active slope conversion circuit of row parallel architecture of the present invention.
Embodiment
In order to make it easy to understand, the present invention is described in detail below with reference to specific drawings and embodiments.Need
It is noted that Fig. 3 and Fig. 5 are only the implementation examples of the present invention, the form of the specific implementation in scope of the invention as claimed
Fig. 3 and Fig. 5 are not limited to details.For the personnel of any known IC design technology, it is known that Fig. 3 and figure of the present invention
5 each examples can make a variety of amendments and change within the scope of the present invention according to illustrating herein, these amendments and change
Also include in the scope of the present invention.
Fig. 3 is a kind of embodiment of the shared active slope conversion circuit of the present invention, including an active switch capacitor
Module（310）With N number of passive switch capacitance module（320.1~320.N）；Active switch capacitor module includes an operation amplifier
Device A1, a sampling capacitance CH0, a parasitic balancing capacitance CM0With six switch S2、S3、S4、S5、S6、S7；K-th（Wherein K=
1,2,…,N）Passive switch capacitance module includes a sampling capacitance CHK, a parasitic balancing capacitance CMKWith a switch S1K。
Active switch capacitor modules A is shared by N number of passive switch capacitance module, constitutes the parallel framework of row.
Fig. 4 be in order to which following description is convenient, added on the basis of Fig. 3 on node introduced by line and load it is equivalent
Parasitic capacitance C over the groundPK（Wherein K=0,1 ..., N）, represented with grey font and lines；CPKWith corresponding parasitic balancing capacitance
CMK, the total capacitance over the ground of the node is collectively constituted, is designated as：CGK =CMK+CPK。
Fig. 5 applies to a kind of embodiment of the shared active slope conversion circuit sequential of the present invention, each switch
Worked under SECO：（1）Switch in N row passive switch capacitance modules（S11~S1N）Work independently from each other：In the first step
N row switches when high M positions conversion starts（S11To S1N）Simultaneously turn on, allow ramp input signal directly compared with each row measured signal；
In the high M positions transfer process of the first step, arranged for K, when ramp input signal is higher than K row measured signals, K row switches
（S1K）Shut-off；During the high M positions conversion end of the first step, the switch of all row（S11To S1N）To successively it be turned off, and by off state
It is continued until the low N positions conversion end of second step.
（2）S is switched in active switch capacitor module2、S3、S4、S5、S6The course of work it is unrelated with measured signal, matched somebody with somebody
It is set to different mode：In the high M positions conversion of the first step, active switch capacitor module is configured as sampling configuration, always to second
Datum is sampled；At the end of the first step, active switch capacitor module is configured as holding pattern to the second datum
Latched；When the low N positions of second step are changed, S2Conducting, S3Shut-off, ramp input signal are connected to the just defeated of operational amplifier A 1
Enter end（B）, transport active switch capacitor module and be configured as follow the mode, operational amplifier positive input terminal（B）Voltage change transmission
Its output end（O）, then the C by each rowHKIt is delivered to the output of each row.
（3）The switch S of active switch capacitor module7In the high M positions conversion of the first step, when opening for passive switch capacitance module
Close S1KOf short duration off state is in before and after shut-off, to ensure to be injected into C by switchHKThe electric charge of pole plate is unrelated with signal；S7
Other moment are then constantly in conducting state.
In shared active slope conversion circuit, when active switch capacitor module is in follow the mode, voltage is become
The overall gain of the transmission function of change is one, and concrete principle can be described as follows.The active switch capacitor module is in the first step to
Cause operational amplifier positive input terminal B voltage change in the switching of two steps and second step transfer process, be designated as Δ VRIN, follow mould
The active switch capacitor module of formula is by Δ VRINIt is delivered to the output end of operational amplifier（O）, and be delivered to by the switch of conducting
Shared node Z, caused voltage change are designated as Δ VZ, due to operational amplifier negative input end（X）Direct-to-ground capacitance be present is CG0=CM0
+CP0, then the gain of the transmission function be more than 1, be expressed as：
According to principle of charge conservation, Δ VZContinue to be delivered to the slope output end V of each rowROK, caused each row
Slope output end voltage, which becomes, turns to Δ VROK, due to sampling capacitance CHKIt is C that output pole plate, which equally exists direct-to-ground capacitance,GK =CMK+CPK,
Then the gain of the transmission function is less than 1, is expressed as：
So it is to the overall gain of the transmission function of voltage change：
As long as ensure：
For all K=1,2 ..., N is set up, then the overall gain of voltage change is just constantly equal to one.
Claims (3)
1. a kind of shared active slope conversion circuit for being used to arrange parallel two-step analog-digital converter, it is characterised in that including one
Individual active switch capacitor module（310）With N number of passive switch capacitance module（320.K）；
Active switch capacitor module（310）Including an operational amplifier（A1）, a sampling capacitance（CH0）, a parasitic balance
Electric capacity（CM0）With six switches（S2、S3、S4、S5、S6、S7）；Passive switch capacitance module（320.K）Including a sampling capacitance
（CHK）, a parasitic balancing capacitance（CMK）With a switch（S1K）, K=1,2 ..., N；
The active switch capacitor module（310）Inputted including the first datum（VREFP）, the second datum input（VREFN）
Inputted with first slope（VRA）Three inputs, and an output end（VAO）；First slope inputs（VRA）With first with reference to electricity
Flat input（VREFP）Pass through second switch respectively（S2）With the 3rd switch（S3）It is connected to operational amplifier（A1）Positive input terminal
（B）；Second datum inputs（VREFN）, pass through the 6th switch（S6）And sampling capacitance（CH0）It is connected to the negative of operational amplifier
Input（X）, while pass through the 6th switch（S6）With the 7th switch（S7）It is connected to output end（VAO）；Operational amplifier（A1）'s
Negative input end（X）, pass through the 4th switch（S4）It is connected to operational amplifier output terminal（O）, while negative input end（X）Pass through successively
Sampling capacitance（CH0）With the 5th switch（S5）It is connected to operational amplifier output terminal（O）, again by parasitic balancing capacitance（CM0）
It is connected to ground；
The passive switch capacitance module（320.K）Including the second ramp input（VRPK）Inputted with reference to pole plate（VCHK）Two defeated
Enter end, and a slope output（VROK）；Second ramp input（VRPK）Arranged and switched by K（S1K）It is connected to slope output
（VROK）, K row sampling capacitances（CHK）A pole plate connection with slope export（VROK）It is connected, referred to as exports pole plate, another
Pole plate with reference to pole plate with inputting（VCHK）It is connected, referred to as with reference to pole plate；K-th parasitism balancing capacitance（CMK）A pole plate with tiltedly
Slope exports（VROK）It is connected, another pole plate is connected to ground；
When the shared active slope conversion circuit composition N row parallel architectures, including a ramp input and N number of slope it is defeated
Go out；The first slope input of the active switch capacitor module（VRA）With the second ramp input of N number of passive switch capacitance module
（VRP1~VRPN）It is joined directly together, total ramp input as the N row parallel architecture（VRIN）；N row passive switch capacitance modules
Slope exports（VRO1 ~VRON）Slope output end as the N row parallel architecture；N row passive switch capacitance modules（320.1~
320.N）Reference pole plate input（VCH1~VCHN）It is joined directly together, referred to as shared node（Z）；The active switch capacitor module
Output end（VAO）With shared node（Z）It is joined directly together, so as to be shared by N number of passive switch capacitance module.
2. shared active slope conversion circuit as claimed in claim 1, it is characterised in that the circuit course of work is as follows：
（1）When first step high position analog-to-digital conversion starts：Active switch capacitor module is configured as sampling configuration；Second with reference to electricity
It is flat（VREFN）On the one hand the switch and shared node of conducting are passed through（Z）It is connected, on the other hand by active switch capacitor module samples；
Total ramp input（VRIN）Switch is arranged by the N of conducting（S11~S1N）Respectively with N row slope output end（VRO1~VRON）It is connected, directly
Output as each row；
（2）In first step high position analog-digital conversion process：N row passive switch capacitance modules are operated independently of each other, total oblique
Slope input signal（VRIN）Once higher than the measured signal of K row, K row switches（S1K）Disconnect immediately, by the moment instantaneous slope
Incoming level is stored in the K row output pole plates of floating（VROK）On, the level is the function of K row measured signals, is designated as VRL
(K)；
（3）At the end of first step high position analog-to-digital conversion：Active switch capacitor module is configured as latch mode, operational amplifier
Output end（O）Pass through the switch and shared node of conducting（Z）It is connected；Connect the second datum（VREFN）With shared node（Z）
Switch off, the second datum（VREFN）First by operational amplifier（A1）After latch, then through operational amplifier output terminal（O）
With shared node（Z）It is connected；
（4）In second step low level analog-to-digital conversion：Active switch capacitor module is configured as follow the mode, total ramp input
（VRIN）Pass through the second switch of conducting（S2）With operational amplifier in active switch capacitor module（A1）Positive input terminal（B）Phase
Even, total ramp input（VRIN）Caused voltage change passes through the positive input terminal of operational amplifier successively（B）, operational amplifier it is defeated
Go out end（O）It is delivered to shared node（Z）；Then, according to principle of charge conservation, in each row sampling capacitance（CHK）Output pole plate
Upper and its level V for being keptRL(K) it is superimposed, arranges and export as K（VROK）.
3. shared active slope conversion circuit as claimed in claim 1, it is characterised in that the active switch capacitor module
In the course of work it is unrelated with measured signal：In first step high position analog-to-digital conversion, it is configured as sampling configuration, joins to second
Examine level（VREFN）Sampled；It is configured as latch mode at the end of the first step, to the second datum（VREFN）Carry out
Keep；In second step low level analog-to-digital conversion, it is configured as follow the mode, to common total ramp input（VRIN）Carry out with
With；And the course of work of passive switch capacitance module is then related to measured signal, electricity at the time of it is switched off with being preserved
Pressure value is measured signal function.
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| CN201410753991.0A CN104506194B (en) | 2014-12-11 | 2014-12-11 | For arranging the shared active slope conversion circuit of parallel two-step analog-digital converter |
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| US10062450B1 (en) * | 2017-06-21 | 2018-08-28 | Analog Devices, Inc. | Passive switched capacitor circuit for sampling and amplification |
| CN113285714B (en) * | 2021-04-02 | 2024-02-02 | 西安理工大学 | Parallel two-step type single-inclined analog-to-digital conversion circuit and method adopting interval fine slope |
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| CN103746694A (en) * | 2014-01-14 | 2014-04-23 | 复旦大学 | Slope conversion circuit applied to two-step type integral analog-to-digital converter |
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