CN104506194A - Shared type active slope conversion circuit used for column parallel two-step type analog-digital converter - Google Patents
Shared type active slope conversion circuit used for column parallel two-step type analog-digital converter Download PDFInfo
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- CN104506194A CN104506194A CN201410753991.0A CN201410753991A CN104506194A CN 104506194 A CN104506194 A CN 104506194A CN 201410753991 A CN201410753991 A CN 201410753991A CN 104506194 A CN104506194 A CN 104506194A
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- slope
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Abstract
The invention belongs to the technical field of a column parallel framework analog-digital converter and particularly provides a shared type active slope conversion circuit used for a column parallel two-step type analog-digital converter. The shared type active slope conversion circuit used for the column parallel two-step type analog-digital converter comprises two parts, namely an active switched capacitor module and passive switched capacitor modules. The active switched capacitor module is composed of an operational amplifier, a sampling capacitor, a parasitic balance capacitor and six switches, and the working state is not related with a signal to be detected; each passive switched capacitor module is composed of a sampling capacitor, a parasitic balance capacitor and a switch, and the working state is determined by the signal to be detected. When the shared type active slope conversion circuit is applied to a column parallel framework, the column parallel passive switched capacitor modules share one active switched capacitor module. With the adoption of the shared type active slope conversion circuit, the power consumption and the area of the column parallel two-step type analog-digital converter can be effectively reduced.
Description
Technical field
The invention belongs to row parallel architecture analog to digital converter technical field, be specifically related to the slope conversion circuit for row parallel architecture two-step analog to digital converter of integrated circuit.
Background technology
In known circuits, as shown in Figure 1, its effect is by measured signal V to two-step list ramp single-slope integral analogue-to-digital converter principle
iNbe quantified as B bit digital and export D<B-1,0>.It is realized with digital to analog converter usually by traditional slope conversion circuit 110, comparator 120, latch and adder 130, counting and controller 140 and ramp signal generator 150().Because traditional slope conversion circuit 110 is passive circuits, so be referred to as passive slope conversion circuit herein.It is by an electric capacity C
11and S
d, S
e, S
rthree switch compositions, its course of work is as follows: when changing in first step height M position, and ramp signal generator 150 exports large stepped-slope signal and passes through S
dwith C
11top crown D is connected, and direct and measured signal V
iNcompared by comparator 120, when comparator 120 output switching activity, C
11top crown D samples and stores ramp signal at that time; Second step low N position conversion, the little stepped-slope signal (when its ladder height is the first step 1/2 that ramp signal generator 150 exports
n) pass through S
ewith C
11bottom crown E be connected, according to law of conservation of charge, on the top crown D of floating, the change in voltage on bottom crown E superposes with first step storage voltage, then compares at comparator 120 with measured signal.
The shortcoming of passive slope conversion circuit is: due to pole plate D place parasitic capacitance C during second step
pDexistence, cause the mode that the change in voltage at pole plate E place cannot be with gain to be delivered to pole plate D, thus cause gain error, work as C
pD/ C
11to cause analog-to-digital non-linear time enough large.
For the problem of above-mentioned gain error, " a kind of slope conversion circuit being applied to two-step integral analogue-to-digital converter " (China, publication number: CN103746694A, publication date: on April 23rd, 2014) propose a kind of slope conversion circuit comprising operational amplifier, because it is an active circuit, so be referred to as active slope conversion circuit herein.It can be divided into an active switch capacitor module and passive switch capacitance module two parts, as shown in Figure 2: active switch capacitor module comprises operational amplifier A 0, sampling capacitance C
hX, parasitic balancing capacitance C
mXwith S
01, S
02, S
03, S
04, S
05five switches; Passive switch capacitance module comprises sampling capacitance C
hA, parasitic balancing capacitance C
mAwith S
01, S
06two switches.For the transfer function of change in voltage, the gain of active slope transducer equals the product of two module gains, because the gain of two modules is in the ideal case reciprocal each other, so active slope transducer gain is constantly equal to one.
The shortcoming of above-mentioned active slope conversion circuit is: the moment that active switch capacitor module enters latch mode and the voltage kept are all the functions of measured signal, and therefore its course of work is relevant to measured signal.This shortcoming just highlights when it is applied to row parallel architecture: comprise operational amplifier active switch capacitor module must with measured signal one_to_one corresponding, cause active switch capacitor number of modules must equal columns (parallel input measured signal number).Like this, considerably increase power consumption and the area of row parallel architecture on the one hand, on the other hand, tightened up the constraint to operational amplifier precision, speed and power consumption, added the design difficulty of operational amplifier.
Summary of the invention
When being applied to row parallel architecture for above-mentioned active slope conversion circuit, the power consumption existed and the problem of area, the invention provides a kind of shared active slope conversion circuit, the course of work of active switch capacitor module wherein and measured signal have nothing to do, achieve sharing of active switch capacitor module, thus the power consumption solved when row parallel architecture is applied and area for cutting.
Shared active slope conversion circuit provided by the invention, as shown in Figure 3, comprises an active switch capacitor module 310 and N number of passive switch capacitance module 320.K, K=1,2 ..., N;
Active switch capacitor module comprises an operational amplifier A 1, sampling capacitance C
h0, a parasitic balancing capacitance C
m0with six switch S
2, S
3, S
4, S
5, S
6, S
7; Described passive switch capacitance module 320.K comprises a sampling capacitance C
hK, a parasitic balancing capacitance C
mKwith a switch S
1K, K=1,2 ..., N;
Described active switch capacitor module 310 comprises the first reference level input V
rEFP, second reference level input V
rEFNwith ramp input V
rAthree inputs, and an output V
aO; Ramp input V
rAwith the first reference level input V
rEFPrespectively by second switch S
2with the 3rd switch S
3be connected to the positive input terminal B of operational amplifier A 1; Second reference level input V
rEFN, by the 6th switch S
6with the 0th sampling capacitance C
h0be connected to the negative input end X of operational amplifier, simultaneously by the 6th switch S
6with the 7th switch S
7be connected to output V
aO; The negative input end X of operational amplifier A 1, by the 4th switch S
4be connected to the output O of operational amplifier A 1, negative input end X is successively through the 0th sampling capacitance C simultaneously
h0with the 5th switch S
5be connected to the output O of operational amplifier, again by the 0th parasitic balancing capacitance C
m0be connected to ground;
Described passive switch capacitance module 320.K comprises ramp input V
rPKv is inputted with reference to pole plate
cHKtwo inputs, and a slope exports V
rOK; Ramp input V
rPKby K row switch S
1Kbe connected to slope and export V
rOK, K row sampling capacitance C
hKpole plate connect and export V with slope
rOKbe connected, be called output pole plate, another pole plate and reference pole plate input V
cHKbe connected, be called with reference to pole plate; K parasitic balancing capacitance C
mKa pole plate and slope export V
rOKbe connected, another pole plate is connected to ground;
When described shared active slope conversion circuit composition N row parallel architecture, comprise a ramp input and the output of N number of slope; The ramp input V of described active switch capacitor module
rAwith the ramp input V of N number of passive switch capacitance module
rP1~ V
rPNdirectly be connected, as the ramp input V of described N row parallel architecture
rIN; The slope of N row passive switch capacitance module exports V
rO1~ V
rONas the slope output of described N row parallel architecture; The reference pole plate input V of N row passive switch capacitance module 320.1 ~ 320.N
cH1~ V
cHNdirectly be connected, be called shared node Z; The output V of described active switch capacitor module
aOdirectly be connected with shared node Z, thus share by N number of passive switch capacitance module.
In the present invention, the shared active slope conversion circuit course of work of N row parallel architecture is as follows:
(1) when the high-order analog-to-digital conversion of the first step starts: active switch capacitor module is configured to sampling configuration; Second reference level V
rEFNbe connected with shared node Z by the switch of conducting on the one hand, on the other hand by active switch capacitor module samples; Ramp input V
rINby the N row switch S of conducting
11~ S
1Nrespectively with N row slope output V
rO1~ V
rONbe connected, directly as the output of each row;
(2) in the high-order analog-digital conversion process of the first step: N row passive switch capacitance module carries out work, ramp input signal V independently of each other
rINonce the measured signal arranged higher than K, K row switch S
1Kdisconnect immediately, the K row instantaneous for this moment ramp input level being stored in floating export pole plate V
rOKon, this voltage is the function of K row measured signal, is designated as V
rL(K);
(3) at the end of the high-order analog-to-digital conversion of the first step: active switch capacitor module is configured to latch mode, the output O of operational amplifier A 1 is connected with shared node Z by the switch of conducting; Connect the second reference level V
rEFNdisconnect with the switch of shared node Z, the second reference level V
rEFNafter first being latched by operational amplifier A 1, then be connected with shared node Z through the output O of operational amplifier A 1;
(4) when second step low level analog-to-digital conversion: active switch capacitor module is configured to follow the mode, ramp input V
rINby the second switch S of conducting
2be connected with the positive input terminal B of operational amplifier A 1 in active switch capacitor module, ramp input V
rINthe change in voltage produced is delivered to shared node Z through the input B of operational amplifier, the output O of operational amplifier successively; Then, according to principle of charge conservation, at each row sampling capacitance C
hKoutput pole plate on its level V kept
rL(K) superpose, export V as K row
rOK.
In the present invention, the course of work in active switch capacitor module and measured signal have nothing to do: when the high-order analog-to-digital conversion of the first step, it is configured to sampling configuration, to the second reference level V
rEFNsample; At the end of the first step, it is configured to latch mode, to the second reference level V
rEFNkeep; When second step low level analog-to-digital conversion, it is configured to follow the mode, to common ramp input V
rINfollow.The course of work of passive switch capacitance module is then relevant to measured signal, and the moment that its switch disconnects is all measured signal functions with the magnitude of voltage preserved.
In the present invention, in described N number of passive switch capacitance module and shared active switch capacitor module thereof, parasitic balancing capacitance C
mK(K=0,1,2 ..., N) with this node over the ground parasitic capacitance be added, obtain the total capacitance over the ground of this node, be designated as C
gK(K=0,1,2 ..., N); The sampling capacitance of modules and total capacitance are over the ground in equal proportions, i.e. C
h0/ C
g0=C
hK/ C
gK(K=1,2 ..., N), make change in voltage be that a mode is from ramp input end V with gain
rINbe delivered to the slope output V of each row
rO1~ V
rON.
The invention has the beneficial effects as follows and provide a kind of by the active switch capacitor module had nothing to do with signal and the shared active slope conversion circuit formed with the passive switch capacitance module of signal correction, when making it be applied to row parallel architecture, active switch capacitor module can share by several passive switch capacitance module; Because active switch capacitor module includes operational amplifier and electric capacity, therefore effectively reduce power consumption and the area of row parallel architecture, also reduce the design difficulty of operational amplifier.
Accompanying drawing explanation
Fig. 1 is the two-step list ramp single-slope integral analogue-to-digital converter schematic diagram of the passive slope conversion circuit of known employing.
Fig. 2 is known active slope conversion circuit.
Fig. 3 is the shared active slope conversion circuit of row parallel architecture of the present invention.
Fig. 4 is the shared active slope conversion circuit of row parallel architecture of the present invention, in order to describe principle, adding the equivalence parasitic capacitance over the ground that node is introduced by line and load, representing with grey font and lines.
Fig. 5 is the sequential chart of the shared active slope conversion circuit of row parallel architecture of the present invention.
Embodiment
For the ease of understanding, below with reference to concrete drawings and embodiments, the present invention is described in detail.It is pointed out that Fig. 3 and Fig. 5 is only implementation example of the present invention, form and the details of the concrete enforcement within the scope of the claims in the present invention are not limited to Fig. 3 and Fig. 5.For any personnel knowing integrated circuit (IC) design technology, each example of known Fig. 3 and Fig. 5 of the present invention all according to illustrating, can make various different correction and change herein within the scope of the present invention, and these are revised and change is also included in scope of the present invention.
Fig. 3 is a kind of execution mode of the shared active slope conversion circuit of the present invention, comprises an active switch capacitor module (310) and N number of passive switch capacitance module (320.1 ~ 320.N); Active switch capacitor module comprises an operational amplifier A 1, sampling capacitance C
h0, a parasitic balancing capacitance C
m0with six switch S
2, S
3, S
4, S
5, S
6, S
7; K (wherein K=1,2 ..., N) and passive switch capacitance module comprises a sampling capacitance C
hK, a parasitic balancing capacitance C
mKwith a switch S
1K.Active switch capacitor modules A is shared by N number of passive switch capacitance module, constitutes the parallel framework of row.
Fig. 4 is in order to following description is convenient, and the basis of Fig. 3 adds the equivalence parasitic capacitance C over the ground that node is introduced by line and load
pK(wherein K=0,1 ..., N), represent with grey font and lines; C
pKwith corresponding parasitic balancing capacitance C
mK, the total capacitance over the ground of common this node of composition, is designated as: C
gK=C
mK+ C
pK.
Fig. 5 is a kind of execution mode being applicable to the shared active slope conversion circuit sequential of the present invention, and each switch works under sequencing control: the switch (S in (1) N row passive switch capacitance module
11~ S
1N) separate work: the N row switch (S when the conversion of first step height M position starts
11to S
1N) conducting simultaneously, allow ramp input signal directly compare with each row measured signal; In the transfer process of first step height M position, for K row, once ramp input signal higher than K row measured signal, K row switch (S
1K) turn off; During first step height M position EOC, the switch (S of all row
11to S
1N) will successively be turned off, and off state is continued until second step low N position EOC.
(2) active switch capacitor module breaker in middle S
2, S
3, S
4, S
5, S
6the course of work and measured signal have nothing to do, be configured as different mode: when changing in first step height M position, active switch capacitor module is configured to sampling configuration, samples to the second reference level always; At the end of the first step, active switch capacitor module is configured to Holdover mode and latches the second reference level; When the low N position of second step is changed, S
2conducting, S
3turn off, ramp input signal is connected to the positive input terminal (B) of operational amplifier A 1, and fortune active switch capacitor module is configured to follow the mode, and operational amplifier positive input terminal (B) change in voltage transmits its output (O), then passes through the C of each row
hKbe delivered to the output of each row.
(3) switch S of active switch capacitor module
7when changing in first step height M position, when the switch S of passive switch capacitance module
1Kof short duration off state is in, to ensure to be injected into C by switch before and after turning off
hKthe electric charge of pole plate and signal have nothing to do; S
7then be in conducting state in other moment always.
In shared active slope conversion circuit, when active switch capacitor module is in follow the mode, be one to the overall gain of the transfer function of change in voltage, concrete principle can be described below.Described active switch capacitor module causes the change in voltage of operational amplifier positive input terminal B in the first step to second step switching and second step transfer process, is designated as Δ V
rIN, the active switch capacitor module of follow the mode is by Δ V
rINbe delivered to the output (O) of operational amplifier, and be delivered to shared node Z by the switch of conducting, the change in voltage of generation is designated as Δ V
z, be C because operational amplifier negative input end (X) exists direct-to-ground capacitance
g0=C
m0+ C
p0, then the gain of this transfer function is greater than 1, is expressed as:
According to principle of charge conservation, Δ V
zthe slope output V being delivered to each row will be continued
rOK, each the row slope output end voltage caused is changed to Δ V
rOK, due to sampling capacitance C
hKit is C that output pole plate exists direct-to-ground capacitance equally
gK=C
mK+ C
pK, then the gain of this transfer function is less than 1, is expressed as:
So to the overall gain of the transfer function of change in voltage be:
As long as ensure:
For all K=1,2 ..., N all sets up, then the overall gain of change in voltage is just constantly equal to one.
Claims (4)
1., for arranging a shared active slope conversion circuit for parallel two-step analog to digital converter, it is characterized in that comprising an active switch capacitor module 310 and N number of passive switch capacitance module 320.K, K=1,2 ..., N;
Active switch capacitor module comprises an operational amplifier A 1, sampling capacitance C
h0, a parasitic balancing capacitance C
m0with six switch S
2, S
3, S
4, S
5, S
6, S
7; Passive switch capacitance module 320.K comprises a sampling capacitance C
hK, a parasitic balancing capacitance C
mKwith a switch S
1K, K=1,2 ..., N;
Described active switch capacitor module 310 comprises the first reference level input V
rEFP, second reference level input V
rEFNwith ramp input V
rAthree inputs, and an output V
aO; Ramp input V
rAwith the first reference level input V
rEFPrespectively by second switch S
2with the 3rd switch S
3be connected to the positive input terminal B of operational amplifier A 1; Second reference level input V
rEFN, by the 6th switch S
6with the 0th sampling capacitance C
h0be connected to the negative input end X of operational amplifier, simultaneously by the 6th switch S
6with the 7th switch S
7be connected to output V
aO; The negative input end X of operational amplifier A 1, by the 4th switch S
4be connected to the output O of operational amplifier A 1, negative input end X is successively through the 0th sampling capacitance C simultaneously
h0with the 5th switch S
5be connected to the output O of operational amplifier, again by the 0th parasitic balancing capacitance C
m0be connected to ground;
Described passive switch capacitance module 320.K comprises ramp input V
rPKv is inputted with reference to pole plate
cHKtwo inputs, and a slope exports V
rOK; Ramp input V
rPKby K row switch S
1Kbe connected to slope and export V
rOK, K row sampling capacitance C
hKpole plate connect and export V with slope
rOKbe connected, be called output pole plate, another pole plate and reference pole plate input V
cHKbe connected, be called with reference to pole plate; K parasitic balancing capacitance C
mKa pole plate and slope export V
rOKbe connected, another pole plate is connected to ground;
When described shared active slope conversion circuit composition N row parallel architecture, comprise a ramp input and the output of N number of slope; The ramp input V of described active switch capacitor module
rAwith the ramp input V of N number of passive switch capacitance module
rP1~ V
rPNdirectly be connected, as the ramp input V of described N row parallel architecture
rIN; The slope of N row passive switch capacitance module exports V
rO1~ V
rONas the slope output of described N row parallel architecture; The reference pole plate input V of N row passive switch capacitance module 320.1 ~ 320.N
cH1~ V
cHNdirectly be connected, be called shared node Z; The output V of described active switch capacitor module
aOdirectly be connected with shared node Z, thus share by N number of passive switch capacitance module.
2. shared active slope conversion circuit as claimed in claim 1, is characterized in that circuit working process is as follows:
(1) when the high-order analog-to-digital conversion of the first step starts: active switch capacitor module is configured to sampling configuration; Second reference level V
rEFNbe connected with shared node Z by the switch of conducting on the one hand, on the other hand by active switch capacitor module samples; Ramp input V
rINby the N row switch S of conducting
11~ S
1Nrespectively with N row slope output V
rO1~ V
rONbe connected, directly as the output of each row;
(2) in the high-order analog-digital conversion process of the first step: N row passive switch capacitance module carries out work, ramp input signal V independently of each other
rINonce the measured signal arranged higher than K, K row switch S
1Kdisconnect immediately, the K row instantaneous for this moment ramp input level being stored in floating export pole plate V
rOKon, this voltage is the function of K row measured signal, is designated as V
rL(K);
(3) at the end of the high-order analog-to-digital conversion of the first step: active switch capacitor module is configured to latch mode, the output O of operational amplifier A 1 is connected with shared node Z by the switch of conducting; Connect the second reference level V
rEFNdisconnect with the switch of shared node Z, the second reference level V
rEFNafter first being latched by operational amplifier A 1, then be connected with shared node Z through the output O of operational amplifier A 1;
(4) when second step low level analog-to-digital conversion: active switch capacitor module is configured to follow the mode, ramp input V
rINby the second switch S of conducting
2be connected with the positive input terminal B of operational amplifier A 1 in active switch capacitor module, ramp input V
rINthe change in voltage produced is delivered to shared node Z through the input B of operational amplifier, the output O of operational amplifier successively; Then, according to principle of charge conservation, at each row sampling capacitance C
hKoutput pole plate on its level V kept
rL(K) superpose, export V as K row
rOK.
3. shared active slope conversion circuit as claimed in claim 1, is characterized in that the course of work in described active switch capacitor module and measured signal have nothing to do: when the high-order analog-to-digital conversion of the first step, it is configured to sampling configuration, to the second reference level V
rEFNsample; At the end of the first step, it is configured to latch mode, to the second reference level V
rEFNkeep; When second step low level analog-to-digital conversion, it is configured to follow the mode, to common ramp input V
rINfollow; The course of work of passive switch capacitance module is then relevant to measured signal, and the moment that its switch disconnects is all measured signal functions with the magnitude of voltage preserved.
4. shared active slope conversion circuit as claimed in claim 1, is characterized in that in described N number of passive switch capacitance module and shared active switch capacitor module thereof, parasitic balancing capacitance C
mKwith this node over the ground parasitic capacitance be added, obtain the total capacitance over the ground of this node, be designated as C
gK; The sampling capacitance of modules and total capacitance are over the ground in equal proportions, i.e. C
h0/ C
g0=C
hK/ C
gK, make change in voltage be that a mode is from ramp input end V with gain
rINbe delivered to the slope output V of each row
rO1~ V
rON; Wherein, K=1,2 ..., N.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410753991.0A CN104506194B (en) | 2014-12-11 | 2014-12-11 | For arranging the shared active slope conversion circuit of parallel two-step analog-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410753991.0A CN104506194B (en) | 2014-12-11 | 2014-12-11 | For arranging the shared active slope conversion circuit of parallel two-step analog-digital converter |
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| Publication Number | Publication Date |
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| CN104506194A true CN104506194A (en) | 2015-04-08 |
| CN104506194B CN104506194B (en) | 2017-12-01 |
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ID=52947918
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109104189A (en) * | 2017-06-21 | 2018-12-28 | 美国亚德诺半导体公司 | Passive switched-capacitor circuit for sampling and amplifying |
| CN113285714A (en) * | 2021-04-02 | 2021-08-20 | 西安理工大学 | Parallel two-step monoclinic analog-to-digital conversion circuit and method adopting interval fine slope |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140008515A1 (en) * | 2012-07-06 | 2014-01-09 | Omnivision Technologies, Inc. | Hybrid analog-to-digital converter having multiple adc modes |
| CN103746694A (en) * | 2014-01-14 | 2014-04-23 | 复旦大学 | Slope conversion circuit applied to two-step type integral analog-to-digital converter |
-
2014
- 2014-12-11 CN CN201410753991.0A patent/CN104506194B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140008515A1 (en) * | 2012-07-06 | 2014-01-09 | Omnivision Technologies, Inc. | Hybrid analog-to-digital converter having multiple adc modes |
| CN103746694A (en) * | 2014-01-14 | 2014-04-23 | 复旦大学 | Slope conversion circuit applied to two-step type integral analog-to-digital converter |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109104189A (en) * | 2017-06-21 | 2018-12-28 | 美国亚德诺半导体公司 | Passive switched-capacitor circuit for sampling and amplifying |
| CN109104189B (en) * | 2017-06-21 | 2022-04-29 | 美国亚德诺半导体公司 | Passive switched capacitor circuit for sampling and amplification |
| CN113285714A (en) * | 2021-04-02 | 2021-08-20 | 西安理工大学 | Parallel two-step monoclinic analog-to-digital conversion circuit and method adopting interval fine slope |
| CN113285714B (en) * | 2021-04-02 | 2024-02-02 | 西安理工大学 | Parallel two-step type single-inclined analog-to-digital conversion circuit and method adopting interval fine slope |
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| CN104506194B (en) | 2017-12-01 |
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