CN105897273A - Analog-to-digital conversion circuit and method for main and secondary gradients - Google Patents
Analog-to-digital conversion circuit and method for main and secondary gradients Download PDFInfo
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- CN105897273A CN105897273A CN201610184245.3A CN201610184245A CN105897273A CN 105897273 A CN105897273 A CN 105897273A CN 201610184245 A CN201610184245 A CN 201610184245A CN 105897273 A CN105897273 A CN 105897273A
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- Prior art keywords
- slope
- ramp voltage
- voltage
- value
- speed comparator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/56—Input signal compared with linear ramp
Abstract
The invention relates to an analog-to-digital conversion circuit and method for main and secondary gradients. The method comprises: a gradient modulator processes a ramp voltage to generate a main gradient ramp voltage and a secondary gradient ramp voltage; a signal voltage and the main gradient ramp voltage are compared, a value M of a counter is recorded by digital processing, a control signal outputted by a high-speed comparator is sent to the gradient modulator, and the gradient modulator modulates the control signal, wherein the M1 is a binary number; and the signal voltage is compared with the secondary gradient ramp voltage and a value M2 of the counter is recorded by digital processing, wherein the M2 is a binary number; and according to the M1 and the M2, a digital output value M is obtained, wherein the M is a binary number.
Description
Technical field
The present invention relates to analog to digital conversion circuit field, particularly relate to a kind of primary and secondary slope analog to digital conversion circuit
And method.
Background technology
Analog-digital converter is key components in infrared imaging system, is to connect reading circuit analog channel
The key component of signal processing below, the performance of analog-digital converter directly affects whole focal plane arrays (FPA) and reads
Go out the performance of circuit, and Embedded analog-digital converter has become the trend of design reading circuit.
The analog-digital converter being typically employed in infrared imaging system can be divided into three kinds: chip-scale, row are parallel,
Pixel-level.Chip-scale refers to that whole pel array shares an analog-digital converter, and picture element signal is through ranks
Selector, delivers to the input of analog-digital converter, so requires that the speed of analog-digital converter is the highest, if
Meter difficulty is big.Pixel-level refers to that each pixel has an independent analog-digital converter to go to change data,
This mode speed is the highest, full parellel, but the data of the analog-digital converter required and pixel are as many,
Area is too big, and noise is too big, and comparison of coherence is poor.Row refer to that every string shares a mould parallel
The concordance of number converter, a line concurrent working, the rate request of reduction, and string is good, power consumption dough-making powder
Amass and all compare compromise.Row parallel organization is compromised best in terms of power consumption, speed, area, is employed
For extensively.
In row parallel organization, single slope analog-to-digital converter is good, consistent with its simple in construction, noiseproof feature
Property the advantage such as good and be employed the most extensive.But the maximum shortcoming of single slope analog-to-digital converter is exactly,
Once conversion needs 2NIndividual clock, N is the figure place of analog-digital converter, required under the same transitions time
Clock frequency is higher.In high-precision applications, it is difficult to meet requirement.Along with the change of array scale is big,
Refresh rate accelerates, and a line time is i.e. also to shorten to the maximum conversion time of analog-digital converter, and this just requires
Clock frequency uprises, but the design of comparator and digital processing system below is all increased by high clock frequency
Add the biggest difficulty.
Summary of the invention
The technical problem to be solved be increasing in planar array, refresh frame frequency increasingly
Hurry up, change figure place increasing in the case of, the problem how reducing the master clock frequency of analog-digital converter.
The technical scheme is that a kind of primary and secondary slope analog digital conversion electricity
Road, described circuit includes:
Ramp generator output ramp voltage, the outfan of described ramp generator is defeated with Slope Modulation device
Entering end to be connected, the described outfan of Slope Modulation device is connected with the negative input of high-speed comparator,
The input applied signal voltage of sampling hold circuit, the outfan of described sampling hold circuit and described height
The positive input of speed comparator is connected, and the outfan of described high-speed comparator is adjusted with described slope respectively
Device sum counter processed is connected, and the outfan of described enumerator is connected with the input of depositor, clock
Signal is connected with described high-speed comparator and described enumerator respectively；
Described ramp voltage is generated main slope ramp voltage and time slope ramp electricity by described Slope Modulation device
Pressure, compares described signal voltage with described main slope ramp voltage, and by digital processing record
Value M1 of described enumerator, and the control signal that described high-speed comparator exports is sent to described slope tune
Device processed, described control signal is modulated by described Slope Modulation device, and wherein, M1 is binary number；
Described signal voltage is compared with described slope ramp voltage, and by described digital processing
Recording value M2 of described enumerator, wherein, M2 is binary number；
Obtaining digital output value M according to described M1 and described M2, wherein, M is binary number.
Another technical scheme that the present invention solves above-mentioned technical problem is as follows: a kind of for such as primary and secondary slope mould
Primary and secondary slope D conversion method described in number conversion circuit, it is characterised in that described method includes:
Ramp voltage is generated main slope ramp voltage and time slope ramp voltage by Slope Modulation device；
Signal voltage is compared with described main slope ramp voltage, and by digital processing record count
Value M1 of device, and the control signal that high-speed comparator exports is sent to described Slope Modulation device, described tiltedly
Described control signal is modulated by rate manipulator, and wherein, M1 is binary number；
Described signal voltage is compared with described slope ramp voltage, and by described digital processing
Recording value M2 of described enumerator, wherein, M2 is binary number；
Obtaining digital output value M according to described M1 and described M2, wherein, M is binary number.
Beneficial effects of the present invention: by signal voltage is oblique with main slope ramp voltage and time slope respectively
Slope voltage compares, and by the value of digital processing recording counter, respectively obtains M1 and M2, root
Obtain digital output value M according to M1 and M2, thus reduce the operating frequency of master clock, reduce power consumption, fall
Low design difficulty, realizes higher resolution with relatively low clock frequency.
Accompanying drawing explanation
A kind of primary and secondary slope analog to digital conversion circuit schematic diagram that Fig. 1 provides for the embodiment of the present invention；
A kind of primary and secondary slope D conversion method flow chart that Fig. 2 provides for the embodiment of the present invention；
The Slope Modulation device logic diagram that Fig. 3 provides for the embodiment of the present invention；
The primary and secondary slope analog to digital conversion circuit working timing figure that Fig. 4 provides for the embodiment of the present invention；
The main slope ramp voltage that Fig. 5 provides for the embodiment of the present invention and time slope ramp voltage ratio relatively moment
Schematic diagram.
In accompanying drawing, the list of parts representated by each label is as follows:
10, ramp generator, 20, Slope Modulation device, 30, high-speed comparator, 40, enumerator, 50,
Depositor, 60, sampling hold circuit.
Detailed description of the invention
A kind of primary and secondary slope analog to digital conversion circuit schematic diagram that Fig. 1 provides for the embodiment of the present invention.
With reference to Fig. 1, this circuit include ramp generator 10, Slope Modulation device 20, high-speed comparator 30,
Enumerator 40, depositor 50 and sampling hold circuit 60.
Ramp generator 10 inputs ramp voltage, the outfan of described ramp generator 10 and Slope Modulation
The input of device 20 is connected, and the outfan of described Slope Modulation device 20 is negative with high-speed comparator 30
Being connected to input, the input applied signal voltage of sampling hold circuit 60, described sampling keeps
The outfan of circuit 60 is connected with the positive input of described high-speed comparator 30, and described high ratio is relatively
The outfan of device 30 is connected with described Slope Modulation device 20 sum counter 40 respectively, described enumerator
The outfan of 40 is connected with the input of depositor 50, clock signal respectively with described high-speed comparator
30 are connected with described enumerator 40；
Described ramp voltage is generated main slope ramp voltage and time slope ramp by described Slope Modulation device 20
Voltage, is compared described signal voltage with described main slope ramp voltage, and is remembered by digital processing
Record value M1 of described enumerator 40, and the control signal that described high-speed comparator 30 exports is sent to institute
Stating Slope Modulation device 20, described control signal is modulated by described Slope Modulation device 20, wherein, and M1
For binary number；
Described signal voltage is compared with described slope ramp voltage, and by described digital processing
Recording value M2 of described enumerator 40, wherein, M2 is binary number；
Obtaining digital output value M according to described M1 and described M2, wherein, M is binary number.
Here, ramp generator, digital processing all reset, signal voltage through sampling hold circuit, by
Lastrow is sampled, and is in hold mode to one's own profession.Reset signal terminates, and ramp generator is started working.
Slope Modulation device is modulated according to described control signal, makes output ramp signal switch from main slope
To time slope output.
In the present embodiment, described circuit also includes: when described main slope ramp voltage exceedes described signal
During voltage, the output state of described high-speed comparator 30 changes.
Specifically, before described main slope ramp voltage rises to described signal voltage, described high ratio
Relatively device is output as height；When described main slope ramp voltage exceedes described signal voltage, described high ratio is relatively
Device is output as low.
In the present embodiment, described circuit also includes: when described slope ramp voltage exceedes described signal electricity
During pressure, the output state of described high-speed comparator 30 changes.
Specifically, before described slope ramp voltage rises to described signal voltage, described high ratio
Relatively device is output as height；When described slope ramp voltage exceedes described signal voltage, described high ratio is relatively
Device is output as low.
Specifically, described circuit also includes: according to formula (1) calculating digital output value M:
M=M1 × A+ (M2-M1) (1)
Wherein, M1 is the described enumerator after described main slope ramp voltage compares with described signal voltage
Value, M2 is the value of the described enumerator after described slope ramp voltage compares with described signal voltage, A
For real number.
Specifically, 640 × 512 array, 50Hz refresh rate are calculated, it is achieved 14 analog digital conversion
Master clock frequency needed for precision.A line time is constant, specially 1/50/512=39us, for the first time than
The maximum clock number relatively needed is: 2^14/A, and the clock number that second time compares is by concrete actual electricity
Road determines, also relevant with ratio A of primary and secondary slope.If arranging A is 16, that second time compare time
Clock number can control within 256, and the clock number that final total conversion needs is:
2^14/16+256=1280, needs the master clock frequency to be: 32.8M, thus is greatly reduced master clock
Frequency.
Ratio A of primary and secondary slope here, twice required clock number the most maximum of the primary and secondary of decision,
It is with main to compare maximum required clock number be inverse ratio, is comparing maximum required clock number just becoming with secondary
Ratio, it is possible to find an optimal value according to actual circuit conditions.
A kind of primary and secondary slope D conversion method flow chart that Fig. 2 provides for the embodiment of the present invention.
With reference to Fig. 2, step S201, ramp voltage is generated main slope ramp voltage with secondary by Slope Modulation device
Slope ramp voltage.
Step S202, compares signal voltage with described main slope ramp voltage, and by numeral at
Value M1 of reason recording counter, and the control signal that high-speed comparator exports is sent to described Slope Modulation
Device, described control signal is modulated by described Slope Modulation device, and wherein, M1 is binary number.
Step S203, compares described signal voltage with described slope ramp voltage, and passes through institute
Stating value M2 of enumerator described in digital processing record, wherein, M2 is binary number.
Step S204, obtains digital output value M according to described M1 and described M2, and wherein, M is two to enter
Number processed.
In the present embodiment, described method also includes: when described main slope ramp voltage exceedes described signal electricity
During pressure, the output state of described high-speed comparator changes.
In the present embodiment, described method also includes: when described slope ramp voltage exceedes described signal electricity
During pressure, the output state of described high-speed comparator changes.
In the present embodiment, described method also includes: calculate described digital output value M according to formula (1).
The Slope Modulation device logic diagram that Fig. 3 provides for the embodiment of the present invention.
With reference to Fig. 3, Slope Modulation device realizes planar array analog digital conversion by row parallel organization.Figure is
Row Parallel transformation, shares a ramp generator, and other module is all that every string has portion.Slope
Generator produces the slope that all row share, and slope is given to the Slope Modulation device of every string, Slope Modulation device
Ramp voltage is generated main slope ramp voltage and time slope ramp voltage, wherein, secondary slope ramp voltage
It is 1/A times of main slope ramp voltage, main slope ramp voltage and the switching instant of time slope ramp voltage
Determined by the finish time compared for the first time.
The primary and secondary slope analog to digital conversion circuit working timing figure that Fig. 4 provides for the embodiment of the present invention.
With reference to Fig. 4, signal voltage is compared with main slope ramp voltage, obtains output signal OUT1,
From the trailing edge of reset signal to the trailing edge of OUT1 signal, obtained by digital processing rolling counters forward
Signal and main slope ratio compared with clock number M1, signal voltage is compared with time slope ramp voltage, must
To output signal OUT2, from the trailing edge of reset signal to the trailing edge of OUT2 signal, at numeral
Reason rolling counters forward obtain signal and main slope ratio compared with clock number M2；Wherein, T l i ne is whole in array
The time of individual a line.
The main slope ramp voltage that Fig. 5 provides for the embodiment of the present invention and time slope ramp voltage ratio relatively moment
Schematic diagram.
With reference to Fig. 5, for main slope ramp voltage, in 0～t1 moment, when on main slope ramp voltage
Before being raised to described signal voltage, described high-speed comparator is output as height；In t1～the t2 moment, work as institute
Stating main slope ramp voltage when exceeding described signal voltage, described high-speed comparator is output as low.
For secondary slope ramp voltage, in t1～the t2 moment, when secondary slope ramp voltage rises to letter
Before number voltage, high-speed comparator is output as height；When more than the t2 moment, when secondary slope ramp voltage
When exceeding signal voltage, high-speed comparator is output as low.
Being described principle and the feature of the present invention below in conjunction with accompanying drawing, example is served only for explaining this
Invention, is not intended to limit the scope of the present invention.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all in the present invention
Spirit and principle within, any modification, equivalent substitution and improvement etc. made, should be included in this
Within bright protection domain.
Claims (8)
1. a primary and secondary slope analog to digital conversion circuit, it is characterised in that described circuit includes:
Ramp generator (10) output ramp voltage, the outfan of described ramp generator (10) is adjusted with slope
The input of device processed (20) is connected, the outfan of described Slope Modulation device (20) and high-speed comparator (30)
Negative input be connected, the input applied signal voltage of sampling hold circuit (60), described sampling
The outfan of holding circuit (60) is connected with the positive input of described high-speed comparator (30), described height
The outfan of speed comparator (30) is connected with described Slope Modulation device (20) sum counter (40) respectively, institute
The input of the outfan and depositor (50) of stating enumerator (40) is connected, and clock signal is respectively with described
High-speed comparator (30) is connected with described enumerator (40)；
Described ramp voltage is generated described Slope Modulation device (20) main slope ramp voltage and time slope is oblique
Slope voltage, compares described signal voltage with described main slope ramp voltage, and passes through digital processing
Record value M1 of described enumerator (40), and the control signal exported by described high-speed comparator (30) sends
To described Slope Modulation device (20), described control signal is modulated by described Slope Modulation device (20), its
In, M1 is binary number；
Described signal voltage is compared with described slope ramp voltage, and by described digital processing
Recording value M2 of described enumerator (40), wherein, M2 is binary number；
Obtaining digital output value M according to described M1 and described M2, wherein, M is binary number.
A kind of primary and secondary slope analog to digital conversion circuit the most according to claim 1, it is characterised in that institute
State circuit also to include:
When described main slope ramp voltage exceedes described signal voltage, described high-speed comparator (30)
Output state changes.
A kind of primary and secondary slope analog to digital conversion circuit the most according to claim 2, it is characterised in that institute
State circuit also to include:
When described slope ramp voltage exceedes described signal voltage, described high-speed comparator (30)
Output state changes.
A kind of primary and secondary slope analog to digital conversion circuit the most according to claim 3, it is characterised in that institute
State circuit also to include:
According to the following formula described digital output value M of calculating:
M=M1 × A+ (M2-M1)
Wherein, M1 is the described enumerator after described main slope ramp voltage compares with described signal voltage
Value, M2 is the value of the described enumerator after described slope ramp voltage compares with described signal voltage,
A is real number.
5., for an a kind of primary and secondary slope D conversion method as claimed in claim 1, its feature exists
In, described method includes:
Ramp voltage is generated main slope ramp voltage and time slope ramp voltage by Slope Modulation device；
Signal voltage is compared with described main slope ramp voltage, and by digital processing record count
Value M1 of device, and the control signal that high-speed comparator exports is sent to described Slope Modulation device, described tiltedly
Described control signal is modulated by rate manipulator, and wherein, M1 is binary number；
Described signal voltage is compared with described slope ramp voltage, and by described digital processing
Recording value M2 of described enumerator, wherein, M2 is binary number；
Obtaining digital output value M according to described M1 and described M2, wherein, M is binary number.
A kind of primary and secondary slope D conversion method the most according to claim 5, it is characterised in that institute
Method of stating also includes:
When described main slope ramp voltage exceedes described signal voltage, the output shape of described high-speed comparator
State changes.
A kind of primary and secondary slope D conversion method the most according to claim 6, it is characterised in that institute
Method of stating also includes:
When described slope ramp voltage exceedes described signal voltage, described high-speed comparator (30)
Output state changes.
A kind of primary and secondary slope D conversion method the most according to claim 7, it is characterised in that institute
Method of stating also includes:
According to the following formula described digital output value M of calculating:
M=M1 × A+ (M2-M1)
Wherein, M1 is the described enumerator after described main slope ramp voltage compares with described signal voltage
Value, M2 is the value of the described enumerator after described slope ramp voltage compares with described signal voltage, A
For real number.
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| CN201610184245.3A CN105897273B (en) | 2016-03-28 | 2016-03-28 | A kind of primary and secondary slope analog to digital conversion circuit and method |
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| CN201610184245.3A CN105897273B (en) | 2016-03-28 | 2016-03-28 | A kind of primary and secondary slope analog to digital conversion circuit and method |
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| CN105897273B CN105897273B (en) | 2019-01-04 |
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| CN104040897A (en) * | 2012-01-23 | 2014-09-10 | 国立大学法人东北大学 | Analog-digital converter and solid-state image capture device |
| EP2993789A1 (en) * | 2014-09-02 | 2016-03-09 | Nxp B.V. | Efficient analog to digital converter |
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| JP2007243324A (en) * | 2006-03-06 | 2007-09-20 | Sony Corp | Solid-state imaging apparatus |
| WO2008026129A3 (en) * | 2006-08-31 | 2008-06-26 | Koninkl Philips Electronics Nv | Single slope analog-to-digital converter |
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