CN103730359A - Manufacturing method of composite gate media SiC MISFET - Google Patents
Manufacturing method of composite gate media SiC MISFET Download PDFInfo
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- CN103730359A CN103730359A CN201310471216.1A CN201310471216A CN103730359A CN 103730359 A CN103730359 A CN 103730359A CN 201310471216 A CN201310471216 A CN 201310471216A CN 103730359 A CN103730359 A CN 103730359A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000002131 composite material Substances 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 40
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 31
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 20
- 239000001301 oxygen Substances 0.000 claims abstract description 20
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 6
- 238000012545 processing Methods 0.000 claims abstract description 4
- 239000003292 glue Substances 0.000 claims description 43
- 239000011248 coating agent Substances 0.000 claims description 42
- 238000000576 coating method Methods 0.000 claims description 42
- 229920002120 photoresistant polymer Polymers 0.000 claims description 33
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 28
- 238000000137 annealing Methods 0.000 claims description 25
- 238000002513 implantation Methods 0.000 claims description 24
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 19
- 239000002253 acid Substances 0.000 claims description 18
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 14
- 238000004140 cleaning Methods 0.000 claims description 14
- 229910052757 nitrogen Inorganic materials 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 238000001459 lithography Methods 0.000 claims description 10
- 238000009832 plasma treatment Methods 0.000 claims description 8
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 claims description 8
- 238000010422 painting Methods 0.000 claims description 7
- 239000000956 alloy Substances 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 230000004913 activation Effects 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000005566 electron beam evaporation Methods 0.000 claims description 4
- 150000002739 metals Chemical class 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 claims description 2
- 238000001704 evaporation Methods 0.000 abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 230000008020 evaporation Effects 0.000 abstract description 9
- 229910052681 coesite Inorganic materials 0.000 abstract description 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 5
- 239000000377 silicon dioxide Substances 0.000 abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 5
- 229910052682 stishovite Inorganic materials 0.000 abstract description 5
- 229910052905 tridymite Inorganic materials 0.000 abstract description 5
- 150000002500 ions Chemical class 0.000 abstract description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 1
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- 238000010894 electron beam technology Methods 0.000 abstract 1
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- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 239000000243 solution Substances 0.000 description 36
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- 239000010408 film Substances 0.000 description 18
- 229910021641 deionized water Inorganic materials 0.000 description 16
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 13
- 239000008367 deionised water Substances 0.000 description 12
- -1 develop Substances 0.000 description 8
- 229910021642 ultra pure water Inorganic materials 0.000 description 8
- 239000012498 ultrapure water Substances 0.000 description 8
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 6
- 235000019441 ethanol Nutrition 0.000 description 5
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
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- 238000005516 engineering process Methods 0.000 description 2
- 238000011010 flushing procedure Methods 0.000 description 2
- 230000008676 import Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052708 sodium Inorganic materials 0.000 description 2
- 239000011734 sodium Substances 0.000 description 2
- 238000000427 thin-film deposition Methods 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 208000034189 Sclerosis Diseases 0.000 description 1
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- 229910006294 Si—N Inorganic materials 0.000 description 1
- FKNQFGJONOIPTF-UHFFFAOYSA-N Sodium cation Chemical compound [Na+] FKNQFGJONOIPTF-UHFFFAOYSA-N 0.000 description 1
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Images
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
- H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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Abstract
The invention discloses a manufacturing method of a composite gate media SiC MISFET. A P-type SiC epitaxial wafer is cleaned in a standard wet method; through high-temperature ions, source and drain leakage N+ is doped; an SiO2 film layer grows in a dry-oxygen oxidation method, and bottom gate media are formed; growing SiO2 films in an ECRPE-MOCVD system are subjected to N-plasma processing; Al2O3 medium films are deposited in an atomic layer deposition ALD method, and top gate media are formed; a source and drain area is etched, a composite gate medium layer in a source and drain ohm contact area is eliminated, source and drain ohm contact metal is formed in an electron beam reactive evaporation chamber in an evaporating mode, and source and drain ohm contact is formed in a stripping mode; gate metal is formed on the composite gate medium layer in an evaporating mode, a gate pattern is formed in a stripping mode, and the MISFET is manufactured. Interface characteristic of the SiC MISFET is improved, channel mobility of the MIS device is improved, and the method can be used for manufacturing large-scale SiC MIS devices.
Description
Technical field
The invention belongs to microelectronics technology, relate to the making of semiconductor device, particularly a kind of manufacture method of gate stack SiC MISFET device, to improve the channel mobility of MISFET device and to reduce SiC/SiO
2interface state density, thus its reliability when high temperature, high-power applications improved.
Background technology
SiC has unique physics, chemistry and electrology characteristic, is at extremely potential semi-conducting materials in extreme applications field such as high temperature, high frequency, high-power and radioresistances.The optimum Working of SiC power MOSFET is closely related with gate medium interfacial dielectric layer characteristic and bulk properties.For improving SiCMOS device interfaces character and improving gate medium reliability, current main method concentrates in the research of annealing process, as traditional Ar, H
2annealing, nitrogen oxide annealing (NO, N
2o), N Implantation before oxidation, and these be all principle by import more Ar, H and N element in interface to reduce interface state density, but found through experiments, the ratio that these methods import element is very little, and interface state density can not well be reduced; And adopt N and H passivation for the electron mobility of MOSFET device, still not to reach afterwards the requirement of practical application, also only there is 30～40cm
2v
-1s
-1, the people such as F.Allerstan find SiC/SiO by test
2150cm can be brought up to by Si face inversion channel mobility by after sodium passivation in interface
2v
-1s
-1but sodium ion can mobile cause the unstable of threshold voltage under the effect of bias voltage, therefore utilizing sodium element passivation is not good method yet.
Summary of the invention
The object of the invention is to the deficiency for above-mentioned technique, propose a kind of Al
2o
3/ Nitrided-SiO
2the manufacture method of gate stack SiC MISFET device, to reduce SiC and SiO
2interface state density, improves SiC MISFET device channel mobility, improves the reliability of SiC MISFET device when high temperature, high-power applications.
For achieving the above object, technical solution of the present invention:
A manufacture method for composite grid structure SIC MISFET device, comprises the following steps:
A1 substrate surface cleans: the cleaning of standard wet processing is carried out on the surface to P type SiC epitaxial wafer sample:
A2 source is leaked high temperature Implantation and is annealed and activate: the P type SiC epitaxial wafer sample surfaces resist coating being cleaned on surface, and carve source, leak high temperature Implantation region, then carry out source and leak high temperature P+ Implantation and Implantation annealing activation:
The formation of ohmic contact is leaked in A3 source: after carrying out source leakage high temperature Implantation and annealing activation, in SiC sample P type epi-layer surface resist coating, the source that carves, leak ohmic contact hole, then carry out the deposit that metal ohmic contact is leaked in source, peel off formation source and leak ohmic contact, and carry out alloy annealing:
A4 gate stack layer growth: the SiC sample surfaces that carries out leaking after ohmic contact in source is carried out to large area HF acid cleaning, then carry out Al
2o
3/ Nitrided-SiO
2the growth of composite gate dielectric layer:
The formation of A5 gate figure: glue is peeled off in the substrate surface painting at the gate stack of having grown, photoresist makes gate region by lithography, and electron beam evaporation forms grid metal, then peels off and realizes gate figure;
A6 electrode fabrication.
Described manufacture method, described steps A 2 detailed processes are as follows,
The P type SiC epitaxial wafer sample that A21 was cleaned surface is put in the middle of PECVD, large area deposit SiO
2layer, thickness is 60nm;
A22 in deposit SiO
2the SiC sample surfaces resist coating of layer, and make source, drain region by lithography; Then in the middle of HF acid solution by the SiO without photoresist protection
2layer washes, and exposes source and leaks high temperature Implantation region;
A23 puts into high temperature ion implantor by the SiC sample that exposes source and drain areas, at 400 ℃, divides and carries out high temperature nitrogen Implantation four times, and dosage and energy are as follows: 400 ℃: 5 × 10
14㎝
-2/ 30K, 6.0 × 10
14㎝
-2/ 60K, 8 × 10
14㎝
-2/ 120K, 1.5 × 10
15㎝
-2/ 190K;
A24 cleans in HF solution the sample having carried out after high temperature Implantation, removes surperficial SiO
2barrier layer;
A25 is by SiO
2the SiC sample that barrier layer is removed is put into the high-temperature annealing furnace 30min that anneals at 1600 ℃.
Described manufacture method, described steps A 3 detailed processes are as follows:
A31 peels off glue, whirl coating to the SiC sample surfaces painting of having carried out high annealing;
A32 was getting rid of SiC sample surfaces resist coating, the whirl coating of glue, and ohmic contact hole is leaked in the source that makes by lithography;
It is that the Al/ Ni/Au of 150nm/50nm/200nm is as metal ohmic contact that A33 evaporates thickness on the SiC sample surfaces that carves drain contact hole, source;
A34 peels off formation source leakage ohmic contact figure to having steamed the SiC sample of metal;
A35 is placed in annealing furnace alloy at 950 ℃ by the SiC sample that has carried out ohmic contact and anneals 30 minutes.
Described manufacture method, described steps A 4 detailed processes are as follows:
A41 puts into high temperature oxidation furnace by the SiC sample that has carried out ohmic contact, in the time of 1180 ℃, passes into purity oxygen, is oxidized the positive 10min of SiC epitaxial wafer, the SiO2 oxide-film that generation thickness is 8nm under dry oxygen condition;
A42 carries out nitrogenize to the oxide-film of growth: in electron cyclotron resonace ECR-PEMOCVD system, the SiO2 oxide-film having generated is carried out to nitrogen plasma treatment; process conditions are: microwave power 625W; temperature is 600 ℃, and N2 flow is 50sccm, and plasma treatment time is 7.5min;
A43 puts into atomic layer deposition reactions chamber by the SiC sample carrying out after nitrogen plasma treatment, with trimethyl aluminium TMA and H
2o is source, and temperature is 300 ℃, and air pressure is 2Torr, obtains the Al that thickness is 20nm
2o
3film.
Described manufacture method, described steps A 5 adopts two kinds of metals of Ni/Au of 20nm/240nm to do grid metal; Its detailed process is as follows:
A51 is coated with and peels off glue, whirl coating at the SiC sample surfaces that has carried out the growth of large area gate stack;
A52 is being painted with the SiC sample surfaces resist coating of peeling off glue, and whirl coating, utilizes grid version to make grid metallic region by lithography;
It is that the Ni/Au of 20nm/240nm is as grid contacting metal that A53 evaporates thickness on the SiC sample surfaces that carves grid contact hole;
A54 utilizes stripping means to form gate figure.
Described manufacture method, described steps A 6, wherein the making of interconnect electrode adopts two kinds of metals of Ti/Au, and thickness is respectively 50nm/200nm; Comprise the following steps:
A61 is making SiC sample surfaces resist coating, the whirl coating of grid metal;
A62 utilizes the anti-version of grid oxygen to make non-gate stack region by lithography; Then sample is put into HF acid solution and carried out rinsing, remove the gate stack in non-grid oxygen region;
A63 peels off glue, whirl coating in the SiC sample surfaces painting of the gate stack of having removed non-grid oxygen region;
A64 is being painted with SiC sample surfaces resist coating, the whirl coating of peeling off glue;
A65 utilizes the photoetching of interconnection contact version, carve grid, source, leakage contact interconnect area '
It is that the Ti/Au of 30nm/200nm is as grid contacting metal that A66 evaporates thickness on the SiC sample surfaces that carves grid contact hole;
A67 utilizes stripping means to form grid, source, leakage interconnection graph.
The present invention compared with prior art tool has the following advantages:
The present invention passes through ultra-thin Si O
2oxide-film carries out nitrogenize, can form stronger Si-N key and O-N key, makes SiC and SiO
2interface and near oxide layer thereof have obtained sclerosis to a certain degree, reduce SiC/SiO
2interface state density, thus SiC/SiO improved
2interfacial characteristics.
The present invention passes through the mode of plasma to ultra-thin Si O
2oxide-film carries out nitrogenize, can improve SiC/SiO
2the content of interfacial nitrogen element, makes SiC/SiO
2interface state density, dangling bonds can effectively be reduced, thereby improve the mobility characteristics of device.
Accompanying drawing explanation
Fig. 1 is the preparation flow figure of embodiments of the invention 1;
Fig. 2 is the preparation flow figure of the embodiment of the present invention 2.
Embodiment
Below in conjunction with specific embodiment, the present invention is described in detail.
Embodiment 1
With reference to Fig. 1, the performing step of this example is as follows:
Step 1, adopts standard cleaning method RCA to carry out surface clean to 4H-SiCP type epitaxial wafer sample:
(1a) 4H-SiCP type epitaxial wafer sample is immersed in to each 5min in acetone, absolute ethyl alcohol successively, then uses deionized water rinsing, to remove the grease of epitaxial wafer sample surfaces;
(1b) the SiC sample after cleaning is for the first time placed in to H
2sO
4: H
2o
2=1: 1(volume ratio) in solution, soak 15min, H
2sO
4concentration be 98%, H
2o
2concentration be 27%, then use deionized water rinsing;
(1c) the SiC sample after cleaning is for the second time placed in to HF: H
2o=1: 10(volume ratio) solution in soak 1min to float natural oxidizing layer, the concentration of HF acid is 40%, and with deionized water rinsing;
(1d) the SiC sample after cleaning is for the third time immersed in to NH
4oH: H
2o
2: DIW=3: 3: 10(volume ratio) solution in boil, NH
4the concentration of OH is 28%, H
2o
2concentration be 27%, then use deionized water rinsing;
(1e) the SiC sample after the 4th cleaning is placed in to HF: H
2o=1: 10(volume ratio) solution in soak 30s, the concentration of HF acid is 40%, and with deionized water rinsing;
(1f) by the 5th time clean after SiC sample at HCl: H
2o
2: DIW=3: 3: 10(volume ratio) solution in boil, the concentration of HCl is 10%, H
2o
2concentration be 27%, with deionized water rinsing;
(1g) by the 6th time clean after SiC sample at HF: H
2o=1: 10(volume ratio) solution in soak 30s, and with deionized water rinsing, the concentration of HF acid is 40%, finally uses N
2rifle dries up.
Step 2, in the epitaxial surface making source in epitaxial wafer sample front, leak N+ high temperature Implantation region:
(2a) cleaned epitaxial wafer is put into PECVD reative cell, at 300 ℃ of lower surface deposit SiO
2layer, thickness is 60nm;
(2b) in deposit SiO
2the unilateral resist coating of extension of layer;
(2c) get rid of photoresist, then the epitaxial wafer that got rid of glue is carried out to front baking at 80 ℃; The front baking time is 10～15min;
(2d) utilize source to leak and inject reticle to the epitaxial wafer sample exposure after front baking;
(2e) in positivity developer solution, develop, solution temperature is 20 ℃, and developing time is 85s;
(2f) epitaxial wafer after developing is carried out to post bake at ultra-pure water, coolant-temperature gage is 20 ℃, and the post bake time is 85s;
(2g) in equipment for burning-off photoresist by plasma, remove the photoresist exposing, expose effective source and drain areas;
(2h) then in HF acid solution by the SiO exposing
2layer washes;
(2i) will wash source-drain area SiO
2the epitaxial wafer of layer is put into high temperature ion implantation chamber and is carried out source leakage N+ Implantation, and temperature is adjusted to 400 ℃, and implantation dosage and energy are as follows: 5 × 10
14㎝
-2/ 30K, 6.0 × 10
14㎝
-2/ 60K, 8 × 10
14㎝
-2/ 120K, 1.5 × 10
15㎝
-2/ 190K; Implantation concentration is 1 × 10
20㎝
-3left and right, the degree of depth is 0.3 μ m left and right;
(2j) the HF(concentration that is 1:10 to the sample injecting later in volume ratio is 40%) with the mixed solution rinsing of water, remove surperficial SiO
2layer;
(2k) epitaxial wafer of surface clean being crossed is put into high-temperature annealing furnace and is carried out high annealing, and annealing conditions is: at 1600 ℃ 30 minutes;
Step 3, on N+ region, ohmic contact is leaked in making source:
(3a) in the epitaxial wafer surface painting of carrying out after high annealing, peel off glue, whirl coating;
(3b) being coated with epitaxial wafer surface resist coating, the whirl coating of peeling off glue, then the epitaxial wafer sample that got rid of glue is carried out to front baking at 80 ℃; The front baking time is 10～15min;
(3c) utilize drain contact reticle in source to the epitaxial wafer exposure after front baking;
(3d) in positivity developer solution, develop, solution temperature is 20 ℃, and developing time is 85s;
(3e) epitaxial wafer after developing is carried out to post bake at ultra-pure water, coolant-temperature gage is 20 ℃, and the post bake time is 85s;
(3f) in equipment for burning-off photoresist by plasma, remove the photoresist exposing, expose effective source and drain areas;
(3g) epitaxial wafer that removed photoresist soaked 5 hours in acetone and utilize the ultrasonic processing of acetone 1 minute, and then acetone, alcohol cleans respectively once, remove source and leak the glue of peeling off in ohmic contact region; Expose drain contact region, effective source;
(3h) epitaxial wafer that removed glue is put into eb evaporation chambers, three kinds of metal A l/Ni/Au of large area evaporation leak Ohm contact electrode in the source of doing, its thickness is respectively 150nm, 50nm and 70nm, then utilizes the method for the peeling off source of realizing to leak ohmic contact figure;
(3i) finally the epitaxial wafer of finishing source-drain electrode is placed in to annealing furnace and at 950 ℃, carries out alloy annealing 30 minutes;
Step 4, large area deposition Al
2o
3/ Nitrided-SiO
2composite gate dielectric layer:
(4a) epitaxial wafer of having made source leakage metal ohmic contact being put into high temperature oxidation furnace, is the N of 750 ℃ in temperature
2in environment, push in oxidation furnace flat-temperature zone;
(4b) by 3 ℃/min speed, flat-temperature zone is heated up;
(4c) when temperature rises to 1180 ℃, pass into oxygen, oxygen flow is 0.5l/min, is oxidized epitaxial wafer surface 10min under pure dry oxygen condition, the SiO that is 8nm at the positive generation of epitaxial wafer thickness
2oxide-film.
(4d) SiO that will grow
2the epitaxial wafer of oxide-film is placed in electron cyclotron resonace ECR-PEMOCVD system, microwave power 625W, and temperature is 600 ℃, N
2flow is 50sccm, and plasma treatment time is 7.5min; .
(4e) the nitrogenize SiO that will grow
2the epitaxial wafer of oxide-film is placed in atomic layer deposition reactions chamber, with trimethyl aluminium TMA and H
2o is source, and set temperature is 300 ℃, and air pressure is 2Torr;
(4f) the nitrogenize SiO growing
2the trimethyl aluminium TMA pulse that carry out 1.5 seconds on oxide-film surface is rinsed,
(4g) N carrying out 2.5 seconds carrying out epitaxial wafer that trimethyl aluminium TMA rinsed
2pulse is rinsed;
(4h) to carrying out N
2the steam pulse that the epitaxial wafer that pulse was rinsed carries out 1.0 seconds is rinsed;
(4i) N carrying out 3.0 seconds carrying out epitaxial wafer that steam pulse rinsed
2pulse is rinsed;
(4j) to process N
2epitaxial wafer after flushing repeats the Al in 200 cycles
2o
3thin film deposition, obtains the Al that thickness is 20nm
2o
3film.
Step 5, the formation of gate figure:
(5a) at the Al that has carried out large area deposition
2o
3/ Nitrided-SiO
2the epitaxial wafer surface of gate stack is coated with peels off glue, whirl coating;
(5b) be coated with the epitaxial wafer surface resist coating of peeling off glue; Get rid of photoresist, then the epitaxial wafer that got rid of glue is carried out to front baking at 80 ℃; The front baking time is 10～15min;
(5c) utilize grid reticle to the epitaxial wafer exposure after front baking;
(5d) in positivity developer solution, develop, solution temperature is 20 ℃, and developing time is 85s;
(5e) epitaxial wafer after developing is carried out to post bake at ultra-pure water, coolant-temperature gage is 20 ℃, and the post bake time is 85s;
(5f) in equipment for burning-off photoresist by plasma, remove the photoresist exposing, then the epitaxial wafer that removed photoresist soaked 5 hours in acetone and utilize acetone ultrasonic 1 minute, and then acetone, alcohol cleans respectively once, remove the glue of peeling off of grid metallic region; Expose effective gate region;
(5g) epitaxial wafer of washing glue is placed in to eb evaporation chambers, at the epitaxial wafer front large area electron beam evaporation Ni/Au metal that removed glue, does grid, evaporating the wherein thickness of Ni metal is 20nm, and the thickness of Au metal is 240nm;
(5h) utilize and peel off formation gate figure;
Step 6, the making of electrode:
(6b) finishing the epitaxial wafer surface resist coating of gate figure; Get rid of photoresist, then the epitaxial wafer that got rid of glue is carried out to front baking at 80 ℃; The front baking time is 10～15min;
(6c) utilize the anti-version of grid oxygen to the epitaxial wafer exposure after front baking;
(6d) in positivity developer solution, develop, solution temperature is 20 ℃, and developing time is 85s;
(6e) epitaxial wafer after developing is carried out to post bake at ultra-pure water, coolant-temperature gage is 20 ℃, and the post bake time is 85s;
(6f) in equipment for burning-off photoresist by plasma, remove the photoresist exposing, then will go epitaxial wafer rinsing in HF acid solution of photoresist, and remove the composite gate dielectric layer that do not have photoresist to protect non-grid oxygen region;
(6g) utilize plasma degumming machine to remove unnecessary glue;
(6h) to going to the epitaxial wafer surface of photoresist to be coated with, peeled off glue, whirl coating; Resist coating, whirl coating then carries out front baking to the epitaxial wafer that got rid of glue at 80 ℃; The front baking time is 10～15min;
(6i) utilize interconnection contact version to the epitaxial wafer exposure after front baking;
(6j) in positivity developer solution, develop, solution temperature is 20 ℃, and developing time is 85s;
(6k) epitaxial wafer after developing is carried out to post bake at ultra-pure water, coolant-temperature gage is 20 ℃, and the post bake time is 85s;
(6l) in equipment for burning-off photoresist by plasma, remove the photoresist exposing, then the epitaxial wafer that removed photoresist soaked 5 hours in acetone and utilize acetone ultrasonic 1 minute, and then acetone, alcohol cleans respectively once, remove the glue of peeling off of contact interconnect area; Expose effective contact area;
(6m) to going photoresist and the epitaxial wafer of peeling off glue to put in the middle of eb evaporation chambers, large area evaporation Ti/Au, thickness is 50nm/200nm;
(6n) by stripping means, form last electrode contact.
Embodiment 2
Compared with embodiment 1, the step of the present embodiment is more simple, only needs four mask plates, and utilizes the composite gate dielectric layer of deposit to do source to leak the mask of ohmic contact, reduced the fussy degree of technique.
With reference to Fig. 2, the performing step of this example is as follows:
Steps A, adopts standard cleaning method RCA to carry out surface clean to 4H-SiC P type epitaxial wafer:
(A1) 4H-SiC P type epitaxial wafer is immersed in to acetone successively, each 5min in absolute ethyl alcohol, then use deionized water rinsing, to remove the grease of epitaxial wafer sample surfaces;
(A2) the SiC sample after cleaning is for the first time placed in to H
2sO
4: H
2o
2=1: 1(volume ratio) in solution, soak 15min, H
2sO
4concentration be 98%, H
2o
2concentration be 27%, then use deionized water rinsing;
(A3) the SiC sample after cleaning is for the second time placed in to HF: H
2o=1: 10(volume ratio) solution in soak 1min to float natural oxidizing layer, the concentration of HF acid is 40%, and with deionized water rinsing;
(A4) the SiC sample after cleaning is for the third time immersed in to NH
4oH: H
2o
2: DIW=3: 3: 10(volume ratio) solution in boil, NH
4the concentration of OH is 28%, H
2o
2concentration be 27%, then use deionized water rinsing;
(A5) the SiC sample after the 4th cleaning is placed in to HF: H
2o=1: 10(volume ratio) solution in soak 30s, the concentration of HF acid is 40%, and with deionized water rinsing;
(A6) by the 5th time clean after SiC sample at HCl: H
2o
2: DIW=3: 3: 10(volume ratio) solution in boil, the concentration of HCl is 10%, H
2o
2concentration be 27%, with deionized water rinsing;
(A7) by the 6th time clean after SiC sample at HF: H
2o=1: 10(volume ratio) solution in soak 30s, and with deionized water rinsing, the concentration of HF acid is 40%, finally uses N
2rifle dries up.
Step B, leaks N+ high temperature Implantation region in the epitaxial surface making source in SiC epitaxial wafer front:
(B1) cleaned SiC epitaxial wafer is put into PECVD reative cell, at 300 ℃ of lower surface deposit SiO
2layer, thickness is 60nm;
(B2) in deposit SiO
2the epitaxial wafer surface resist coating of layer;
(B3) get rid of photoresist, then the epitaxial wafer that got rid of glue is carried out to front baking at 80 ℃; The front baking time is 10～15min;
(B4) utilize source light leak to cut blocks for printing to the epitaxial wafer exposure after front baking;
(B5) in positivity developer solution, develop, solution temperature is 20 ℃, and developing time is 85s;
(B6) epitaxial wafer after developing is carried out to post bake at ultra-pure water, coolant-temperature gage is 20 ℃, and the post bake time is 85s;
(B7) in equipment for burning-off photoresist by plasma, remove the photoresist exposing, expose effective source and leak injection zone;
(B8) then in HF acid solution by the SiO not protected by photoresist
2layer washes;
(B9) will wash source-drain area SiO
2the epitaxial wafer of layer is put into high temperature ion implantation chamber and is carried out source leakage N+ Implantation, and temperature is adjusted to 400 ℃, injects metering and energy as follows: 5 × 10
14㎝
-2/ 30K, 6.0 × 10
14㎝
-2/ 60K, 8 × 10
14㎝
-2/ 120K, 1.5 × 10
15㎝
-2/ 190K, implantation concentration is 1 × 10
20㎝
-3left and right, the degree of depth is 0.3 μ m left and right;
(B10) to injecting sample later, in volume ratio, be 1: 10, HF acid and H that concentration is 40%
2rinsing in the solution of O, removes surperficial SiO
2layer;
(B11) epitaxial wafer of surface clean being crossed is put into high-temperature annealing furnace and is carried out high annealing, and annealing conditions is: at 1600 ℃ 30 minutes;
Step C, the growth of sacrificial oxide layer:
(C1) epitaxial wafer that carried out high annealing is put into high temperature oxidation furnace, in the time of 1200 ℃, under pure dry oxygen condition, be oxidized epitaxial wafer surface 30min, the SiO that is 20nm at the positive generation of epitaxial wafer thickness
2oxide-film;
(C2) SiO that will grow
2the epitaxial wafer of oxide-film is put in the middle of HF acid, and surperficial oxide layer is washed;
Step D, large area deposition Al
2o
3/ Nitrided-SiO
2composite gate dielectric layer:
(D1) epitaxial wafer of HF acid rinse being crossed is put into high temperature oxidation furnace, is the N of 750 ℃ in temperature
2in environment, push in oxidation furnace flat-temperature zone;
(D2) by 3 ℃/min speed, flat-temperature zone is heated up;
(D3) when temperature rises to 1180 ℃, pass into oxygen, oxygen flow is 0.5l/min, is oxidized epitaxial wafer surface 10min under pure dry oxygen condition, the SiO that is 8nm at the positive generation of epitaxial wafer thickness
2oxide-film.
(D4) epitaxial wafer of the SiO2 oxide-film of having grown is placed in to electron cyclotron resonace ECR-PEMOCVD system, microwave power 625W, temperature is 600 ℃, N
2flow is 50sccm, and plasma treatment time is 7.5min;
(D5) the nitrogenize SiO that will grow
2the epitaxial wafer of oxide-film is placed in atomic layer deposition reactions chamber, with trimethyl aluminium TMA and H
2o is source, and set temperature is 300 ℃, and air pressure is 2Torr;
(D6) the nitrogenize SiO growing
2the trimethyl aluminium TMA pulse that carry out 1.5 seconds on oxide-film surface is rinsed;
(D7) N carrying out 2.5 seconds carrying out epitaxial wafer that trimethyl aluminium TMA rinsed
2pulse is rinsed;
(D8) to carrying out N
2the steam pulse that the epitaxial wafer that pulse was rinsed carries out 1.0 seconds is rinsed;
(D9) N carrying out 3.0 seconds carrying out epitaxial wafer that steam pulse rinsed
2pulse is rinsed;
(D10) to process N
2epitaxial wafer after flushing repeats the Al in 200 cycles
2o
3thin film deposition, obtains the Al that thickness is 20nm
2o
3film.
Step e, the preparation of ohmic contact is leaked in source:
(E1) carrying out large area Al
2o
3/ Nitrided-SiO
2the epitaxial wafer surface of gate stack layer growth is coated with peels off glue, whirl coating;
(E2) be coated with the epitaxial wafer surface resist coating of peeling off glue, whirl coating then carries out front baking to the epitaxial wafer that got rid of glue at 80 ℃; The front baking time is 10～15min;
(E3) utilize drain contact reticle in source to the epitaxial wafer exposure after front baking;
(E4) in positivity developer solution, develop, solution temperature is 20 ℃, and developing time is 85s;
(E5) epitaxial wafer after developing is carried out to post bake at ultra-pure water, coolant-temperature gage is 20 ℃, and the post bake time is 85s;
(E6) in equipment for burning-off photoresist by plasma, remove the photoresist exposing, then in acetone, soak 5 hours and utilize acetone ultrasonic 1 minute, acetone, the each cleaning of alcohol once, are removed the glue of peeling off of source and drain areas; Expose not by photoresist and peel off the drain contact region, effective source that glue is protected;
(E7) epitaxial wafer that removed glue is put into HF acid solution, remove the composite gate dielectric layer of not protected by glue;
(E7) epitaxial wafer of removing unnecessary composite gate dielectric layer is put into eb evaporation chambers, three kinds of metal A l/Ni/Au of large area evaporation leak Ohm contact electrode in the source of doing, and its thickness is respectively 100nm, 50nm and 70nm,
(E8) utilize the method for the peeling off source of realizing to leak ohmic contact figure;
Step F, the formation of gate figure:
(F1) on the epitaxial wafer surface of having carried out source leakage ohmic contact, be coated with and peel off glue, whirl coating;
(F2) being coated with epitaxial wafer surface resist coating, the whirl coating of peeling off glue, then the epitaxial wafer that got rid of glue is carried out to front baking at 80 ℃; The front baking time is 10～15min;
(F3) utilize grid reticle to the epitaxial wafer exposure after front baking;
(F4) in positivity developer solution, develop, solution temperature is 20 ℃, and developing time is 85s;
(F5) epitaxial wafer after developing is carried out to post bake at ultra-pure water, coolant-temperature gage is 20 ℃, and the post bake time is 85s;
(F6) in equipment for burning-off photoresist by plasma, remove the photoresist exposing, then in acetone, soak 5 hours and utilize acetone ultrasonic 1 minute, acetone, the each cleaning of alcohol once, are removed the glue of peeling off of gate region; Expose territory, effective gate contact zone;
(F7) epitaxial wafer of washing glue is placed in to eb evaporation chambers, at the epitaxial wafer front large area electron beam evaporation Ni/Au metal that removed glue, does grid, evaporating the wherein thickness of Ni metal is 20nm, and the thickness of Au metal is 240nm;
(F8) utilize and peel off formation gate figure.
Claims (6)
1. a manufacture method for composite grid structure SIC MISFET device, is characterized in that, comprises the following steps:
A1 substrate surface cleans: the cleaning of standard wet processing is carried out on the surface to P type SiC epitaxial wafer sample:
A2 source is leaked high temperature Implantation and is annealed and activate: the P type SiC epitaxial wafer sample surfaces resist coating being cleaned on surface, and carve source, leak high temperature Implantation region, then carry out source and leak high temperature P+ Implantation and Implantation annealing activation:
The formation of ohmic contact is leaked in A3 source: after carrying out source leakage high temperature Implantation and annealing activation, in SiC sample P type epi-layer surface resist coating, the source that carves, leak ohmic contact hole, then carry out the deposit that metal ohmic contact is leaked in source, peel off formation source and leak ohmic contact, and carry out alloy annealing:
A4 gate stack layer growth: the SiC sample surfaces that carries out leaking after ohmic contact in source is carried out to large area HF acid cleaning, then carry out Al
2o
3/ Nitrided-SiO
2the growth of composite gate dielectric layer:
The formation of A5 gate figure: glue is peeled off in the substrate surface painting at the gate stack of having grown, photoresist makes gate region by lithography, and electron beam evaporation forms grid metal, then peels off and realizes gate figure;
A6 electrode fabrication.
2. manufacture method according to claim 1, is characterized in that, described steps A 2 detailed processes are as follows,
The P type SiC epitaxial wafer sample that A21 was cleaned surface is put in the middle of PECVD, large area deposit SiO
2layer, thickness is 60nm;
A22 in deposit SiO
2the SiC sample surfaces resist coating of layer, and make source, drain region by lithography; Then in the middle of HF acid solution by the SiO without photoresist protection
2layer washes, and exposes source and leaks high temperature Implantation region;
A23 puts into high temperature ion implantor by the SiC sample that exposes source and drain areas, at 400 ℃, divides and carries out high temperature nitrogen Implantation four times, and dosage and energy are as follows: 400 ℃: 5 × 10
14㎝
-2/ 30K, 6.0 × 10
14㎝
-2/ 60K, 8 × 10
14㎝
-2/ 120K, 1.5 × 10
15㎝
-2/ 190K;
A24 cleans in HF solution the sample having carried out after high temperature Implantation, removes surperficial SiO
2barrier layer;
A25 is by SiO
2the SiC sample that barrier layer is removed is put into the high-temperature annealing furnace 30min that anneals at 1600 ℃.
3. manufacture method according to claim 1, is characterized in that, described steps A 3 detailed processes are as follows:
A31 peels off glue, whirl coating to the SiC sample surfaces painting of having carried out high annealing;
A32 was getting rid of SiC sample surfaces resist coating, the whirl coating of glue, and ohmic contact hole is leaked in the source that makes by lithography;
It is that the Al/Ni/Au of 150nm/50nm/200nm is as metal ohmic contact that A33 evaporates thickness on the SiC sample surfaces that carves drain contact hole, source;
A34 peels off formation source leakage ohmic contact figure to having steamed the SiC sample of metal;
A35 is placed in annealing furnace alloy at 950 ℃ by the SiC sample that has carried out ohmic contact and anneals 30 minutes.
4. manufacture method according to claim 1, is characterized in that, described steps A 4 detailed processes are as follows:
A41 puts into high temperature oxidation furnace by the SiC sample that has carried out ohmic contact, in the time of 1180 ℃, passes into purity oxygen, is oxidized the positive 10min of SiC epitaxial wafer, the SiO that generation thickness is 8nm under dry oxygen condition
2oxide-film;
A42 to growth oxide-film carry out nitrogenize: in electron cyclotron resonace ECR-PEMOCVD system to the SiO having generated
2oxide-film carries out nitrogen plasma treatment, and process conditions are: microwave power 625W, temperature is 600 ℃, N
2flow is 50sccm, and plasma treatment time is 7.5min;
A43 puts into atomic layer deposition reactions chamber by the SiC sample carrying out after nitrogen plasma treatment, with trimethyl aluminium TMA and H
2o is source, and temperature is 300 ℃, and air pressure is 2Torr, obtains the Al that thickness is 20nm
2o
3film.
5. manufacture method according to claim 1, is characterized in that, described steps A 5 adopts two kinds of metals of Ni/Au of 20nm/240nm to do grid metal; Its detailed process is as follows:
A51 is coated with and peels off glue, whirl coating at the SiC sample surfaces that has carried out the growth of large area gate stack;
A52 is being painted with the SiC sample surfaces resist coating of peeling off glue, and whirl coating, utilizes grid version to make grid metallic region by lithography;
It is that the Ni/Au of 20nm/240nm is as grid contacting metal that A53 evaporates thickness on the SiC sample surfaces that carves grid contact hole;
A54 utilizes stripping means to form gate figure.
6. manufacture method according to claim 1, is characterized in that, described steps A 6, and wherein the making of interconnect electrode adopts two kinds of metals of Ti/Au, and thickness is respectively 50nm/200nm; Comprise the following steps:
A61 is making SiC sample surfaces resist coating, the whirl coating of grid metal;
A62 utilizes the anti-version of grid oxygen to make non-gate stack region by lithography; Then sample is put into HF acid solution and carried out rinsing, remove the gate stack in non-grid oxygen region;
A63 peels off glue, whirl coating in the SiC sample surfaces painting of the gate stack of having removed non-grid oxygen region;
A64 is being painted with SiC sample surfaces resist coating, the whirl coating of peeling off glue;
A65 utilizes the photoetching of interconnection contact version, carve grid, source, leakage contact interconnect area '
It is that the Ti/Au of 30nm/200nm is as grid contacting metal that A66 evaporates thickness on the SiC sample surfaces that carves grid contact hole;
A67 utilizes stripping means to form grid, source, leakage interconnection graph.
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| CN109003895A (en) * | 2018-07-19 | 2018-12-14 | 大连理工大学 | A kind of production method improving SiC MOSFET element stability |
| CN109003895B (en) * | 2018-07-19 | 2021-06-08 | 大连理工大学 | Manufacturing method for improving performance stability of SiC MOSFET device |
| CN109801840A (en) * | 2018-12-04 | 2019-05-24 | 中国科学院微电子研究所 | A kind of method and SiC device improving SiC device interface feature |
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Application publication date: 20140416 |