CN105470288B - Delta channel doping SiC vertical power MOS device production methods - Google Patents
Delta channel doping SiC vertical power MOS device production methods Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
Abstract
A kind of Delta channel dopings SiC vertical power MOS device production methods, step are followed successively by N/N+ type SiC epitaxial wafer surface cleans；Layering doping is carried out in CVD stoves；Carve the areas P base and high temperature Al ion implantings；Carve N+ doping source regions and high temperature N ion implantings；It carves P+ contact areas and carries out high temperature Al ion implantings；Carbon protective film is formed on N/N+ type SiC epitaxial wafers surface；High temperature tension is annealed；Surface carbon film removal；Acid cleaning；SiO2Insulating layer growth；Bottom drain electrode growth；It applies stripping glue, photoresist, carve source contact hole, carry out source Metal deposition, and remove and form source figure；Source-drain electrode is annealed；The formation of gate electrode；Grid, source interconnection electrode are formed.The present invention can effectively improve the raceway groove effective mobility of vertical power MOS device, reduce the threshold voltage of device, improve the on state characteristic of vertical power device.
Description
Technical field
The present invention relates to microelectronics technologies, more particularly to a kind of Delta channel dopings SiC vertical power MOS devices
The production method of part.To reduce the threshold voltage of SiC vertical power MOS devices, raceway groove effective mobility is improved, so as to improve
The on state characteristic of power MOS (Metal Oxide Semiconductor) device.
Background technology
SiC has unique physics, chemistry and electrology characteristic, is extremely answered in high temperature, high frequency, high-power and radioresistance etc.
With the extremely potential semi-conducting material in field.The improvement of on state characteristic and changing for transient response of SiC power MOSFET
Kind is always the difficult point of power device.Although current lot of domestic and foreign seminar carries structure and surface texture by improving device
It is expected to improve the on state characteristic of device, such as how sub- accumulation area, also UMOS structures etc. are formed in device surface, but due to
The formation in surface multiple subarea domain, many devices are normally opens.
Invention content
It is an object of the invention to the deficiency for above-mentioned technique and structure, propose a kind of Delta channel dopings SiC's
The production method of vertical power MOS device uses raceway groove to carry out Delta layering doping to improve SiC MISFET devices in height
Reliability when temperature, high-power applications, while device being made to be maintained at normally-off states.
To achieve the goals above, the technical scheme is that：A kind of Delta channel dopings SiC vertical power MOS devices
Part production method, which is characterized in that the production method includes the following steps：
A1, substrate surface cleaning：Standardised wet methods technique cleaning is carried out to the surface of N-/N+ type SiC epitaxial wafers；
The formation of A2, Delta channel doping layer：Delta channel doping layers are formed on epitaxial wafer surface；
The formation in the area A3, P-base：The N-/N+ type SiC epitaxial wafers surface of Delta channel doping layers has been formed on surface
Resist coating carves the areas P-base high temperature tension region, then carries out the areas P-base high temperature Al ion implantings；
A4, N+ source region high temperature tension：After carrying out the regions P-base Al high temperature tensions, carves N+ and mix
Then miscellaneous source region carries out N+ source region high temperature N ion implantings；
The contact zone A5, P+ high temperature tension：N-/N+ type SiC extensions after having carried out N+ source region high temperature tensions
Piece surface carves P+ doped region windows, then carries out P+ high temperature tensions；
The formation of A6, surface carbon protective film：After having carried out n-type doping high temperature Al ion implantings, in N-/N+ types SiC
Epitaxial wafer surface forms carbon protective film；
A7, high temperature tension activation：1600 DEG C of high temperature tension annealing are carried out to having formed carbon protective film；
The removal of A8, surface carbon film：Surface carbon film is carried out to carrying out the SiC epitaxial wafers after high temperature tension is annealed
Removal：
A9, gate dielectric layer are grown and the formation of grid oxygen figure：The SiC epitaxial wafers for eliminating surface carbon film are subjected to large area
HF acid cleans, and then carries out SiO2The growth of gate dielectric layer and pattern etching；
The formation of A10, bottom drain electrode：To having carried out SiO2The SiC epitaxial wafers of gate dielectric layer carry out bottom drain electrode
Growth；
The formation of A11, source region electrode：After the growth for having carried out bottom drain electrode, applies and remove on SiC epitaxial wafers surface
Glue, photoresist carve source contact hole, carry out source Metal deposition, and remove and form source figure；
A12, source-drain electrode annealing：Entire device to having deposited source-drain electrode carries out source-drain electrode annealing；
The formation of A13, gate electrode：SiC epitaxial wafers to having carried out source-drain electrode annealing carry out the formation of gate electrode；
The formation of A14, grid, source interconnection electrode：SiC epitaxial wafers surface to forming gate electrode applies stripping glue, photoresist, profit
Grid, source contact hole are made by lithography with contact version, carry out grid, source interconnection Metal deposition, and remove and form grid, source interconnection graph.
The specific process step of the step A2 is：
A21, the N-/N+ type SiC epitaxial wafers that surface is washed are put into CVD epitaxial furnaces, face deposit big first is dense
Degree is 2 × 1014cm-3Thickness is the first SiC layer of 45nm；
A22, thickness is deposited out on it deposited the first SiC layer as 5nm nitratings a concentration of 2 × 1018cm-3The 2nd SiC
Layer；
A23, thickness is deposited out on it deposited the second SiC layer as a concentration of the 2 × 10 of 45nm14cm-3Third SiC layer；
A24, thickness is deposited out on it deposited third SiC layer as 5nm nitratings a concentration of 2 × 1018cm-3The 4th SiC
Layer；
A25, thickness is deposited out on it deposited the 4th SiC layer as a concentration of the 2 × 10 of 45nm14cm-3The 5th SiC layer；
The specific process step of the step A3 is：
A31, the N-/N+ type SiC epitaxial wafers surface large area that Delta channel doping layers have been formed on surface deposit one layer
Al, thickness are masks of the 2um as high temperature tension；
A32, the N-/N+ type SiC epitaxial wafers surface resist coating of Al films has been deposited on surface, has carved the areas P-base height
Warm ion implanted regions；
A33, in the SiO for the N-/N+ type SiC epitaxial wafer surface depositions 50nm for having made the regions P-base by lithography2Layer；
A34, SiO will have been carried out2The SiC epitaxial wafers of deposit are put into high temperature tension machine, are carried out in four times at 400 DEG C
High temperature Al ion implantings, the dosage and energy of four high temperature Al ion implantings are followed successively by：4.9×1012㎝-2/ 100K, 7.5 ×
1012㎝-2/ 200K, 9.8 × 1012㎝-2/ 350K, 2 × 1012㎝-2/550K；
A35, it is cleaned in HF solution to having carried out the SiC epitaxial wafers after high temperature tension, removes the SiO on surface2Resistance
Barrier and Al mask layers.
The specific process step of the step A4 is：
A41, surface SiO is being eliminated2The SiC epitaxial wafer surface depositions of barrier layer and Al mask layers deposit one layer of Al, thick
Degree is masks of the 2um as high temperature source N ion implantings；
A42, in SiC epitaxial wafers surface resist coating, the whirl coating that deposited Al masks, make high temperature source N ion implantings by lithography
Area；
A43, in the SiO for the one layer of 50nm of SiC epitaxial wafers surface deposition that deposited Al masks2Layer is used as high temperature source N
The barrier layer of ion implanting；
A44, SiO will have been carried out2The SiC epitaxial wafers of deposit are put into high temperature tension machine, are carried out in four times at 400 DEG C
High temperature high temperature N ion implantings, the dosage and energy of four high temperature high temperature N ion implantings are followed successively by：5×1014㎝-2/ 30K, 6.0
×1014㎝-2/ 60K, 8 × 1014㎝-2/ 120K, 1.5 × 1015㎝-2/190K；
A45, it is cleaned in HF acid solutions to having carried out the SiC epitaxial wafers after high temperature N ion implantings, removes surface
SiO2Barrier layer and Al mask layers.
The specific process step of the step A5 is：
A51, surface SiO is being eliminated2The SiC epitaxial wafer surface depositions of barrier layer and Al mask layers deposit a layer thickness and are
The Al of 2um, the mask as high temperature Al ion implantings；
A52, in SiC epitaxial wafers surface resist coating, the whirl coating that deposited Al masks, make high temperature Al ion implanted regions by lithography
Window；
A53, in the SiO for the one layer of 50nm of SiC epitaxial wafers surface deposition that deposited Al masks2Layer as high temperature Al from
The barrier layer of son injection；
A54, SiO will have been carried out2The SiC epitaxial wafers of deposit are put into high temperature tension machine, are carried out in four times at 400 DEG C
High temperature Al ion implantings, the dosage and energy of four high temperature Al ion implantings are followed successively by：2×1014㎝-2/ 30K, 3.0 × 1014
㎝-2/ 80K, 5 × 1014㎝-2/ 150K, 1.0 × 1015㎝-2/260K；
A55, it is cleaned in HF acid solutions to having carried out the SiC epitaxial wafers after high temperature Al ion implantings, removes surface
SiO2Barrier layer and the barrier layers Al.
The specific process step of the step A6 is：
A61, surface SiO is being removed2SiC epitaxial wafers surface resist coating, the whirl coating on barrier layer and the barrier layers Al, are put into roasting
Front baking 1 minute at 90 DEG C in case；
A62, it the SiC epitaxial wafers crossed of front baking will be carried out will be put into high-temperature annealing furnace, be kept for 30 minutes at 600 DEG C, to light
Photoresist is carbonized, and carbon film is formed on SiC epitaxial wafers surface；
A63, cool down to the SiC epitaxial wafers for carrying out carbonization.
The specific process step of the step A7 is：
A71, the SiC epitaxial wafers of carbonization are placed in high-temperature annealing furnace, down by have carbon film one, are evacuated down to 10- 7Torr, fills Ar gas, is gradually warming up to 1600 DEG C, is stopped 30 minutes at 1600 DEG C, carries out high temperature tension annealing；
A72, when high-temperature annealing furnace is cooled to room temperature, SiC epitaxial wafers are taken out from high-temperature annealing furnace.
The specific process step of the step A8 is：
A81, the SiC epitaxial wafers of high annealing are put into RIE reative cells, the one side with carbon film upward, shuts reaction
Room valve opens N2Valve leads to N to 1/4260 seconds, it is then turned off nitrogen valve；
A82, the N that 60 seconds have been carried out to the SiC epitaxial wafers with carbon film2After flushing, oil pump is opened, waits until the sound of oil pump
The change of tune is big and opens pump valve completely when becoming stable, until pump is stablized 20-30 minutes；
A83, oxygen valve is opened, until the pressure of chamber reaches 9-12mT；
A84, cooling system is opened, adjusts oxygen flow to 47sccm；
A85, radio frequency network adapter, 90 minutes carbon films for removing SiC epitaxial wafers surface of timing are opened；
A86, turn off network adapter power supply, turn off O2；
A87, system is depressured to normal pressure, turns off cooling system, to filling N inside RIE reative cells2Until reactor chamber door can
To open, SiC epitaxial wafers are taken out.
The specific process step of the step A9 is：
A91, HF acid cleanings are carried out to the SiC epitaxial wafers for eliminating surface carbon film；
A92, it HF acid cleaning SiC epitaxial wafers will be carried out is put into high temperature oxidation furnace and heats, at 1180 DEG C, be passed through pure
Oxygen, aoxidizes SiC epitaxial wafers front 10 hours under the conditions of dry oxygen, generates the SiO that thickness is 50nm2Oxidation film；
A93, the oxidation film of growth is nitrogenized：To the SiO of growth2The NO that oxidation film carries out 2 hours at 1175 DEG C is moved back
Fire；
The specific process step of the step A10 is：
A101, having formed SiO2The SiC epitaxial wafers of gate dielectric layer are put into eb evaporation chambers；
A102, evaporation thickness is the Ni/Au of 20nm/240nm as drain contact metal on the SiC epitaxial wafers back side.
The specific process step of the step A11 is：
A111, stripping glue, photoresist are applied in the SiC epitaxial wafers front for having carried out leakage underlayer electrode making, light is cleaned in photoetching
Photoresist, stripping glue, expose effective source electrode contact area；
A112, SiC epitaxial wafer are put into eb evaporation chambers；
A113, SiC epitaxial wafers front evaporation thickness be 20nm/240nm Ni/Au as source contacting metal；
A114, stripping form source contacting metal figure.
The specific process step of the step A12 is：
The SiC epitaxial wafers for having carried out source-drain electrode making are placed in annealing furnace the alloy at 950 DEG C to anneal 30 minutes.
The specific process step of the step A13 is：
A131, stripping glue, whirl coating are applied on the SiC epitaxial wafers surface for having carried out source-drain electrode annealing；
A132, it is being painted with the SiC epitaxial wafers surface resist coating for removing glue, whirl coating makes grid metal area by lithography using grid version
Domain；
A133, evaporation thickness is the Ni/Au of 20nm/240nm as grid on the SiC epitaxial wafers surface for carve grid contact hole
Contacting metal；
A134, gate figure is formed using stripping means.
The specific process step of the step A14 is：
A141, stripping glue, resist coating are applied on the SiC epitaxial wafers surface for having made grid metal；
A142, grid and source electrode interconnection window are carved using interconnection reticle；
A143, the Ti/Au works that thickness is 30nm/200nm are evaporated on the SiC epitaxial wafers surface for carving grid, source contact hole
For grid, source contacting metal；
A144, grid, source interconnection metallic pattern are formed using stripping means.
Increase the growth step of sacrificial oxide layer between the step A8 and A9, specific embodiment is：
（a）, the SiC epitaxial wafers for carrying out high annealing are put into high temperature oxidation furnace, at 1200 DEG C in pure dry oxygen item
SiC epitaxial wafers surface 30min is aoxidized under part, and the SiO that thickness is 20nm is generated in SiC epitaxial wafers front2Oxidation film；
(b), SiO will be grown2The SiC epitaxial wafers of oxidation film are put into HF acid, and the oxide layer on surface is washed.
It has the following advantages that compared with prior art：
The present invention is by carrying out the surface of vertical power MOS device the Delta channel dopings of the nm orders of magnitude, in doped layer
Electronics two-dimensional gas is formed, so as to effectively improve the channel mobility of vertical power MOS device device, while reducing threshold value electricity
Pressure, improves the on state characteristic of device.
Description of the drawings
Fig. 1 is the total technological process figure of first embodiment of the invention；
Fig. 2 is the total technological process figure of second embodiment of the invention；
Fig. 3 is the step 1 of first embodiment of the invention to the technique content flow figure of step 8；
Fig. 4 is the step 9 of the first embodiment of the present invention to the technique content flow figure of step 13；
Fig. 5 is the technique content flow figure of the step A to step H of second embodiment of the invention；
Fig. 6 is the technique content flow figure of the step I to step N of second embodiment of the invention.
Specific implementation mode
With reference to specific embodiment, the specific implementation mode of the present invention is described in further detail.Implement below
Example is not limited to the scope of the present invention for illustrating the present invention.
Embodiment 1：
Referring to Fig.1, the preparation of Fig. 3 and Fig. 4, first embodiment of the invention realize that steps are as follows：
Step 1, surface clean is carried out to 4H-SiC N-/N+ type SiC epitaxial wafers using standard cleaning method RCA, it is specific clear
It is as follows to wash journey：
4H-SiC N-/N+ type SiC epitaxial wafers are immersed in each 5min in acetone, absolute ethyl alcohol by (1a) successively, then spend from
Sub- water rinses, to remove the grease on SiC epitaxial wafers surface；
SiC epitaxial wafers after (1b) cleans first time are placed in H2SO4∶H2O2= 1∶1（Volume ratio）Solution in impregnate
15min, H2SO4A concentration of 98%, H2O2A concentration of 27%, then rinsed with deionized water；
SiC epitaxial wafers after (1c) cleans second are placed in HF: H2O = 1∶10 （Volume ratio）Solution in impregnate
1min is to float natural oxidizing layer, and a concentration of the 40% of HF acid, it is used in combination deionized water to rinse；
SiC epitaxial wafers after (1d) cleans third time are immersed in NH4OH∶H2O2∶DIW = 3∶3∶10 （Volume ratio）It is molten
It is boiled in liquid, NH4A concentration of 28%, the H of OH2O2A concentration of 27%, then rinsed with deionized water；
SiC epitaxial wafers after 4th cleaning are placed in HF: H by (1e)2O = 1∶10 （Volume ratio）Solution in impregnate
A concentration of the 40% of 30s, HF acid, is used in combination deionized water to rinse；
(1f) is by the SiC epitaxial wafers after the 5th cleaning HCl: H2O2∶DIW = 3∶3∶10 （Volume ratio）Solution in
It boils, a concentration of 10%, the H of HCl2O2A concentration of 27%, rinsed with deionized water；
(1g) is by the SiC epitaxial wafers after the 6th cleaning HF: H2O =1∶10（Volume ratio）Solution in impregnate 30s, and
It is rinsed with deionized water, a concentration of the 40% of HF acid, finally uses N2Rifle dries up；
Step 2, Delta channel doping layers are formed on SiC epitaxial wafers surface, specific operation process is as follows:
Cleaned SiC epitaxial wafers are put into hot-wall cvd stove by (2a), N- extension placed face downs；
(2b) opens vacuum valve, and vacuum pressure is modulated 10-7Torr or less；
(2c) opens H2Valve, adjusting flow velocity are 2slm；
Growth temperature is modulated 1600 DEG C by (2d), and it is 700Torr to be maintained at air pressure in growth course；
(2e) is by SiH4、C3H8Flow velocity modulate 3sccm, C/Si ratios be 3；
(2f) opens N2Control valve, N2Pressure is 1kgf/cm2, the time is 120 μ s, grows the first nitrogen of Delta doped layers
Doped layer；
(2g) turns off N2The control valve time is 4ms, grows the first undoped layer of Delta doped layers；
(2h) opens N2The control valve time is 120 μ s；Grow the second nitrogen doped layer of Delta doped layers；
(2i) turns off N2The control valve time is 4ms；Grow the second undoped layer of Delta doped layers；
(2j) opens N2The control valve time is 120 μ s；Grow the third doped layer of Delta doped layers；
(2k) turns off N2The control valve time is 4ms；Grow the third undoped layer of Delta doped layers；
(2l) opens N2The control valve time is 120 μ s；Grow the 4th doped layer of Delta doped layers；
(2m) turns off N2The control valve time is 4ms；Grow the 4th undoped layer of Delta doped layers；
(2n) cools down, and extension furnace temperature is dropped to room temperature, 5 DEG C/min of rate；
(2o) takes out sample from epitaxial furnace.
Step 3, P-base high temperature tensions region is made on the positive surface of SiC epitaxial wafers：
The N-/N+ type SiC epitaxial wafers that surface has been formed Delta channel doping layers by (3a) are put into eb evaporation chambers
In, on surface, large area deposits one layer of Al, and thickness is masks of the 2um as high temperature tension；
(3b) deposited the N-/N+ type SiC epitaxial wafers surface resist coating of Al films on surface, carve the areas P-base height
Warm ion implanted regions；
The N-/N+ type SiC epitaxial wafers for having carried out photoetching are immersed in HF acid by (3c), remove the Al of ion implanted regions；
The N-/N+ type SiC epitaxial wafers for eliminating ion implanted regions Al are put into PECVD stoves by (3d), in N-/N+ types
The SiO of SiC epitaxial wafer surface depositions 50nm2Layer；
(3e) will carry out SiO2The SiC epitaxial wafers of deposit are put into high temperature tension machine, are carried out in four times at 400 DEG C
High temperature Al ion implantings, the dosage and energy of four high temperature Al ion implantings are followed successively by：4.9×1012㎝-2/ 100K, 7.5 ×
1012㎝-2/ 200K, 9.8 × 1012㎝-2/ 350K, 2 × 1012㎝-2/550K；
(3f) cleans the SiC epitaxial wafers after having carried out high temperature tension in HF solution, removes the SiO on surface2Resistance
Barrier and Al mask layers.
Step 4, source region ion implanting is carried out on the regions P-base：
(4a) is to eliminating surface SiO2The SiC epitaxial wafers surface large area of barrier layer and Al mask layers applies stripping glue；
The SiC epitaxial wafers of coated stripping glue are put into eb evaporation chambers by (4b), the Al for being 2 μm in surface deposition thickness
Layer；
(4c) deposited Al layers of SiC epitaxial wafers surface resist coating；
(4d) to the SiC epitaxial wafer whirl coatings of coated photoresist, before then being carried out at 90 DEG C to the SiC epitaxial wafers for getting rid of glue
It dries；The front baking time is 1min；
(4e) exposes the SiC epitaxial wafers after front baking using N-source injection reticles；
(4f) develops in positivity developer solution to the SiC epitaxial wafers for exposing light, and solution temperature is 20 DEG C, and developing time is
20s；
SiC epitaxial wafers after development are carried out post bake by (4g) in ultra-pure water, and coolant-temperature gage is 20 DEG C, and the post bake time is 20s；
(4h) removes exposed photoresist in equipment for burning-off photoresist by plasma, exposes effective regions N-source；
(4i) rinses the SiC epitaxial wafers for exposing the regions N-source in HF acid solutions, removes the regions N-source
Al layers；
The SiC epitaxial wafers for exposing the regions N-source are put into PECVD stoves by (4j), and deposition thickness is the SiO of 50nm2
Layer；
(4k) will deposited SiO2The SiC epitaxial wafers of floor are put into high temperature tension room and carry out source N ion implantings, by temperature
400 DEG C are adjusted to, implantation dosage is as follows with energy：：5×1014㎝-2/ 30K, 6.0 × 1014㎝-2/ 60K, 8 × 1014㎝-2/ 120K,
1.5×1015㎝-2/190K；Implantation concentration is 1 × 1020㎝-3Left and right, depth are 0.3 μm or so；
(4l) is 1 in volume ratio to the SiC epitaxial wafers after injection：10 HF（A concentration of 40%）With the mixed solution of water
Rinsing, removes the SiO on surface2Layer；
(4m) is to eliminating surface SiO2The SiC epitaxial wafers of layer are removed, and the remaining Al in surface is removed;
Step 5, p-type contact zone ion implanting is carried out on the regions P-base：
(5a) applies stripping glue to the SiC epitaxial wafers surface large area after having carried out the injection of the regions N-source；
The SiC epitaxial wafers of coated stripping glue are put into eb evaporation chambers by (5b), the Al for being 2 μm in surface deposition thickness
Layer；
(5c) deposited Al layers of SiC epitaxial wafers surface resist coating；
(5d) to the SiC epitaxial wafer whirl coatings of coated photoresist, before then being carried out at 90 DEG C to the SiC epitaxial wafers for getting rid of glue
It dries；The front baking time is 1min；
(5e) exposes the SiC epitaxial wafers after front baking using P contact injection reticles；
(5f) develops in positivity developer solution to the SiC epitaxial wafers for exposing light, and solution temperature is 20 DEG C, and developing time is
20s；
SiC epitaxial wafers after development are carried out post bake by (5g) in ultra-pure water, and coolant-temperature gage is 20 DEG C, and the post bake time is 20s；
(5h) removes exposed photoresist in equipment for burning-off photoresist by plasma, exposes effective p-type contact region；
(5i) rinses the SiC epitaxial wafers for exposing p-type contact zone in HF acid solutions, removes the Al of p-type contact region
Layer；
The SiC epitaxial wafers for exposing p-type contact zone are put into PECVD stoves by (5j), and deposition thickness is the SiO of 50nm2Layer；
(5k) will wash p-type contact zone SiO2The SiC epitaxial wafers of floor be put into high temperature tension room carry out source and drain Al from
Son injection, is adjusted to 400 DEG C, implantation dosage is as follows with energy by temperature：：2×1014㎝-2/ 30K, 3.0 × 1014㎝-2/ 80K, 5 ×
1014㎝-2/ 150K, 1.0 × 1015㎝-2/260K；Implantation concentration is 1 × 1020㎝-3Left and right, depth are 0.3 μm or so；
(5l) is 1 in volume ratio to the SiC epitaxial wafers after injection：10 HF（A concentration of 40%）With the mixed solution of water
Rinsing, removes the SiO on surface2Layer；
(5m) is to eliminating surface SiO2The SiC epitaxial wafers of layer are removed, and the remaining Al in surface is removed;
Step 6, high temperature tension annealing carbon protective film is made in N-/N+SiC epitaxial wafers front：
(6a) is in the SiC epitaxial wafers surface resist coating for removing l layers of surface A;
(6b) whirl coating is put into oven front baking 1 minute at 90 DEG C；
(6c) is put into the SiC epitaxial wafers that front baking is crossed are carried out in high-temperature annealing furnace, and carbon is face-up；
(6d) is vacuumized 2 hours, and pressure reaches 4 ~ 5E-7Torr；
(6e) fills Ar gas, and setting output pressure is 12psi；
(6f) opens fan；
Power is adjusted to 10% by (6g) first, 30% power is then transferred to according to 5%/2min speed, then carefully
It adjusts power to be adjusted to temperature rise to 600 DEG C according to the power of 2%/2min, is kept for 30 minutes at 600 DEG C；
(6h) turns off heating power adjusting knob；
(6i) takes out the SiC epitaxial wafers with carbon film；
Step 7, high temperature tension is annealed；
SiC epitaxial wafers with carbon protective film are put into high-temperature annealing furnace by (7a), and one with carbon face is down；
(7b) is vacuumized, and pressure reaches 4 ~ 5E-7Torr；
(7c) fills Ar gas, and setting output pressure is 12psi；
(7d) opens fan；
Power is adjusted to 60% by (7e) first, is then adjusted to temperature rise to 1600 DEG C according to 1%/10s speed,
It is kept for 30 minutes at 1600 DEG C；
(7f) turns off heating power adjusting knob；
(7i) takes out the SiC epitaxial wafers after annealing by high temperature tension with carbon film；
Step 8, remove the positive carbon protective film of N-/N+SiC epitaxial wafers：
(8a) in RIE cavitys to filling N2, open RIE reactor chamber doors；
(8b) will be placed on center by the SiC epitaxial wafers after high annealing, and the one side with carbon film upward, uses tweezers
It compresses, shut reactor chamber door and then tightens valve；
(8c) starts logical O2, flow velocity 47sccm；
(8d) opens radio frequency network adapter, and regulation power is set as 18 ± 3W；
(8e) starts the carbon film on 90 minutes removal SiC epitaxial wafers surfaces of timing；
(8f) turns off radio frequency network adapter, turns off O2；
(8g) fills N2Until reative cell chamber door can automatically open, take out；
The SiC epitaxial wafers for getting rid of surface carbon film are carried out RCA cleanings by (8h)；
Step 9, large area deposition SiO2Gate dielectric layer：
(9a) will go the SiC epitaxial wafers for having carried out RCA cleanings to be put into high temperature oxidation furnace, the N for being 750 DEG C in temperature2Ring
It is pushed into oxidation furnace flat-temperature zone in border；
(9b) heats up to flat-temperature zone by 3 DEG C/min rates；
(9c) is passed through oxygen when temperature rises to 1150 DEG C, and oxygen flow 0.5l/min is aoxidized under the conditions of pure dry oxygen
SiC epitaxial wafers surface 10 hours generates the SiO that thickness is 50nm in SiC epitaxial wafers front2Oxidation film；
(9d) turns off O2, Ar is opened, leads to Ar gas 15 minutes；
(9e) heats up to flat-temperature zone according to 3 DEG C/min rates；
(9f) opens NO, flow 577sccm, time 2 h when temperature is raised to 1175 DEG C；
(9h) turns off NO gases, and furnace temperature is dropped to 900 DEG C；
(9i) turns off Ar gases, takes out；
Step 10, the formation of grid oxygen figure：
(10a) is in the SiO for carrying out large area deposition2The SiC epitaxial wafers surface resist coating of gate medium；Photoresist is got rid of,
Then front baking is carried out at 80 DEG C to the SiC epitaxial wafers for getting rid of glue；The front baking time is 10 ~ 15min；
(10b) exposes the SiC epitaxial wafers after front baking using grid oxygen reticle；
(10c) develops in positivity developer solution, and solution temperature is 20 DEG C, developing time 85s；
SiC epitaxial wafers after development are carried out post bake by (10d) in ultra-pure water, and coolant-temperature gage is 20 DEG C, and the post bake time is
85s；
(10e) removes exposed photoresist in equipment for burning-off photoresist by plasma, then will remove the SiC epitaxial wafers of photoresist
It is impregnated in HF acid, removes non-effective grid oxygen region, retain effective grid oxygen region；
Step 11, the formation of substrate leakage pole：
The SiC epitaxial wafers for forming gate dielectric layer are put into eb evaporation chambers by (11a)；
(11b) overleaf three kinds of metal Al/Ni/Au of large area evaporation do leakage Ohm contact electrode, and thickness is respectively
150nm, 50nm and 70nm leak Ohmic contact to form substrate；
Step 12, source Ohmic contact is made on the regions N+ and the regions P+：
(12a) applies stripping glue, whirl coating on the SiC epitaxial wafers surface for finishing underlayer electrode；
(12b) coated stripping glue SiC epitaxial wafers surface resist coating, whirl coating, then to getting rid of the SiC epitaxial wafers of glue
Front baking is carried out at 80 DEG C；The front baking time is 10 ~ 15min；
(12c) exposes the SiC epitaxial wafers after front baking using source contact reticle；
(12d) develops in positivity developer solution, and solution temperature is 20 DEG C, developing time 85s；
SiC epitaxial wafers after development are carried out post bake by (12e) in ultra-pure water, and coolant-temperature gage is 20 DEG C, and the post bake time is
85s；
(12f) removes exposed photoresist in equipment for burning-off photoresist by plasma, exposes effective source and drain areas；
The SiC epitaxial wafers for removing photoresist are impregnated 5 hours and are ultrasonically treated 1 point using acetone by (12g) in acetone
Clock, then acetone, alcohol washes are each primary again, remove the stripping glue of source and drain ohmic contact regions；Expose effective source contact area；
The SiC epitaxial wafers for removing glue are put into eb evaporation chambers by (12h), and large area evaporates three kinds of metal Al/Ni/Au
Source Ohm contact electrode is done, thickness is respectively 150nm, 50nm and 70nm, then realizes source and drain ohm using the method for stripping
Contact pattern；
The SiC epitaxial wafers for finishing source electrode are finally placed in annealing furnace and carry out 30 points of alloy annealing at 950 DEG C by (12i)
Clock；
The formation of step 13 gate electrode：
(13a) applies stripping glue, photoresist, whirl coating, then to getting rid of in the SiC epitaxial wafers front for having carried out source-drain electrode annealing
The SiC epitaxial wafers for crossing glue carry out front baking at 80 DEG C；The front baking time is 10 ~ 15min；
(13b) carves gate figure using gate electrode photolithography plate；
(13c) develops in positivity developer solution, and solution temperature is 20 DEG C, developing time 85s；
SiC epitaxial wafers after development are carried out post bake by (13d) in ultra-pure water, and coolant-temperature gage is 20 DEG C, and the post bake time is
85s；
(13e) removes exposed photoresist in equipment for burning-off photoresist by plasma, is then cleaned using deionized water；
(13f) and then the SiC epitaxial wafers for removing photoresist are impregnated 5 hours to and are utilized 1 point of acetone ultrasound in acetone
Clock, then acetone, alcohol washes are each primary again, remove the stripping glue in gate electrode region；Expose effective contact area；
(13g) is put into removing photoresist and removing the SiC epitaxial wafers of glue in eb evaporation chambers, large area evaporation
Ti/Au, thickness are 50nm/ 200nm；
(13m) forms last gate electrode by stripping means and contacts.
Step 14, the making of interconnection electrode：
(14a) applies stripping glue, whirl coating to the SiC epitaxial wafers surface that deposited grid metal；Resist coating, whirl coating are then right
The SiC epitaxial wafers for getting rid of glue carry out front baking at 80 DEG C；The front baking time is 10 ~ 15min；
(14b) exposes the SiC epitaxial wafers after front baking using interconnection contact version；
(14c) develops in positivity developer solution, and solution temperature is 20 DEG C, developing time 85s；
SiC epitaxial wafers after development are carried out post bake by (14d) in ultra-pure water, and coolant-temperature gage is 20 DEG C, and the post bake time is
85s；
(14e) removes exposed photoresist in equipment for burning-off photoresist by plasma, then will remove the SiC epitaxial wafers of photoresist
It impregnates 5 hours in acetone and 1 minute ultrasonic using acetone, then acetone, alcohol washes are each primary again, remove contact interconnection
The stripping glue in region；Expose effective contact area；
(14f) is put into removing photoresist and removing the SiC epitaxial wafers of glue in eb evaporation chambers, large area evaporation
Ti/Au, thickness are 50nm/ 200nm；
(14g) forms last electrode by stripping means and contacts.
Embodiment 2
Compared with Example 1, on the basis of the present embodiment is in embodiment 1, removing, N-/N+SiC extensions are positive
Carbon protective film and large area deposition SiO2The growth technique of one of sacrificial oxide layer is increased between gate dielectric layer, it can be more effective
The annealing of reduction high temperature tension caused by interface damage, it is effective to improve interface flatness.
As shown in Figure 2, Figure 5 and Figure 6, steps are as follows for the realization of the present embodiment 2（Other unmentioned technique contents and upper one
Embodiment is identical）：
Step I, the growth of sacrificial oxide layer：
(Ia) the SiC epitaxial wafers for carrying out high annealing are put into high temperature oxidation furnace, at 1200 DEG C in pure dry oxygen item
SiC epitaxial wafers surface 30min is aoxidized under part, and the SiO that thickness is 20nm is generated in SiC epitaxial wafers front2Oxidation film；
(Ib) SiO will be grown2The SiC epitaxial wafers of oxidation film are put into HF acid, and the oxide layer on surface is washed.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
With within principle, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention god.
Claims (14)
1. a kind of Delta channel dopings SiC vertical power MOS device production methods, which is characterized in that the production method include with
Lower step：
A1, substrate surface cleaning：Standardised wet methods technique cleaning is carried out to the surface of N-/N+ type SiC epitaxial wafers；
The formation of A2, Delta channel doping layer：Delta channel doping layers are formed on epitaxial wafer surface；
The formation in the area A3, P-base：The N-/N+ type SiC epitaxial wafers surface that Delta channel doping layers have been formed on surface applies light
Photoresist carves the areas P-base high temperature tension region, then carries out the areas P-base high temperature Al ion implantings；
A4, N+ source region high temperature tension：After carrying out the regions P-base Al high temperature tensions, N+ doped sources are carved
Then area carries out N+ source region high temperature N ion implantings；
The contact zone A5, P+ high temperature tension：N-/N+ type SiC epitaxial wafer tables after having carried out N+ source region high temperature tensions
Face carves P+ doped region windows, then carries out P+ high temperature tensions；
The formation of A6, surface carbon protective film：After having carried out n-type doping high temperature Al ion implantings, in N-/N+ type SiC extensions
Piece surface forms carbon protective film；
A7, high temperature tension activation：1600 DEG C of high temperature tension annealing are carried out to having formed carbon protective film；
The removal of A8, surface carbon film：Going for surface carbon film is carried out to carrying out the SiC epitaxial wafers after high temperature tension is annealed
It removes：
A9, gate dielectric layer are grown and the formation of grid oxygen figure：The SiC epitaxial wafers for eliminating surface carbon film are subjected to large area HF acid
Cleaning, then carries out SiO2The growth of gate dielectric layer and pattern etching；
The formation of A10, bottom drain electrode：To having carried out SiO2The SiC epitaxial wafers of gate dielectric layer carry out the growth of bottom drain electrode；
The formation of A11, source region electrode：After the growth for having carried out bottom drain electrode, SiC epitaxial wafers surface apply stripping glue,
Photoresist carves source contact hole, carries out source Metal deposition, and remove and form source figure；
A12, source-drain electrode annealing：Entire device to having deposited source-drain electrode carries out source-drain electrode annealing；
The formation of A13, gate electrode：SiC epitaxial wafers to having carried out source-drain electrode annealing carry out the formation of gate electrode；
The formation of A14, grid, source interconnection electrode：SiC epitaxial wafers surface to forming gate electrode applies stripping glue, photoresist, using connecing
Tactile version makes grid, source contact hole by lithography, carries out grid, source interconnection Metal deposition, and remove and form grid, source interconnection graph；
The specific process step of step A2 is：
(2f) opens N2 control valves, and N2 pressure is 1kgf/cm2, and the time is 120 μ s, grows the first N doping of Delta doped layers
Layer；
(2g) turns off the N2 control valve times for 4ms, grows the first undoped layer of Delta doped layers；
(2h) opens the N2 control valve times as 120 μ s；Grow the second nitrogen doped layer of Delta doped layers；
(2i) turns off the N2 control valve times for 4ms；Grow the second undoped layer of Delta doped layers；
(2j) opens the N2 control valve times as 120 μ s；Grow the third doped layer of Delta doped layers；
(2k) turns off the N2 control valve times for 4ms；Grow the third undoped layer of Delta doped layers；
(2l) opens the N2 control valve times as 120 μ s；Grow the 4th doped layer of Delta doped layers；
(2m) turns off the N2 control valve times for 4ms；Grow the 4th undoped layer of Delta doped layers.
2. Delta channel dopings SiC vertical power MOS device production methods as described in claim 1, which is characterized in that step
Suddenly the specific process step of A3 is：
A31, the N-/N+ type SiC epitaxial wafers surface large area that Delta channel doping layers have been formed on surface deposit one layer of Al,
Thickness is masks of the 2um as high temperature tension；
A32, deposited the N-/N+ type SiC epitaxial wafers surface resist coating of Al films on surface, carve the areas P-base high temperature from
Sub- injection zone；
A33, in the SiO for the N-/N+ type SiC epitaxial wafer surface depositions 50nm for having made the regions P-base by lithography2Layer；
A34, SiO will have been carried out2The SiC epitaxial wafers of deposit are put into high temperature tension machine, carry out high temperature in four times at 400 DEG C
Al ion implantings, the dosage and energy of four high temperature Al ion implantings are followed successively by：4.9×1012㎝-2/ 100K, 7.5 × 1012
㎝-2/ 200K, 9.8 × 1012㎝-2/ 350K, 2 × 1012㎝-2/550K；
A35, it is cleaned in HF solution to having carried out the SiC epitaxial wafers after high temperature tension, removes the SiO on surface2Barrier layer with
And Al mask layers.
3. Delta channel dopings SiC vertical power MOS device production methods as described in claim 1, which is characterized in that step
Suddenly the specific process step of A4 is：
A41, surface SiO is being eliminated2The SiC epitaxial wafer surface depositions of barrier layer and Al mask layers deposit one layer of Al, and thickness is
Masks of the 2um as high temperature source N ion implantings；
A42, in SiC epitaxial wafers surface resist coating, the whirl coating that deposited Al masks, make high temperature source N ion implanted regions by lithography；
A43, in the SiO for the one layer of 50nm of SiC epitaxial wafers surface deposition that deposited Al masks2Layer is noted as high temperature source N ions
The barrier layer entered；
A44, SiO will have been carried out2The SiC epitaxial wafers of deposit are put into high temperature tension machine, carry out high temperature in four times at 400 DEG C
High temperature N ion implantings, the dosage and energy of four high temperature high temperature N ion implantings are followed successively by：5×1014㎝-2/ 30K, 6.0 × 1014
㎝-2/ 60K, 8 × 1014㎝-2/ 120K, 1.5 × 1015㎝-2/190K；
A45, it is cleaned in HF acid solutions to having carried out the SiC epitaxial wafers after high temperature N ion implantings, removes the SiO on surface2Resistance
Barrier and Al mask layers.
4. Delta channel dopings SiC vertical power MOS device production methods as described in claim 1, which is characterized in that step
Suddenly the specific process step of A5 is：
A51, surface SiO is being eliminated2It is 2um's that the SiC epitaxial wafer surface depositions of barrier layer and Al mask layers, which deposit a layer thickness,
Al, the mask as high temperature Al ion implantings；
A52, in SiC epitaxial wafers surface resist coating, the whirl coating that deposited Al masks, make high temperature Al ion implanted region windows by lithography
Mouthful；
A53, in the SiO for the one layer of 50nm of SiC epitaxial wafers surface deposition that deposited Al masks2Layer is noted as high temperature Al ions
The barrier layer entered；
A54, SiO will have been carried out2The SiC epitaxial wafers of deposit are put into high temperature tension machine, carry out high temperature in four times at 400 DEG C
Al ion implantings, the dosage and energy of four high temperature Al ion implantings are followed successively by：2×1014㎝-2/ 30K, 3.0 × 1014㎝-2/
80K, 5 × 1014㎝-2/ 150K, 1.0 × 1015㎝-2/260K；
A55, it is cleaned in HF acid solutions to having carried out the SiC epitaxial wafers after high temperature Al ion implantings, removes the SiO on surface2Resistance
Barrier and the barrier layers Al.
5. Delta channel dopings SiC vertical power MOS device production methods as described in claim 1, which is characterized in that step
Suddenly the specific process step of A6 is：
A61, surface SiO is being removed2SiC epitaxial wafers surface resist coating, the whirl coating on barrier layer and the barrier layers Al, are put into oven
Front baking 1 minute at 90 DEG C；
A62, it the SiC epitaxial wafers crossed of front baking will be carried out will be put into high-temperature annealing furnace, be kept for 30 minutes at 600 DEG C, to photoresist
It is carbonized, carbon film is formed on SiC epitaxial wafers surface；
A63, cool down to the SiC epitaxial wafers for carrying out carbonization.
6. Delta channel dopings SiC vertical power MOS device production methods as described in claim 1, which is characterized in that step
Suddenly the specific process step of A7 is：
A71, the SiC epitaxial wafers of carbonization are placed in high-temperature annealing furnace, down by have carbon film one, are evacuated down to 10-7Torr,
Ar gas is filled, is gradually warming up to 1600 DEG C, is stopped 30 minutes at 1600 DEG C, high temperature tension annealing is carried out；
A72, when high-temperature annealing furnace is cooled to room temperature, SiC epitaxial wafers are taken out from high-temperature annealing furnace.
7. Delta channel dopings SiC vertical power MOS device production methods as described in claim 1, which is characterized in that step
Suddenly the specific process step of A8 is：
A81, the SiC epitaxial wafers of high annealing are put into RIE reative cells, the one side with carbon film upward, shuts reative cell valve
Door opens N2Valve leads to N to 1/4260 seconds, it is then turned off nitrogen valve；
A82, the N that 60 seconds have been carried out to the SiC epitaxial wafers with carbon film2After flushing, oil pump is opened, until the sound of oil pump becomes
Pump valve is opened completely greatly and when becoming stable, until pump is stablized 20-30 minutes；
A83, oxygen valve is opened, until the pressure of chamber reaches 9-12mT；
A84, cooling system is opened, adjusts oxygen flow to 47sccm；
A85, radio frequency network adapter, 90 minutes carbon films for removing SiC epitaxial wafers surface of timing are opened；
A86, turn off network adapter power supply, turn off O2；
A87, system is depressured to normal pressure, turns off cooling system, to filling N inside RIE reative cells2Until reactor chamber door can be beaten
It opens, takes out SiC epitaxial wafers.
8. Delta channel dopings SiC vertical power MOS device production methods as described in claim 1, which is characterized in that step
Suddenly the specific process step of A9 is：
A91, HF acid cleanings are carried out to the SiC epitaxial wafers for eliminating surface carbon film；
A92, it HF acid cleaning SiC epitaxial wafers will be carried out is put into high temperature oxidation furnace and heats, and at 1180 DEG C, be passed through pure oxygen
Gas, aoxidizes SiC epitaxial wafers front 10 hours under the conditions of dry oxygen, generates the SiO that thickness is 50nm2Oxidation film；
A93, the oxidation film of growth is nitrogenized：To the SiO of growth2Oxidation film carries out NO annealing in 2 hours at 1175 DEG C.
9. Delta channel dopings SiC vertical power MOS device production methods as described in claim 1, which is characterized in that step
Suddenly the specific process step of A10 is：
A101, having formed SiO2The SiC epitaxial wafers of gate dielectric layer are put into eb evaporation chambers；
A102, evaporation thickness is the Ni/Au of 20nm/240nm as drain contact metal on the SiC epitaxial wafers back side.
10. Delta channel dopings SiC vertical power MOS device production methods as described in claim 1, which is characterized in that step
Suddenly the specific process step of A11 is：
A111, stripping glue, photoresist are applied in the SiC epitaxial wafers front for having carried out leakage underlayer electrode making, photoetching is cleaned in photoetching
Glue, stripping glue, expose effective source electrode contact area；
A112, SiC epitaxial wafer are put into eb evaporation chambers；
A113, SiC epitaxial wafers front evaporation thickness be 20nm/240nm Ni/Au as source contacting metal；
A114, stripping form source contacting metal figure.
11. Delta channel dopings SiC vertical power MOS device production methods as described in claim 1, which is characterized in that step
Suddenly the specific process step of A12 is：
The SiC epitaxial wafers for having carried out source-drain electrode making are placed in annealing furnace the alloy at 950 DEG C to anneal 30 minutes.
12. Delta channel dopings SiC vertical power MOS device production methods as described in claim 1, which is characterized in that step
Suddenly the specific process step of A13 is：
A131, stripping glue, whirl coating are applied on the SiC epitaxial wafers surface for having carried out source-drain electrode annealing；
A132, it is being painted with the SiC epitaxial wafers surface resist coating for removing glue, whirl coating makes grid metal region by lithography using grid version；
A133, the Ni/Au that evaporation thickness is 20nm/240nm on the SiC epitaxial wafers surface for carve grid contact hole are contacted as grid
Metal；
A134, gate figure is formed using stripping means.
13. Delta channel dopings SiC vertical power MOS device production methods as described in claim 1, which is characterized in that step
Suddenly the specific process step of A14 is：
A141, stripping glue, resist coating are applied on the SiC epitaxial wafers surface for having made grid metal；
A142, grid and source electrode interconnection window are carved using interconnection reticle；
A143, on the SiC epitaxial wafers surface for carving grid, source contact hole evaporate thickness be 30nm/200nm Ti/Au as grid,
Source contacting metal；
A144, grid, source interconnection metallic pattern are formed using stripping means.
14. Delta channel dopings SiC vertical power MOS device production methods as described in claim 1, which is characterized in that
Increase the growth step of sacrificial oxide layer between the step A8 and A9, specific embodiment is：
（a）, the SiC epitaxial wafers for carrying out high annealing are put into high temperature oxidation furnace, under the conditions of at 1200 DEG C in pure dry oxygen
SiC epitaxial wafers surface 30min is aoxidized, the SiO that thickness is 20nm is generated in SiC epitaxial wafers front2Oxidation film；
(b), SiO will be grown2The SiC epitaxial wafers of oxidation film are put into HF acid, and the oxide layer on surface is washed.
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