CN104766798A - Method for improving roughness of SiC/SiO2 interface - Google Patents
Method for improving roughness of SiC/SiO2 interface Download PDFInfo
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- CN104766798A CN104766798A CN201510141650.2A CN201510141650A CN104766798A CN 104766798 A CN104766798 A CN 104766798A CN 201510141650 A CN201510141650 A CN 201510141650A CN 104766798 A CN104766798 A CN 104766798A
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- 238000000034 method Methods 0.000 title claims abstract description 36
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 title abstract description 12
- 229910052681 coesite Inorganic materials 0.000 title abstract description 6
- 229910052906 cristobalite Inorganic materials 0.000 title abstract description 6
- 239000000377 silicon dioxide Substances 0.000 title abstract description 6
- 235000012239 silicon dioxide Nutrition 0.000 title abstract description 6
- 229910052682 stishovite Inorganic materials 0.000 title abstract description 6
- 229910052905 tridymite Inorganic materials 0.000 title abstract description 6
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 54
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 53
- 238000000137 annealing Methods 0.000 claims abstract description 47
- 238000004140 cleaning Methods 0.000 claims abstract description 24
- 239000002253 acid Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 17
- 239000011248 coating agent Substances 0.000 claims description 16
- 238000000576 coating method Methods 0.000 claims description 16
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 15
- 229910052760 oxygen Inorganic materials 0.000 claims description 15
- 239000001301 oxygen Substances 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- 238000005516 engineering process Methods 0.000 claims description 14
- 239000007789 gas Substances 0.000 claims description 12
- 239000003292 glue Substances 0.000 claims description 12
- 230000001681 protective effect Effects 0.000 claims description 10
- 230000008020 evaporation Effects 0.000 claims description 7
- 238000001704 evaporation Methods 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 238000003763 carbonization Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 238000001816 cooling Methods 0.000 claims description 4
- 230000000694 effects Effects 0.000 claims description 2
- 238000011010 flushing procedure Methods 0.000 claims description 2
- 238000001459 lithography Methods 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 14
- 230000005684 electric field Effects 0.000 abstract description 4
- 230000008569 process Effects 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 229910021641 deionized water Inorganic materials 0.000 description 18
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 14
- 239000008367 deionised water Substances 0.000 description 14
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 14
- 230000006872 improvement Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 235000019441 ethanol Nutrition 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 229910021642 ultra pure water Inorganic materials 0.000 description 2
- 239000012498 ultrapure water Substances 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a method for improving the roughness of a SiC/SiO2 interface. The method comprises the following steps that the surface of a substrate is cleaned so that a carbon protecting film can be formed on the surface of a SiC epitaxial wafer; high-temperature ion implantation annealing at 1600 DEG C is carried out; the surface carbon film is removed; large-area HF acid cleaning is carried out on the SiC epitaxial wafer with the surface carbon film removed, and then a SiO2 gate medium layer grows; for the SiC epitaxial wafer with the SiO2 gate dielectric layer, a bottom substrate electrode grows, and electrode annealing is carried out; a gate electrode grows for the SiC epitaxial wafer with the substrate electrode annealed. According to the method, photoresist is heated at high temperature to form the carbon film, compared with other process methods, the method is simple, the practical value is high, the roughness of the SiC/SiO2 surface can be effectively reduced, the surface flatness is improved, local gate electric field intensity under high gate voltage is reduced, and the reliability of the gate dielectric layer is improved.
Description
Technical field
The present invention relates to microelectronics technology, particularly relate to one and improve SiC/SiO
2the method of interface roughness, to reduce SiC/SiO
2the roughness of interface after high annealing, reduces the local electric field strength in gate dielectric layer under high pressure, improves the reliability of gate dielectric layer, thus improves its reliability when high temperature, high-power applications.
Background technology
SiC has unique physics, chemistry and electrology characteristic, is at extremely potential semi-conducting materials in extreme applications field such as high temperature, high frequency, high-power and radioresistances.The optimum Working of SiC power MOSFET is closely related with gate medium interfacial dielectric layer characteristic and bulk properties.Well-known SiC material surface can make SiC/SiO because of experience ion implantation high temperature " stepbunching " produced that anneal
2there is great regression and have a strong impact on the inversion layer mobility of MOSFET in interface topography, is in most cases less than 10cm
2the inversion layer mobility of/Vs then because surface roughness causes, and can cause power device conducting resistance to increase.In order to improve interface roughness, a lot of method is have employed in current industry, as AlN or Graphene mask and chemico-mechanical polishing carry out high temperature tension annealing again, but while reduction surface roughness, very large impact created on device property and produce a lot of antipodal conclusion.
Summary of the invention
The object of the invention is to the deficiency for above-mentioned technique, propose one and improve SiC/SiO
2the method of interface roughness, utilizes the carbon protective film in photoresist formation high-temperature annealing process, to improve SiC/SiO
2because of the surface roughness that high annealing brings, improve the reliability of SiC MISFET device when high temperature, high-power applications.
To achieve these goals, technical scheme of the present invention is:
One improves SiC/SiO
2the method of interface roughness, the method comprises the following steps:
A1, substrate surface clean: carry out the cleaning of standardised wet methods technique to the surface of N-/N+ type SiC epitaxial wafer;
The formation of A2, surface carbon diaphragm: form carbon protective film on SiC epitaxial wafer surface;
A3, high annealing: the SiC epitaxial wafer of effects on surface formation carbon protective film carries out the high temperature tension annealing of 1600 DEG C;
The removal of A4, surperficial carbon film: the removal SiC epitaxial wafer carried out after high temperature tension annealing being carried out to surperficial carbon film;
A5, gate dielectric layer grow: the SiC epitaxial wafer eliminating surperficial carbon film is carried out large area HF acid cleaning, then carry out SiO
2the growth of gate dielectric layer;
The formation of A6, base substrate electrode: to having carried out SiO
2the SiC epitaxial wafer of gate dielectric layer carries out the growth of base substrate electrode, and column electrode of going forward side by side is annealed;
The formation of A7, gate electrode: the formation SiC epitaxial wafer having carried out underlayer electrode annealing being carried out to gate electrode.
As the improvement to technique scheme, the concrete technology step of steps A 2 is:
A21, at N-/N+SiC epitaxial wafer surface resist coating, whirl coating, to put at baking box 90 DEG C front baking 1 minute;
A22, the SiC epitaxial wafer carrying out front baking is put into high-temperature annealing furnace, keep 30 minutes at 600 DEG C, carry out carbonization;
A23, the SiC epitaxial wafer carrying out carbonization to be lowered the temperature.
As the improvement to technique scheme, the concrete technology step of steps A 3 is:
A31, SiC epitaxial wafer surface having been carried out carbonization are placed in high-temperature annealing furnace, by having one of carbon film to face down, are evacuated down to 10
-7torr, fills Ar gas, is progressively warmed up to 1600 DEG C, stops 30 minutes, carry out high temperature tension annealing at 1600 DEG C;
A32, high-temperature annealing furnace cool to normal temperature, are taken out by SiC epitaxial wafer from high-temperature annealing furnace.
As the improvement to technique scheme, the concrete technology step of steps A 4 is:
A41, by carried out high temperature tension annealing SiC epitaxial wafer put into RIE reative cell, face up with one of carbon film, shut reative cell valve, open N
2valve, to 1/4, leads to N
260 seconds, then turn off nitrogen valve;
A42, the SiC epitaxial wafer with carbon film carried out to the N of 60 seconds
2after flushing, open oil pump, the sound of oil pump becomes large and opens pump valve completely when becoming stable by the time, and 20-30 minute stablized by pump by the time;
A43, open oxygen valve, until the pressure of chamber reaches 9-12mT;
A44, open cooling system, regulate oxygen flow to 47sccm;
A45, open radio frequency network adapter, the carbon film on SiC epitaxial wafer surface is removed in timing for 90 minutes;
A46, turn off network adapter power supply, turn off O
2;
A47, system is depressured to normal pressure, turns off cooling system, fill N to inside RIE reative cell
2until reactor chamber door can be opened, take out SiC epitaxial wafer.
As the improvement to technique scheme, the concrete technology step of steps A 5 is:
A51, the SiC epitaxial wafer eliminating surperficial carbon film carried out to HF acid cleaning;
A52, by carry out HF acid cleaning SiC epitaxial wafer put into high temperature oxidation furnace, when 1180 DEG C, pass into purity oxygen, under dry oxygen condition, be oxidized 10 hours, SiC epitaxial wafer front, generate thickness be the SiO of 51nm
2oxide-film;
A53, to growth oxide-film carry out nitrogenize: to growth SiO
2oxide-film carries out the NO annealing of at 1175 DEG C 2 hours.
As the improvement to technique scheme, the concrete technology step of steps A 6 is:
A61, forming gate medium SiO
2siC epitaxial wafer put into eb evaporation chambers;
A62, on the SiC epitaxial wafer back side, evaporate thickness be that Au two kinds of metals of Ni and 240nm of 20nm are as substrate contact metal;
A63, be placed in annealing furnace alloy at 950 DEG C anneal having carried out the SiC epitaxial wafer that underlayer electrode makes 30 minutes.
As the improvement to technique scheme, the concrete technology step of steps A 7 is:
A71, carrying out underlayer electrode deposit SiC epitaxial wafer surface be coated with peel off glue, whirl coating;
A72, be painted with peel off glue SiC epitaxial wafer surface resist coating, whirl coating, utilizes grid version to make grid metallic region by lithography;
A73, to evaporate thickness on the surface at the SiC epitaxial wafer carving grid contact hole be that the Ni/Au of 20nm/240nm is as grid contacting metal;
A74, utilize stripping means formed gate figure.
Compared with prior art, tool of the present invention has the following advantages:
The present invention by high temperature adding thermosetting carbon film to photoresist, other process of comparing, simple and practical value is high, effectively can reduce SiC/SiO
2surface roughness, improves the evenness on surface, reduces the local grid electric field strength under high gate voltage, improves the reliability of gate dielectric layer.
Accompanying drawing explanation
Fig. 1 is preparation flow figure of the present invention;
Fig. 2 is that SiC epitaxial wafer does not have carbon film to protect the test result schematic diagram of lower AFM through 1650 DEG C of annealing;
Fig. 3 is that SiC epitaxial wafer has carbon film to protect the test result schematic diagram of lower AFM through 1650 DEG C of annealing;
Embodiment
Below in conjunction with specific embodiment, the specific embodiment of the present invention is described in further detail.Following examples for illustration of the present invention, but are not used for limiting the scope of the invention.
Embodiment 1
With reference to Fig. 1, the performing step of the present embodiment is as follows:
Step 1, adopts standard cleaning method RCA to carry out surface clean to 4H-SiC N-/N+ type SiC epitaxial wafer:
(1a) 4H-SiC N-/N+ type SiC epitaxial wafer is immersed in each 5min in acetone, absolute ethyl alcohol successively, then uses deionized water rinsing, to remove the grease on SiC epitaxial wafer surface;
(1b) the SiC epitaxial wafer after first time cleaning is placed in H
2sO
4: H
2o
215min is soaked, H in the solution of=1: 1 (volume ratio)
2sO
4concentration be 98%, H
2o
2concentration be 27%, then use deionized water rinsing;
(1c) the SiC epitaxial wafer after second time cleaning is placed in HF: H
2soak 1min in the solution of O=1: 10 (volume ratios) and remove natural oxidizing layer with drift, the concentration of HF acid is 40%, and with deionized water rinsing;
(1d) the SiC epitaxial wafer after third time cleaning is immersed in NH
4oH: H
2o
2: boil in the solution of DIW=3: 3: 10 (volume ratios), NH
4the concentration of OH is 28%, H
2o
2concentration be 27%, then use deionized water rinsing;
(1e) the SiC epitaxial wafer after cleaning the 4th time is placed in HF: H
2soak 30s in the solution of O=1: 10 (volume ratios), the concentration of HF acid is 40%, and with deionized water rinsing;
(1f) the SiC epitaxial wafer after cleaning the 5th time is HCl: H
2o
2: boil in the solution of DIW=3: 3: 10 (volume ratios), the concentration of HCl is 10%, H
2o
2concentration be 27%, with deionized water rinsing;
(1g) the SiC epitaxial wafer after cleaning the 6th time is HF: H
2soak 30s in the solution of O=1: 10 (volume ratios), and with deionized water rinsing, the concentration of HF acid is 40%, finally uses N
2rifle dries up;
Step 2, makes high temperature tension temper carbon diaphragm in N-/N+SiC epitaxial wafer front:
(2a) surperficial SiO is being removed
2the SiC epitaxial wafer surface resist coating on barrier layer;
(2b) whirl coating, to put at baking box 90 DEG C front baking 1 minute;
(2c) put into high-temperature annealing furnace by carrying out the SiC epitaxial wafer that front baking crosses, carbon faces up;
(2d) vacuumize 2 hours, pressure reaches 4 ~ 5E-7Torr;
(2e) fill Ar gas, arrange and export pressure for 12psi;
(2f) fan is opened;
(2g) first power is adjusted to 10%, be then transferred to the power of 30% according to 5%/2min speed, then fine tuning power is adjusted to temperature according to the power of 2%/2min and rises to 600 DEG C, keeps 30 minutes at 600 DEG C;
(2h) intensification power adjusting knob is turned off;
(2i) the SiC epitaxial wafer with carbon film is taken out;
Step 3, high annealing;
(3a) the SiC epitaxial wafer with carbon protective film is put into high-temperature annealing furnace, face down with one of carbon face;
(3b) vacuumize, pressure reaches 4 ~ 5E-7Torr;
(3c) fill Ar gas, arrange and export pressure for 12psi;
(3d) fan is opened;
(3e) first power is adjusted to 60%, is then adjusted to temperature according to 1%/10s speed and rises to 1600 DEG C, keep 30 minutes at 1600 DEG C;
(3f) intensification power adjusting knob is turned off;
(3i) the SiC epitaxial wafer after high temperature tension annealing with carbon film is taken out;
Step 4, remove the carbon protective film in N-/N+SiC epitaxial wafer front:
(4a) N is filled in RIE cavity
2, open RIE reactor chamber door;
(4b) SiC epitaxial wafer is placed on center, faces up with one of carbon film, compress with tweezers, shut reactor chamber door and then tighten valve;
(4c) logical O is started
2, flow velocity 47sccm;
(4d) open radio frequency network adapter, regulating power is set to 18 ± 3W;
(4e) carbon film that SiC epitaxial wafer surface is removed in timing for 90 minutes is started;
(4f) turn off radio frequency network adapter, turn off O
2;
(4g) N is filled
2until reaction chamber door can be opened automatically, take out SiC epitaxial wafer;
(4h) the SiC epitaxial wafer getting rid of surperficial carbon film is carried out RCA cleaning;
Step 5, large area deposition SiO
2gate dielectric layer:
(5a) the SiC epitaxial wafer having carried out RCA cleaning being put into high temperature oxidation furnace, is the N of 750 DEG C in temperature
2push in oxidation furnace flat-temperature zone in environment;
(5b) by 3 DEG C/min speed, flat-temperature zone is heated up;
(5c) pass into oxygen when temperature rises to 1150 DEG C, oxygen flow is 0.5l/min, and under pure dry oxygen condition, be oxidized 10 hours, epitaxial wafer surface, generating thickness in epitaxial wafer front is the SiO of 51nm
2oxide-film.
(5d) O is turned off
2, open Ar, logical Ar gas 15 minutes;
(5e) according to 3 DEG C/min speed, flat-temperature zone is heated up;
(5f) when temperature is raised to 1175 DEG C, NO is opened, flow 577sccm, time 2 h;
(5h) turn off NO gas, furnace temperature is dropped to 900 DEG C;
(5i) turn off Ar gas, take out SiC epitaxial wafer;
Step 6, the formation of substrate leakage pole:
(6a) gate medium SiO will be grown
2siC epitaxial wafer put into eb evaporation chambers;
(6b) evaporate three kinds of metal A l/Ni/Au in SiC epitaxial wafer back side large area and do substrate Ohm contact electrode, its thickness is respectively 150nm, 50nm and 70nm, thus forms substrate ohmic contact;
(6e) finally the SiC epitaxial wafer finishing source electrode is placed in annealing furnace at 950 DEG C, to carry out alloy anneal 30 minutes;
The formation of step 7 gate electrode:
(7a) be coated with stripping glue, photoresist in the SiC epitaxial wafer front of having carried out underlayer electrode annealing, whirl coating, then carries out front baking to the SiC epitaxial wafer getting rid of glue at 80 DEG C; The front baking time is 10 ~ 15min;
(7b) gate electrode photolithography plate is utilized to carve gate figure;
(7c) develop in positivity developer solution, solution temperature is 20 DEG C, and developing time is 85s;
(7d) the SiC epitaxial wafer after development is carried out post bake at ultra-pure water, coolant-temperature gage is 20 DEG C, and the post bake time is 85s;
(7e) in equipment for burning-off photoresist by plasma, remove exposed photoresist, then utilize deionized water to clean;
(7f) then will the SiC epitaxial wafer of photoresist be gone 5 hours to soak in acetone and utilize acetone ultrasonic 1 minute, and then acetone, alcohol washes respectively once, remove the stripping glue in gate electrode region; Expose effective contact area;
(7g) to going the SiC epitaxial wafer of photoresist and stripping glue to put in the middle of eb evaporation chambers, large area evaporation Ti/Au, thickness is 50nm/200nm;
(7m) last gate electrode contact is formed by stripping means.
Embodiment 2
Compared with embodiment 1, be on the basis of embodiment 1 at the present embodiment, removing carbon protective film and the large area deposition SiO in N-/N+SiC epitaxial wafer front
2add the growth operation of one sacrificial oxide layer in gate dielectric layer operation, can to anneal the interface damage brought by more effective reduction high temperature tension, effectively improve interface evenness.
The performing step of this example is as follows:
Steps A, adopts standard cleaning method RCA to carry out surface clean to 4H-SiC N-/N+ type SiC epitaxial wafer:
(Aa) 44H-SiC N-/N+ type SiC epitaxial wafer is immersed in acetone successively, each 5min in absolute ethyl alcohol, then uses deionized water rinsing, to remove the grease on SiC epitaxial wafer surface;
(Ab) the SiC epitaxial wafer after first time cleaning is placed in H
2sO
4: H
2o
215min is soaked, H in the solution of=1: 1 (volume ratio)
2sO
4concentration be 98%, H
2o
2concentration be 27%, then use deionized water rinsing;
(Ac) the SiC epitaxial wafer after second time cleaning is placed in HF: H
2soak 1min in the solution of O=1: 10 (volume ratios) and remove natural oxidizing layer with drift, the concentration of HF acid is 40%, and with deionized water rinsing;
(Ad) the SiC epitaxial wafer after third time cleaning is immersed in NH
4oH: H
2o
2: boil in the solution of DIW=3: 3: 10 (volume ratios), NH
4the concentration of OH is 28%, H
2o
2concentration be 27%, then use deionized water rinsing;
(Ae) the SiC epitaxial wafer after cleaning the 4th time is placed in HF: H
2soak 30s in the solution of O=1: 10 (volume ratios), the concentration of HF acid is 40%, and with deionized water rinsing;
(Af) the SiC epitaxial wafer after cleaning the 5th time is HCl: H
2o
2: boil in the solution of DIW=3: 3: 10 (volume ratios), the concentration of HCl is 10%, H
2o
2concentration be 27%, with deionized water rinsing;
(Ag) the SiC epitaxial wafer after cleaning the 6th time is HF: H
2soak 30s in the solution of O=1: 10 (volume ratios), and with deionized water rinsing, the concentration of HF acid is 40%, finally uses N
2rifle dries up;
Step B, makes high annealing carbon protective film in N-/N+SiC epitaxial wafer front:
(Ba) surperficial SiO is being removed
2the SiC epitaxial wafer surface resist coating on barrier layer;
(Bb) whirl coating, to put at baking box 90 DEG C front baking 1 minute;
(Bc) put into high-temperature annealing furnace by carrying out the SiC epitaxial wafer that front baking crosses, carbon faces up;
(Bd) vacuumize 2 hours, pressure reaches 4 ~ 5E-7Torr;
(Be) fill Ar gas, arrange and export pressure for 12psi;
(Bf) fan is opened;
(Bg) first power is adjusted to 10%, be then transferred to the power of 30% according to 5%/2min speed, then fine tuning power is adjusted to temperature according to the power of 2%/2min and rises to 600 DEG C, keeps 30 minutes at 600 DEG C;
(Bh) intensification power adjusting knob is turned off;
(Bi) the SiC epitaxial wafer with carbon film is taken out;
Step C, high temperature tension is annealed;
(Ca) the SiC epitaxial wafer with carbon protective film is put into high-temperature annealing furnace, face down with one of carbon face;
(Cb) vacuumize, pressure reaches 4 ~ 5E-7Torr;
(Cc) fill Ar gas, arrange and export pressure for 12psi;
(Cd) fan is opened;
(Ce) first power is adjusted to 60%, is then adjusted to temperature according to 1%/10s speed and rises to 1600 DEG C, keep 30 minutes at 1600 DEG C;
(Cf) intensification power adjusting knob is turned off;
(Ci) the SiC epitaxial wafer after high temperature tension annealing with carbon film is taken out;
Step D, removes the carbon protective film in N-/N+SiC epitaxial wafer front:
(Da) N is filled in RIE cavity
2, open RIE reactor chamber door;
(Db) will center be placed on, face up with one of carbon film, and compress with tweezers, shut reactor chamber door and then tighten valve;
(Dc) logical O is started
2, flow velocity 47sccm;
(Dd) open radio frequency network adapter, regulating power is set to 18 ± 3W;
(De) carbon film that SiC epitaxial wafer surface is removed in timing for 90 minutes is started;
(Df) turn off radio frequency network adapter, turn off O
2;
(Dg) N is filled
2until reaction chamber door can be opened automatically, take out;
(Dh) the SiC epitaxial wafer getting rid of surperficial carbon film is carried out RCA cleaning;
Step e, the growth of sacrificial oxide layer:
(Ea) the SiC epitaxial wafer carrying out high annealing is put into high temperature oxidation furnace, 1200 DEG C time, be oxidized SiC epitaxial wafer surface 30min under pure dry oxygen condition, generating thickness in SiC epitaxial wafer front is the SiO of 20nm
2oxide-film;
(Eb) SiO will be grown
2the SiC epitaxial wafer of oxide-film is put in the middle of HF acid, the oxide layer on surface is washed;
Step F, large area deposition SiO
2gate dielectric layer:
(Fa) SiC having carried out HF acid cleaning being put into high temperature oxidation furnace, is the N of 750 DEG C in temperature
2push in oxidation furnace flat-temperature zone in environment;
(Fb) by 3 DEG C/min speed, flat-temperature zone is heated up;
(Fc) pass into oxygen when temperature rises to 1150 DEG C, oxygen flow is 0.5l/min, and under pure dry oxygen condition, be oxidized 10 hours, epitaxial wafer surface, generating thickness in SiC epitaxial wafer front is the SiO of 51nm
2oxide-film.
(Fd) O is turned off
2, open Ar, logical Ar gas 15 minutes;
(Fe) according to 3 DEG C/min speed, flat-temperature zone is heated up;
(Ff) when temperature is raised to 1175 DEG C, NO is opened, flow 577sccm, time 2 h;
(Fh) turn off NO gas, furnace temperature is dropped to 900 DEG C;
(Fi) turn off Ar gas, take out;
Step G, the formation of underlayer electrode:
(Ga) the SiC epitaxial wafer that grown gate medium is put into eb evaporation chambers;
(Gb) large area is evaporated three kinds of metal A l/Ni/Au and is done substrate Ohm contact electrode overleaf, and its thickness is respectively 150nm, 50nm and 70nm, thus forms substrate ohmic contact;
(Gc) finally the SiC epitaxial wafer finishing source electrode is placed in annealing furnace at 950 DEG C, to carry out alloy anneal 30 minutes;
The formation of step H gate electrode:
(Ha) be coated with stripping glue, photoresist in the SiC epitaxial wafer front of having carried out source-drain electrode annealing, whirl coating, then carries out front baking to the SiC epitaxial wafer getting rid of glue at 80 DEG C; The front baking time is 10 ~ 15min;
(Hb) gate electrode photolithography plate is utilized to carve gate figure;
(Hc) develop in positivity developer solution, solution temperature is 20 DEG C, and developing time is 85s;
(Hd) the SiC epitaxial wafer after development is carried out post bake at ultra-pure water, coolant-temperature gage is 20 DEG C, and the post bake time is 85s;
(He) in equipment for burning-off photoresist by plasma, remove exposed photoresist, then utilize deionized water to clean;
(Hf) then will the SiC epitaxial wafer of photoresist be gone 5 hours to soak in acetone and utilize acetone ultrasonic 1 minute, and then acetone, alcohol washes respectively once, remove the stripping glue in gate electrode region; Expose effective contact area;
(Hg) to going the SiC epitaxial wafer of photoresist and stripping glue to put in the middle of eb evaporation chambers, large area evaporation Ti/Au, thickness is 50nm/200nm;
(Hm) last gate electrode contact is formed by stripping means.
Fig. 2 is that SiC epitaxial wafer does not have carbon film to protect the test result schematic diagram (RMS=6.1nm) of lower AFM through 1650 DEG C of annealing; Fig. 3 is that SiC epitaxial wafer has carbon film to protect the test result schematic diagram (RMS=2.6nm) of lower AFM through 1650 DEG C of annealing; It can thus be appreciated that compared with prior art, tool of the present invention has the following advantages:
The present invention by high temperature adding thermosetting carbon film to photoresist, other process of comparing, simple and practical value is high, effectively can reduce SiC/SiO
2surface roughness, improves the evenness on surface, reduces the local grid electric field strength under high gate voltage, improves the reliability of gate dielectric layer.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. one kind is improved SiC/SiO
2the method of interface roughness, is characterized in that, the method comprises the following steps:
A1, substrate surface clean: carry out the cleaning of standardised wet methods technique to the surface of N-/N+ type SiC epitaxial wafer;
The formation of A2, surface carbon diaphragm: form carbon protective film on SiC epitaxial wafer surface;
A3, high annealing: the SiC epitaxial wafer of effects on surface formation carbon protective film carries out the high temperature tension annealing of 1600 DEG C;
The removal of A4, surperficial carbon film: the removal SiC epitaxial wafer carried out after high temperature tension annealing being carried out to surperficial carbon film;
A5, gate dielectric layer grow: the SiC epitaxial wafer eliminating surperficial carbon film is carried out large area HF acid cleaning, then carry out SiO
2the growth of gate dielectric layer;
The formation of A6, base substrate electrode: to having carried out SiO
2the SiC epitaxial wafer of gate dielectric layer carries out the growth of base substrate electrode, and column electrode of going forward side by side is annealed;
The formation of A7, gate electrode: the formation SiC epitaxial wafer having carried out underlayer electrode annealing being carried out to gate electrode.
2. improve SiC/SiO as claimed in claim 1
2the method of interface roughness, is characterized in that, the concrete technology step of steps A 2 is:
A21, at N-/N+SiC epitaxial wafer surface resist coating, whirl coating, to put at baking box 90 DEG C front baking 1 minute;
A22, the SiC epitaxial wafer carrying out front baking is put into high-temperature annealing furnace, keep 30 minutes at 600 DEG C, carry out carbonization;
A23, the SiC epitaxial wafer carrying out carbonization to be lowered the temperature.
3. improve SiC/SiO as claimed in claim 1
2the method of interface roughness, is characterized in that, the concrete technology step of steps A 3 is:
A31, SiC epitaxial wafer surface having been carried out carbonization are placed in high-temperature annealing furnace, by having one of carbon film to face down, are evacuated down to 10
-7torr, fills Ar gas, is progressively warmed up to 1600 DEG C, stops 30 minutes, carry out high temperature tension annealing at 1600 DEG C;
A32, high-temperature annealing furnace cool to normal temperature, are taken out by SiC epitaxial wafer from high-temperature annealing furnace.
4. improve SiC/SiO as claimed in claim 1
2the method of interface roughness, is characterized in that, the concrete technology step of steps A 4 is:
A41, by carried out high temperature tension annealing SiC epitaxial wafer put into RIE reative cell, face up with one of carbon film, shut reative cell valve, open N
2valve, to 1/4, leads to N
260 seconds, then turn off nitrogen valve;
A42, the SiC epitaxial wafer with carbon film carried out to the N of 60 seconds
2after flushing, open oil pump, the sound of oil pump becomes large and opens pump valve completely when becoming stable by the time, and 20-30 minute stablized by pump by the time;
A43, open oxygen valve, until the pressure of chamber reaches 9E-12mT;
A44, open cooling system, regulate oxygen flow to 47sccm;
A45, open radio frequency network adapter, the carbon film on SiC epitaxial wafer surface is removed in timing for 90 minutes;
A46, turn off network adapter power supply, turn off O
2;
A47, system is depressured to normal pressure, turns off cooling system, fill N to inside RIE reative cell
2until reactor chamber door can be opened, take out SiC epitaxial wafer.
5. improve SiC/SiO as claimed in claim 1
2the method of interface roughness, is characterized in that, the concrete technology step of steps A 5 is:
A51, the SiC epitaxial wafer eliminating surperficial carbon film carried out to HF acid cleaning;
A52, by carry out HF acid cleaning SiC epitaxial wafer put into high temperature oxidation furnace, when 1180 DEG C, pass into purity oxygen, under dry oxygen condition, be oxidized 10 hours, SiC epitaxial wafer front, generate thickness be the SiO of 51nm
2oxide-film;
A53, to growth oxide-film carry out nitrogenize: to growth SiO
2oxide-film carries out the NO annealing of at 1175 DEG C 2 hours.
6. improve SiC/SiO as claimed in claim 1
2the method of interface roughness, is characterized in that,
The concrete technology step of steps A 6 is:
A61, forming gate medium SiO
2siC epitaxial wafer put into eb evaporation chambers;
A62, on the SiC epitaxial wafer back side, evaporate thickness be that Au two kinds of metals of Ni and 240nm of 20nm are as substrate contact metal;
A63, be placed in annealing furnace alloy at 950 DEG C anneal having carried out the SiC epitaxial wafer that underlayer electrode makes 30 minutes.
7. improve SiC/SiO as claimed in claim 1
2the method of interface roughness, is characterized in that, the concrete technology step of steps A 7 is:
A71, carrying out underlayer electrode deposit SiC epitaxial wafer surface be coated with peel off glue, whirl coating;
A72, be painted with peel off glue SiC epitaxial wafer surface resist coating, whirl coating, utilizes grid version to make grid metallic region by lithography;
A73, to evaporate thickness on the surface at the SiC epitaxial wafer carving grid contact hole be that the Ni/Au of 20nm/240nm is as grid contacting metal;
A74, utilize stripping means formed gate figure.
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