CN104882367B - A method of improving SiC MOSFET element channel mobility - Google Patents
A method of improving SiC MOSFET element channel mobility Download PDFInfo
- Publication number
- CN104882367B CN104882367B CN201510221211.2A CN201510221211A CN104882367B CN 104882367 B CN104882367 B CN 104882367B CN 201510221211 A CN201510221211 A CN 201510221211A CN 104882367 B CN104882367 B CN 104882367B
- Authority
- CN
- China
- Prior art keywords
- mosfet element
- sic mosfet
- treated
- sic
- epitaxial wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 40
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 28
- 230000006872 improvement Effects 0.000 claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 claims abstract description 8
- 230000008569 process Effects 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 230000001681 protective effect Effects 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 3
- 239000011248 coating agent Substances 0.000 claims description 78
- 238000000576 coating method Methods 0.000 claims description 78
- 238000012545 processing Methods 0.000 claims description 46
- 239000000243 solution Substances 0.000 claims description 34
- 239000003292 glue Substances 0.000 claims description 28
- 238000000137 annealing Methods 0.000 claims description 25
- 238000007254 oxidation reaction Methods 0.000 claims description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 22
- 229910052681 coesite Inorganic materials 0.000 claims description 19
- 229910052906 cristobalite Inorganic materials 0.000 claims description 19
- 239000000377 silicon dioxide Substances 0.000 claims description 19
- 229910052682 stishovite Inorganic materials 0.000 claims description 19
- 229910052905 tridymite Inorganic materials 0.000 claims description 19
- 238000001704 evaporation Methods 0.000 claims description 18
- 230000008020 evaporation Effects 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 16
- 239000001301 oxygen Substances 0.000 claims description 16
- 229910052760 oxygen Inorganic materials 0.000 claims description 16
- 230000003647 oxidation Effects 0.000 claims description 15
- 238000002513 implantation Methods 0.000 claims description 14
- 239000002253 acid Substances 0.000 claims description 13
- 239000007789 gas Substances 0.000 claims description 12
- 238000004140 cleaning Methods 0.000 claims description 10
- 238000001020 plasma etching Methods 0.000 claims description 10
- 229910001868 water Inorganic materials 0.000 claims description 8
- 239000011259 mixed solution Substances 0.000 claims description 6
- 238000001459 lithography Methods 0.000 claims description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 2
- 238000003763 carbonization Methods 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 238000001816 cooling Methods 0.000 claims description 2
- 230000002708 enhancing effect Effects 0.000 claims description 2
- 238000010792 warming Methods 0.000 claims description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims 4
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 36
- 229910021641 deionized water Inorganic materials 0.000 description 18
- 239000008367 deionised water Substances 0.000 description 14
- 150000002500 ions Chemical class 0.000 description 13
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 8
- 229910021642 ultra pure water Inorganic materials 0.000 description 8
- 239000012498 ultrapure water Substances 0.000 description 8
- 238000011161 development Methods 0.000 description 7
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 125000001967 indiganyl group Chemical group [H][In]([H])[*] 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 238000002604 ultrasonography Methods 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 235000011114 ammonium hydroxide Nutrition 0.000 description 2
- 229960000935 dehydrated alcohol Drugs 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 239000004519 grease Substances 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 150000002576 ketones Chemical class 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052708 sodium Inorganic materials 0.000 description 2
- 239000011734 sodium Substances 0.000 description 2
- 235000011149 sulphuric acid Nutrition 0.000 description 2
- 229910007991 Si-N Inorganic materials 0.000 description 1
- 229910006294 Si—N Inorganic materials 0.000 description 1
- FKNQFGJONOIPTF-UHFFFAOYSA-N Sodium cation Chemical compound [Na+] FKNQFGJONOIPTF-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000003471 anti-radiation Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A method of improving SiC MOSFET element channel mobility, comprising the following steps: first clean SiC MOSFET element substrate surface；Ion implanting is carried out later；Rear surface formed carbon protective film；It is removed surface carbon film process later；SiO is carried out later2The growth of gate dielectric layer；Surface is carried out later forms source and drain Ohmic contact；The formation of gate figure is carried out later；Electrode fabrication is carried out later, that is, completes the improvement of SiC MOSFET element channel mobility.The method of improvement SiC MOSFET element channel mobility improves SiC MOSFET element interfacial characteristics and improves MIS device channel mobility, can be used for the production of extensive SiC MIS device and circuit.
Description
[technical field]
The invention belongs to microelectronics technologies, are related to the production of semiconductor devices, and in particular to a kind of improvement SiC
The method of MOSFET element channel mobility, to improve the channel mobility of MOSFET element and reduce SiC/SiO2Interfacial state is close
Degree, to improve its reliability in high temperature, high-power applications.
[background technique]
SiC has unique physics, chemistry and electrology characteristic, is in high temperature, high frequency, high-power and anti-radiation etc. extremely answer
With the semiconductor material of field with development potential.The optimum Working and gate medium interfacial dielectric layer of SiC power MOSFET
Characteristic and bulk properties are closely related.The problem of SiC MOS device production at present is primarily present is moved how to improve the channel of device
Shifting rate, and used a variety of modes both at home and abroad for this purpose, such as traditional Ar, H2Annealing, nitrogen oxides annealing (NO, N2O),
N ion implanting before aoxidizing, and these are all close to reduce interfacial state by importing the principle of more H and N element in interface
Degree, in SiC/SiO2Interface, which introduces nitrogen, can form stronger Si-N key and O-N key, so that SiC/SiO2Interface and its attached
Close oxide layer has obtained a degree of hardening, so as to improve the breakdown characteristics and reliability of oxide layer, nitrogenizes SiO2Film is most
It is early to be used in 1997, is annealed using NO to reduce interface state density, but no matter use NO or N2O nitridation,
The nitrogen that MOS device interface introduces is seldom, and the channel mobility of SiC MOSFET element also only has 30-40cm2V-1s-1,
F.Allerstan et al. is found by experiment that SiC/SiO2It interface can be by the face Si inversion channel mobility after being passivated by sodium
It is increased to 150cm2V-1s-1, but sodium ion can move under the action of bias leads to the unstable of threshold voltage, therefore utilizes
Sodium element passivation is not good method yet.
[summary of the invention]
In view of the above-mentioned problems, the present invention provides a kind of method for improving SiC MOSFET element channel mobility, in channel
In by ion injection method inject As element, SiC MOSFET element channel mobility can be effectively improved, and in order to keep away
Exempt from " step bunching " brought by ion implantation high temperature annealing and protected using carbon film, there is no therefore damage device
The characteristic of part, while interface state density is effectively reduced using NO in-situ annealing, improve SiC MISFET device in high temperature, big function
Reliability when rate is applied.
The present invention is achieved by the following technical solutions, and providing a kind of improves SiC MOSFET element channel mobility
Method, comprising the following steps:
The cleaning of S1:SiC MOSFET element substrate surface；
S2: the SiC MOSFET element after step S1 cleaning is subjected to ion implanting；
S3: carbon protective film is formed in the surface of step S2 treated SiC MOSFET element；
S4: by step S3, treated that SiC MOSFET element is removed surface carbon film process；
S5: step S4 treated SiC MOSFET element is subjected to SiO2The growth of gate dielectric layer；
S6: source and drain Ohmic contact is formed in treated the SiC MOSFET element surface step S5；
S7: step S5 treated SiC MOSFET element is carried out to the formation of gate figure；
S8: carrying out electrode fabrication for step S6 treated SiC MOSFET element, i.e. completion SiC MOSFET element ditch
The improvement of road mobility.
Particularly, the step S2 specifically includes the following steps:
S21 high temperature N~+ implantation: being put into high temperature tension machine for the SiC MOSFET element after step S1 cleaning,
Carrying out high temperature N~+ implantation at a temperature of 400 DEG C in four times, the N~+ implantation dosage and energy be respectively as follows: 4.14 ×
1011cm-2/ 30K, 4.37 × 1011cm-2/ 55K, 4.61 × 1011cm-2/ 80K, 12.1 × 1011cm-2/125K；
The mixed solution of HF and water that step S21 treated SiC MOSFET element is put into volume ratio is 1: 10 by S22
Rinsing, removes the SiO on surface2Layer, the concentration of the HF are 40%；
S23 source and drain high temperature tension, is specifically implemented according to the following steps:
S231 carries out step S22 treated SiC MOSFET element using plasma enhancing chemical vapour deposition technique
Surface SiO2The deposit of layer, the SiO2Layer with a thickness of 60~70nm；
S232 deposited SiO2The SiC MOSFET element surface resist coating of layer, and make source, drain region by lithography；
The SiO that S233 protects SiC MOSFET element without photoresist in HF acid solution2Layer washes, and exposes source
Leak high temperature tension region；
Treated that SiC MOSFET element is put into high temperature tension machine by step S233 by S234, in 400 DEG C of temperature
Under carry out high temperature N~+ implantation in four times, carry out high temperature N~+ implantation, the N~+ implantation agent in four times at 400 DEG C
Amount and energy are respectively as follows: 5 × 1014cm-2/ 30K, 6.0 × 1014cm-2/ 60K, 8 × 1014cm-2/ 120K, 1.5 × 1015cm-2/
190K；
Treated that SiC MOSFET element is cleaned in HF solution by step S234 by S235, removes SiC MOSFET
The SiO of device surface2Barrier layer.
Particularly, the step S3 specifically includes the following steps:
S31 is to step S2 treated SiC MOSFET element surface resist coating, and after carrying out whirl coating processing with whirl coating,
Front baking 1 minute at 90 DEG C is put into oven；
Treated that SiC MOSFET element is put into high-temperature annealing furnace by step S31 by S32, and 30 points are kept at 600 DEG C
Clock carries out cooling processing after carrying out carbonization treatment.
Particularly, the step S4 specifically includes the following steps:
Treated that SiC MOSFET element is put in high-temperature annealing furnace by step S3 by S41, down by have carbon film one,
It is evacuated down to 10-7Torr, applying argon gas are gradually warming up to 1600 DEG C, stop 30 minutes at 1600 DEG C, carry out high temperature tension and move back
Fire takes out after being down to room temperature；
S42 is removed the carbon film on treated the SiC MOSFET element surface step S41 using reactive ion etching method.
Particularly, the step S5 specifically includes the following steps:
By treated in step S4, SiC MOSFET element is put into high temperature oxidation furnace S51, is led under the conditions of 1180 DEG C
Enter oxygen, SiC MOSFET element front is aoxidized under the conditions of dry oxygen 10 hours, generates the SiO with a thickness of 51nm2Oxidation film；
The SiO that S52 generates step S51 treated SiC MOSFET element2Oxidation film carries out 2 under the conditions of 1175 DEG C
The NO annealing of hour.
Particularly, the step S5 further includes step B5: step S4 treated SiC MOSFET element sacrifice is aoxidized
The growth process of layer.
Particularly, the step B5 specifically includes the following steps:
Treated that SiC MOSFET element is put into high temperature oxidation furnace by step S4 by B51, in 1200 DEG C of pure dry oxygen item
Oxidized surface 30min under part makes Surface Creation with a thickness of the SiO of 20nm2Oxidation film；
B52 washes the oxide layer on surface in step SB1 treated SiC MOSFET element is put into HF acid.
Particularly, the step S6 specifically includes the following steps:
S61 applies removing glue to treated the SiC MOSFET element surface step S5, and carries out whirl coating processing with whirl coating；
S62 carries out whirl coating processing with whirl coating in step S61 treated SiC MOSFET element surface resist coating
Afterwards, source and drain ohmic contact hole is made by lithography；
S63 is respectively 150nm/50nm/200nm to evaporation thickness on SiC MOSFET element surface after step S62 processing
Al/Ni/Au as metal ohmic contact；
Treated that SiC MOSFET element is removed to step S63 by S64, forms source and drain Ohmic contact pattern；
Treated that SiC MOSFET element is placed in annealing furnace by step S64 by S65, and alloy is annealed 30 points at 950 DEG C
Clock.
Particularly, the step S7 specifically includes the following steps:
S71 applies removing glue to treated the SiC MOSFET element surface step S5, and carries out whirl coating processing with whirl coating；
S72 carries out whirl coating processing with whirl coating in step S71 treated SiC MOSFET element surface resist coating
Afterwards, grid metal region is made by lithography using grid version；
S73 is respectively the Ni/Au of 20nm/240nm to evaporation thickness on SiC MOSFET element surface after step S72 processing
Metal is contacted as grid；
S74 forms gate figure using stripping means.
Particularly, the step S8 specifically includes the following steps:
S81 applies removing glue in treated the SiC MOSFET element surface step S8, and carries out whirl coating processing with whirl coating；
S82 carries out whirl coating processing with whirl coating in step S91 treated SiC MOSFET element surface resist coating
Afterwards, interconnection area is carved using interconnection electrode reticle；
S83 is respectively the Ti/Au of 50nm/200nm to evaporation thickness on SiC MOSFET element surface after step S92 processing
Metal is contacted as interconnection；
S84 forms grid, source, leakage interconnection graph using stripping means, that is, completes changing for iC MOSFET element channel mobility
It is kind.
Compared to the prior art, the present invention provides a kind of method for improving SiC MOSFET element channel mobility, passes through
As element is injected by ion injection method in channels, minority carrier density of the device in strong inversion work can be increased, thus
SiC MOSFET element channel mobility is effectively improved, and in order to avoid " step brought by ion implantation high temperature annealing
Bunching " and protected using carbon film, there is no the therefore characteristics of damage device, while effective using NO in-situ annealing
Reduce interface state density, improves reliability of the SiC MISFET device in high temperature, high-power applications.
[Detailed description of the invention]
Fig. 1 is the effect picture after a kind of method for improving SiC MOSFET element channel mobility of the present invention improves；
Fig. 2 is the mobility change after a kind of method for improving SiC MOSFET element channel mobility of the present invention improves
Figure.
[specific embodiment]
In order to make the objectives, technical solutions, and advantages of the present invention clearer, 4H-SiCP type epitaxial wafer is used below
The present invention is described in more detail in conjunction with the embodiments for sample.
Embodiment 1
A method of improving SiC MOSFET element channel mobility, specifically implement in accordance with the following methods:
S1 carries out surface clean to 4H-SiC p-type epitaxial wafer sample using RCA standard cleaning method, specifically according to following step
Suddenly it is cleaned:
4H-SiC p-type epitaxial wafer sample is successively immersed in acetone by S11, each 5min in dehydrated alcohol, then is rushed with deionized water
It washes, to remove the grease of epitaxial wafer sample surfaces；
4H-SiC p-type epitaxial wafer sample after S12 cleans S11 is placed in H22O4∶H2O2The solution of=1: 1 (volume ratio)
The concentration that the concentration of middle immersion 15min, H2SO4 are 98%, H2O2 is 27%, is then rinsed with deionized water；
4H-SiC p-type epitaxial wafer sample after S13 cleans S12 is placed in HF: H2In the solution of O=1: 10 (volume ratios)
1min is impregnated to float natural oxidizing layer, and the concentration of HF acid is 40%, and is rinsed with deionized water；
4H-SiC p-type epitaxial wafer sample after S14 cleans S13 is immersed in NH4OH∶H2O2: DIW=3: 3: 10 (volume ratios)
Solution in boil, the concentration that the concentration of NH4OH is 28%, H2O2 is 27%, then is rinsed with deionized water；
4H-SiC p-type epitaxial wafer sample after S15 cleans S14 is placed in HF: H2In the solution of O=1: 10 (volume ratios)
30s is impregnated, the concentration of HF acid is 40%, and is rinsed with deionized water；
S16 S15 is cleaned after 4H-SiC p-type epitaxial wafer sample HCl: H2O2: DIW=3: 3: 10 (volume ratios) it is molten
It is boiled in liquid, the concentration of HCl is 10%, H2O2Concentration be 27%, rinsed with deionized water；
4H-SiC p-type epitaxial wafer sample after S17 cleans S16 soaks in the solution of HF: H2O=1: 10 (volume ratios)
30s is steeped, and is rinsed with deionized water, the concentration of HF acid is 40%, finally uses N2Rifle drying.
4H-SiC p-type epitaxial wafer sample after S2 cleans step S1 carries out ion implanting, specifically real according to the following steps
It applies:
The 4H-SiC p-type epitaxial wafer sample that step S17 was cleaned is put into high temperature tension room and carries out channel As by S21
Temperature is adjusted to 400 DEG C by ion implanting, and the N~+ implantation dosage and energy are respectively as follows: 4.14 × 1011cm-2/ 30K,
4.37×1011cm-2/ 55K, 4.61 × 1011cm-2/ 80K, 12.1 × 1011cm-2/125K；
S22 by step S21 treated 4H-SiC p-type epitaxial wafer sample is put into volume ratio be 1: 10 HF and water it is mixed
Solution rinsing is closed, the SiO on surface is removed2Layer, the concentration of the HF are 40%；
S23 source and drain high temperature tension, is specifically implemented according to the following steps:
The epitaxial wafer of step S22 treated 4H-SiC p-type epitaxial wafer sample is put into plasma enhanced chemical by S231
Vapour deposition process (Plasma Enhanced Chemical Vapor Deposition, hereinafter referred to as PECVD) reaction chamber,
Make its surface deposition with a thickness of the SiO of 60nm under conditions of 300 DEG C2Layer；
S232 deposited SiO2 layers of 4H-SiC p-type epitaxial wafer sample surface resist coating；Whirl coating is carried out with whirl coating later
After processing, front baking is carried out at 80 DEG C, the front baking time is 10~15min, after injecting reticle to front baking using source and drain later
After epitaxial wafer sample exposure, develop in positivity developer solution, solution temperature is 20 DEG C, developing time 85s；It will be developed later
Epitaxial wafer afterwards carries out post bake in ultrapure water, and coolant-temperature gage is 20 DEG C, and the post bake time is 85s；Later in equipment for burning-off photoresist by plasma
Remove exposed photoresist, exposes effective source and drain areas；
The SiO that S233 protects 4H-SiC p-type epitaxial wafer sample without photoresist in HF acid solution2Layer washes,
Expose source and drain high temperature tension region；
Treated that 4H-SiC p-type epitaxial wafer sample is put into high temperature tension machine the source that carries out by step S233 by S234
N+ ion implanting is leaked, temperature is adjusted to 400 DEG C, implantation dosage and energy following 5 × 1014cm-2/ 30K, 6.0 × 1014cm-2/
60K, 8 × 1014cm-2/ 120K, 1.5 × 1015cm-2/ 190K, implantation concentration are 1 × 1020cm-3Left and right, depth are 0.3 μm of left side
It is right；
S235 to step S234 treated 4H-SiC p-type epitaxial wafer sample volume ratio be 1: 10 HF and water it is mixed
Solution rinsing is closed, the SiO2 layer on surface is removed, the concentration of the HF is 40%.
S3: forming carbon protective film in the surface of step S2 treated 4H-SiC p-type epitaxial wafer sample, specifically according to
Lower step is implemented:
S31 gets rid of step S235 treated 4H-SiC p-type epitaxial wafer sample surfaces resist coating with whirl coating
After glue processing, front baking 1 minute at 90 DEG C is put into oven；
Treated that 4H-SiC p-type epitaxial wafer sample is put into high-temperature annealing furnace by step S31 by S32, and carbon is face-up；It
After vacuumize 2 hours, after so that high-temperature annealing furnace pressure is reached 4~5E-7Torr, fill Ar gas, setting output pressure is 12psi；Later
Fan is opened, power is adjusted to 10% first, 30% power is then transferred to according to 5%/2min speed, then carefully
It adjusts power to be adjusted to temperature according to the power of 2%/2min and rises to 600 DEG C, after being kept for 30 minutes at 600 DEG C, turn off liter
Warm power adjusting knob takes out the 4H-SiC p-type epitaxial wafer sample with carbon film
S4: by step S3, treated that 4H-SiC p-type epitaxial wafer sample is removed surface carbon film process, specifically according to
Following steps are implemented:
Treated that 4H-SiC p-type epitaxial wafer sample is put into high temperature oxidation furnace by step S32 by S41, one with carbon face
Down；It vacuumizes later, after so that high-temperature oxydation furnace pressure is reached 4~5E-7Torr, fills Ar gas, setting output pressure is
12psi；Fan is opened later, power is adjusted to 60% first, is then adjusted to temperature according to 1%/10s speed and is risen to
1600 DEG C, kept for 30 minutes at 1600 DEG C, after turn off heating power adjusting knob, take out with carbon film pass through high temperature
4H-SiC p-type epitaxial wafer sample after ion implanting annealing；
S42: by step S41, treated that 4H-SiC p-type epitaxial wafer sample is put into reactive ion etching (Reactive
Ion Etching, hereinafter referred to as RIE) N is filled in cavity2, open RIE reactor chamber door；Later by 4H-SiC p-type epitaxial wafer sample
It is placed on cavity center, the one side with carbon film upward, is compressed with tweezers, is shut reactor chamber door and then is started to lead to after tightening valve
O2, flow velocity 47sccm；Radio frequency network adapter is opened, regulation power is set as 18 ± 3W, and starts 90 minutes removal SiC of timing
The carbon film of sample surfaces；Turn off radio frequency network adapter later, turns off O2Afterwards.Fill N2Until reaction chamber chamber door can automatically open,
It takes out sample and carries out RCA cleaning.
B5: by the growth process of step S4 treated 4H-SiC p-type epitaxial wafer sample sacrificial oxide layer, specifically according to
Following steps are implemented:
B51: by step S42, treated that 4H-SiC p-type epitaxial wafer sample is put into high temperature oxidation furnace, at 1200 DEG C
Oxidized surface 30min under the conditions of pure dry oxygen, makes Surface Creation with a thickness of the SiO of 20nm2Oxidation film；
B52 cleans the oxide layer on surface in step B51 treated 4H-SiC p-type epitaxial wafer sample is put into HF acid
Fall.
S6: step B5 treated 4H-SiC p-type epitaxial wafer sample is subjected to SiO2The growth of gate dielectric layer, is specifically pressed
Implement according to following steps:
By treated in step B52,4H-SiC p-type epitaxial wafer sample is put into high temperature oxidation furnace S51, is put into high temperature oxygen
Change in furnace, the N for being 750 DEG C in temperature2It is pushed into oxidation furnace flat-temperature zone in environment；Later by 3 DEG C/min rate to flat-temperature zone into
Row heating, oxygen is passed through when temperature rises to 1180 DEG C, oxygen flow 0.51/min aoxidizes epitaxial wafer under the conditions of pure dry oxygen
Surface 10 hours generates the SiO with a thickness of 51nm in epitaxial wafer front2Turn off O after oxidation film2, Ar is opened, is led to Ar gas 15 minutes；
S52 heats up to flat-temperature zone according to 3 DEG C/min rate, when temperature is raised to 1175 DEG C, opens NO, flow
577sccm, time 2 h；Turn off NO gas later, high temperature oxidation furnace furnace temperature is dropped to 900 DEG C, completes 4H-SiC p-type extension
The NO of piece sample makes annealing treatment, and stops the input of Ar gas later, takes out sample.
S6: forming source and drain Ohmic contact in step S5 treated 4H-SiC p-type epitaxial wafer sample surfaces, specifically according to
Following steps are implemented:
S61 applies removing glue to step S52 treated 4H-SiC p-type epitaxial wafer sample surfaces, and carries out whirl coating with whirl coating
Processing；
S62 carries out whirl coating with whirl coating in step S61 treated 4H-SiC p-type epitaxial wafer sample surfaces resist coating
Processing；The 4H-SiC p-type epitaxial wafer sample for getting rid of glue after 10~15min of front baking, is contacted into light using source and drain at 80 DEG C later
It cuts blocks for printing to the epitaxial wafer exposure after front baking；Develop in positivity developer solution later, solution temperature is 20 DEG C, and developing time is
85s；The epitaxial wafer after development is subjected to post bake in ultrapure water later, coolant-temperature gage is 20 DEG C, and the post bake time is 85s；Exist later
Remove exposed photoresist in equipment for burning-off photoresist by plasma, exposes effective source and drain areas；The 4H-SiC of photoresist will be removed later
P-type epitaxial wafer sample is impregnated 5 hours in acetone and is ultrasonically treated 1 minute using acetone, and then acetone, alcohol washes are each again
Once, the removing glue for removing source and drain ohmic contact regions exposes effective source and drain contact area；
Treated that 4H-SiC p-type epitaxial wafer sample is put into eb evaporation chambers by step S62 by S63, large area evaporation
Three kinds of metal Al/Ni/Au do source and drain Ohm contact electrode, and thickness is respectively 150nm, 50nm and 70nm；
Treated that 4H-SiC p-type epitaxial wafer sample is removed to step S63 by S64, forms source and drain Ohmic contact figure
Shape；
Treated that 4H-SiC p-type epitaxial wafer sample is placed in annealing furnace by step S64 by S65, and alloy moves back at 950 DEG C
Fire 30 minutes.
S7: step S5 treated 4H-SiC p-type epitaxial wafer sample is carried out to the formation of gate figure, specifically according to following
Step is implemented:
S71 applies removing glue to step S62 treated 4H-SiC p-type epitaxial wafer sample surfaces, and carries out whirl coating with whirl coating
Processing；
S72 carries out whirl coating with whirl coating in step S71 treated 4H-SiC p-type epitaxial wafer sample surfaces resist coating
After processing, then to getting rid of the 4H-SiC p-type epitaxial wafer sample of glue 10~15min of front baking at 80 DEG C；Grid photoetching is utilized later
Version exposes the epitaxial wafer after front baking；Develop in positivity developer solution, solution temperature is 20 DEG C, developing time 85s；Later
Epitaxial wafer after development is subjected to post bake in ultrapure water, coolant-temperature gage is 20 DEG C, and the post bake time is 85s；Later in plasma
Remove exposed photoresist in resist remover, then the epitaxial wafer for removing photoresist is impregnated 5 hours in acetone and utilized
Acetone ultrasound 1 minute, then acetone, alcohol washes are each primary again, remove the removing glue in grid metal region, expose effective grid region
Domain；
4H-SiC p-type epitaxial wafer sample after step S72 processing is placed in eb evaporation chambers by S73, is removing the outer of glue
Prolong piece front large area electron beam evaporation Ni/Au metal and do grid, evaporation wherein Ni metal with a thickness of 20nm, the thickness of Au metal
For 240nm；
Step S73 treated 4H-SiC p-type epitaxial wafer sample is formed gate figure using stripping means by S74.
S8: carrying out electrode fabrication for step S7 treated SiC MOSFET element, i.e. completion SiCMOSFET device channel
The improvement of mobility, is specifically implemented according to the following steps:
S81 applies removing glue in step S74 treated 4H-SiC p-type epitaxial wafer sample surfaces, and carries out whirl coating with whirl coating
After processing, to getting rid of the 4H-SiC p-type epitaxial wafer sample of glue 10~15min of front baking at 80 DEG C:
S82 carries out whirl coating with whirl coating in step S81 treated 4H-SiC p-type epitaxial wafer sample surfaces resist coating
After processing, the epitaxial wafer after front baking is exposed using interconnection contact version；Develop in positivity developer solution later, solution temperature is
20 DEG C, developing time 85s；The epitaxial wafer after development is subjected to post bake in ultrapure water later, coolant-temperature gage is 20 DEG C, when post bake
Between be 85s；Remove exposed photoresist in equipment for burning-off photoresist by plasma later, then the epitaxial wafer of photoresist will be gone third
It is impregnated 5 hours in ketone and using acetone ultrasound 1 minute, then acetone, alcohol washes was each primary again, remove contact interconnection area
Removing glue, expose effective contact area；
S83 is put into eb evaporation chambers 4H-SiC p-type epitaxial wafer sample after step S82 processing, large area evaporation
Ti/Au, with a thickness of 50nm/200nm；
4H-SiC p-type epitaxial wafer sample after step S83 processing is formed grid, source, leakage interconnection network using stripping means by S84
Shape forms the improvement that channel mobility after step S92 processing is completed in last electrode contact by stripping means.
Embodiment 2
Compared with Example 1, the step of the present embodiment is more simple, can not use sacrificial oxide layer, reduce technique
Fussy degree, specifically in accordance with the following methods implement:
S1: surface clean is carried out to 4H-SiC p-type epitaxial wafer sample using RCA standard cleaning method, specifically according to following step
Suddenly it is cleaned:
4H-SiC p-type epitaxial wafer sample is successively immersed in acetone by S11, each 5min in dehydrated alcohol, then is rushed with deionized water
It washes, to remove the grease of epitaxial wafer sample surfaces；
4H-SiC p-type epitaxial wafer sample after S12 cleans S11 is placed in H22O4∶H2O2The solution of=1: 1 (volume ratio)
The concentration that the concentration of middle immersion 15min, H2SO4 are 98%, H2O2 is 27%, is then rinsed with deionized water；
4H-SiC p-type epitaxial wafer sample after S13 cleans S12 is placed in HF: H2In the solution of O=1: 10 (volume ratios)
1min is impregnated to float natural oxidizing layer, and the concentration of HF acid is 40%, and is rinsed with deionized water；
4H-SiC p-type epitaxial wafer sample after S14 cleans S13 is immersed in NH4OH∶H2O2: DIW=3: 3: 10 (volume ratios)
Solution in boil, the concentration that the concentration of NH4OH is 28%, H2O2 is 27%, then is rinsed with deionized water；
4H-SiC p-type epitaxial wafer sample after S15 cleans S14 is placed in HF: H2In the solution of O=1: 10 (volume ratios)
30s is impregnated, the concentration of HF acid is 40%, and is rinsed with deionized water；
A16 A15 is cleaned after 4H-SiC p-type epitaxial wafer sample HCl: H2O2: DIW=3: 3: 10 (volume ratios) it is molten
It is boiled in liquid, the concentration of HCl is 10%, H2O2Concentration be 27%, rinsed with deionized water；
4H-SiC p-type epitaxial wafer sample after S17 cleans S16 soaks in the solution of HF: H2O=1: 10 (volume ratios)
30s is steeped, and is rinsed with deionized water, the concentration of HF acid is 40%, finally uses N2Rifle drying.
4H-SiC p-type epitaxial wafer sample after S2 cleans step S1 carries out ion implanting, specifically real according to the following steps
It applies:
The 4H-SiC p-type epitaxial wafer sample that step S17 was cleaned is put into high temperature tension room and carries out channel As by S21
Temperature is adjusted to 400 DEG C by ion implanting, and the N~+ implantation dosage and energy are respectively as follows: 4.14 × 1011cm-2/ 30K,
4.37×1011cm-2/ 55K, 4.61 × 1011cm-2/ 80K, 12.1 × 1011cm-2/125K；
S22 by step S21 treated 4H-SiC p-type epitaxial wafer sample is put into volume ratio be 1: 10 HF and water it is mixed
Solution rinsing is closed, the SiO on surface is removed2Layer, the concentration of the HF are 40%；
The epitaxial wafer of step S22 treated 4H-SiC p-type epitaxial wafer sample is put into PECVD reaction chamber by S231,
Make its surface deposition with a thickness of the SiO of 60nm under conditions of 300 DEG C2Layer；
S232 deposited SiO2 layers of 4H-SiC p-type epitaxial wafer sample surface resist coating；Whirl coating is carried out with whirl coating later
After processing, front baking is carried out at 80 DEG C, the front baking time is 10~15min, after injecting reticle to front baking using source and drain later
After epitaxial wafer sample exposure, develop in positivity developer solution, solution temperature is 20 DEG C, developing time 85s；It will be developed later
Epitaxial wafer afterwards carries out post bake in ultrapure water, and coolant-temperature gage is 20 DEG C, and the post bake time is 85s；Later in equipment for burning-off photoresist by plasma
Remove exposed photoresist, exposes effective source and drain areas；
The SiO that S233 protects 4H-SiC p-type epitaxial wafer sample without photoresist in HF acid solution2Layer washes,
Expose source and drain high temperature tension region；
Treated that 4H-SiC p-type epitaxial wafer sample is put into high temperature tension machine the source that carries out by step S233 by S234
N+ ion implanting is leaked, temperature is adjusted to 400 DEG C, implantation dosage and energy following 5 × 1014cm-2/ 30K, 6.0 × 1014cm-2/
60K, 8 × 1014cm-2/ 120K, 1.5 × 1015cm-2/ 190K, implantation concentration are 1 × 1020cm-3Left and right, depth are 0.3 μm of left side
It is right；
S235 to step S234 treated 4H-SiC p-type epitaxial wafer sample volume ratio be 1: 10 HF and water it is mixed
Solution rinsing is closed, the SiO2 layer on surface is removed, the concentration of the HF is 40%.
S3: forming carbon protective film in the surface of step S2 treated 4H-SiC p-type epitaxial wafer sample, specifically according to
Lower step is implemented:
A31 gets rid of step S235 treated 4H-SiC p-type epitaxial wafer sample surfaces resist coating with whirl coating
After glue processing, front baking 1 minute at 90 DEG C is put into oven；
Treated that 4H-SiC p-type epitaxial wafer sample is put into high-temperature annealing furnace by step S31 by S32, and carbon is face-up；It
After vacuumize 2 hours, after so that high-temperature annealing furnace pressure is reached 4~5E-7Torr, fill Ar gas, setting output pressure is 12psi；Later
Fan is opened, power is adjusted to 10% first, 30% power is then transferred to according to 5%/2min speed, then carefully
It adjusts power to be adjusted to temperature according to the power of 2%/2min and rises to 600 DEG C, after being kept for 30 minutes at 600 DEG C, turn off liter
Warm power adjusting knob takes out the 4H-SiC p-type epitaxial wafer sample with carbon film
S4: by step S3, treated that 4H-SiC p-type epitaxial wafer sample is removed surface carbon film process, specifically according to
Following steps are implemented:
Treated that 4H-SiC p-type epitaxial wafer sample is put into high temperature oxidation furnace by step S3 by S41, one with carbon face
Down；It vacuumizes later, after so that high-temperature oxydation furnace pressure is reached 4~5E-7Torr, fills Ar gas, setting output pressure is
12psi；Fan is opened later, power is adjusted to 60% first, is then adjusted to temperature according to 1%/10s speed and is risen to
1600 DEG C, kept for 30 minutes at 1600 DEG C, after turn off heating power adjusting knob, take out with carbon film pass through high temperature
4H-SiC p-type epitaxial wafer sample after ion implanting annealing；
S42: by step S41, treated that 4H-SiC p-type epitaxial wafer sample is put into reactive ion etching (Reactive
Ion Etching, hereinafter referred to as RIE) N is filled in cavity2, open RIE reactor chamber door；Later by 4H-SiC p-type epitaxial wafer sample
It is placed on cavity center, the one side with carbon film upward, is compressed with tweezers, is shut reactor chamber door and then is started to lead to after tightening valve
O2, flow velocity 47sccm；Radio frequency network adapter is opened, regulation power is set as 18 ± 3W, and starts 90 minutes removal SiC of timing
The carbon film of sample surfaces；Turn off radio frequency network adapter later, turns off O2Afterwards.Fill N2Until reaction chamber chamber door can automatically open,
It takes out sample and carries out RCA cleaning.
S5: step S42 treated 4H-SiC p-type epitaxial wafer sample is subjected to SiO2The growth of gate dielectric layer, is specifically pressed
Implement according to following steps:
By treated in step S52,4H-SiC p-type epitaxial wafer sample is put into high temperature oxidation furnace S51, is put into high temperature oxygen
Change in furnace, the N for being 750 DEG C in temperature2It is pushed into oxidation furnace flat-temperature zone in environment；Later by 3 DEG C/min rate to flat-temperature zone into
Row heating, oxygen is passed through when temperature rises to 1180 DEG C, oxygen flow 0.5l/min aoxidizes epitaxial wafer under the conditions of pure dry oxygen
Surface 10 hours generates the SiO with a thickness of 51nm in epitaxial wafer front2Turn off O after oxidation film2, Ar is opened, is led to Ar gas 15 minutes；
S52 heats up to flat-temperature zone according to 3 DEG C/min rate, when temperature is raised to 1175 DEG C, opens NO, flow
577sccm, time 2 h；Turn off NO gas later, high temperature oxidation furnace furnace temperature is dropped to 900 DEG C, completes 4H-SiC p-type extension
The NO of piece sample makes annealing treatment, and stops the input of Ar gas later, takes out sample.
S6: forming source and drain Ohmic contact in step S5 treated 4H-SiC p-type epitaxial wafer sample surfaces, specifically according to
Following steps are implemented:
S61 applies removing glue to step S52 treated 4H-SiC p-type epitaxial wafer sample surfaces, and carries out whirl coating with whirl coating
Processing；
S62 carries out whirl coating with whirl coating in step S61 treated 4H-SiC p-type epitaxial wafer sample surfaces resist coating
Processing；The 4H-SiC p-type epitaxial wafer sample for getting rid of glue after 10~15min of front baking, is contacted into light using source and drain at 80 DEG C later
It cuts blocks for printing to the epitaxial wafer exposure after front baking；Develop in positivity developer solution later, solution temperature is 20 DEG C, and developing time is
85s；The epitaxial wafer after development is subjected to post bake in ultrapure water later, coolant-temperature gage is 20 DEG C, and the post bake time is 85s；Exist later
Remove exposed photoresist in equipment for burning-off photoresist by plasma, exposes effective source and drain areas；The 4H-SiC of photoresist will be removed later
P-type epitaxial wafer sample is impregnated 5 hours in acetone and is ultrasonically treated 1 minute using acetone, and then acetone, alcohol washes are each again
Once, the removing glue for removing source and drain ohmic contact regions exposes effective source and drain contact area；
Treated that 4H-SiC p-type epitaxial wafer sample is put into eb evaporation chambers by step S62 by S63, large area evaporation
Three kinds of metal Al/Ni/Au do source and drain Ohm contact electrode, and thickness is respectively 150nm, 50nm and 70nm；
Treated that 4H-SiC p-type epitaxial wafer sample is removed to step S63 by S64, forms source and drain Ohmic contact figure
Shape；
Treated that 4H-SiC p-type epitaxial wafer sample is placed in annealing furnace by step S64 by S65, and alloy moves back at 950 DEG C
Fire 30 minutes.
S7: step S5 treated 4H-SiC p-type epitaxial wafer sample is carried out to the formation of gate figure, specifically according to following
Step is implemented:
S71 applies removing glue to step S62 treated 4H-SiC p-type epitaxial wafer sample surfaces, and carries out whirl coating with whirl coating
Processing；
S72 carries out whirl coating with whirl coating in step S71 treated 4H-SiC p-type epitaxial wafer sample surfaces resist coating
After processing, then to getting rid of the 4H-SiC p-type epitaxial wafer sample of glue 10~15min of front baking at 80 DEG C；Grid photoetching is utilized later
Version exposes the epitaxial wafer after front baking；Develop in positivity developer solution, solution temperature is 20 DEG C, developing time 85s；Later
Epitaxial wafer after development is subjected to post bake in ultrapure water, coolant-temperature gage is 20 DEG C, and the post bake time is 85s；Later in plasma
Remove exposed photoresist in resist remover, then the epitaxial wafer for removing photoresist is impregnated 5 hours in acetone and utilized
Acetone ultrasound 1 minute, then acetone, alcohol washes are each primary again, remove the removing glue in grid metal region, expose effective grid region
Domain；
4H-SiC p-type epitaxial wafer sample after step S72 processing is placed in eb evaporation chambers by S73, is removing the outer of glue
Prolong piece front large area electron beam evaporation Ni/Au metal and do grid, evaporation wherein Ni metal with a thickness of 20nm, the thickness of Au metal
For 240nm；
Step S73 treated 4H-SiC p-type epitaxial wafer sample is formed gate figure using stripping means by S74.
S8: carrying out electrode fabrication for step S7 treated SiC MOSFET element, i.e. completion SiCMOSFET device channel
The improvement of mobility, is specifically implemented according to the following steps:
S81 applies removing glue in step S74 treated 4H-SiC p-type epitaxial wafer sample surfaces, and carries out whirl coating with whirl coating
After processing, to getting rid of the 4H-SiC p-type epitaxial wafer sample of glue 10~15min of front baking at 80 DEG C:
S82 carries out whirl coating with whirl coating in step S81 treated 4H-SiC p-type epitaxial wafer sample surfaces resist coating
After processing, the epitaxial wafer after front baking is exposed using interconnection contact version；Develop in positivity developer solution later, solution temperature is
20 DEG C, developing time 85s；The epitaxial wafer after development is subjected to post bake in ultrapure water later, coolant-temperature gage is 20 DEG C, when post bake
Between be 85s；Remove exposed photoresist in equipment for burning-off photoresist by plasma later, then the epitaxial wafer of photoresist will be gone third
It is impregnated 5 hours in ketone and using acetone ultrasound 1 minute, then acetone, alcohol washes was each primary again, remove contact interconnection area
Removing glue, expose effective contact area；
S83 is put into eb evaporation chambers 4H-SiC p-type epitaxial wafer sample after step S82 processing, large area evaporation
Ti/Au, with a thickness of 50nm/200nm；
4H-SiC p-type epitaxial wafer sample after step S83 processing is formed grid, source, leakage interconnection network using stripping means by S84
Shape forms the improvement that channel mobility after step S92 processing is completed in last electrode contact by stripping means.
Fig. 1-Fig. 2 is the improvement for improving 4H-SiC p-type epitaxial wafer sample channel mobility using method provided by the invention
Effect picture, as seen from the figure, after the 4H-SiC p-type epitaxial wafer sample channel As ion implanting after improvement, mobility can be with
It is increased to 150cm2V-1s-1, still it is able to maintain good transistor working characteristics.
It should be understood that it can be modified or changed according to the above description for those skilled in the art, and
All these modifications and variations should all belong to the protection domain of appended claims of the present invention.
Claims (7)
1. a kind of method for improving SiC MOSFET element channel mobility, which comprises the following steps:
The cleaning of S1:SiC MOSFET element substrate surface；
S2: the SiC MOSFET element after step S1 cleaning is subjected to ion implanting；
S3: carbon protective film is formed in the surface of step S2 treated SiC MOSFET element；
S4: by step S3, treated that SiC MOSFET element is removed surface carbon film process；
S5: step S4 treated SiC MOSFET element is subjected to SiO2The growth of gate dielectric layer；
S6: source and drain Ohmic contact is formed in treated the SiC MOSFET element surface step S5；
S7: step S5 treated SiC MOSFET element is carried out to the formation of gate figure；
S8: carrying out electrode fabrication for step S6 treated SiC MOSFET element, i.e. completion SiC MOSFET element channel moves
The improvement of shifting rate；
Wherein, step S2 specifically includes the following steps:
S21 high temperature As ion implanting: the SiC MOSFET element after step S1 cleaning is put into high temperature tension machine, 400
Carrying out high temperature As ion implanting at a temperature of DEG C in four times, the As ion implantation dosage and energy be respectively as follows: 4.14 ×
1011cm-2/ 30K, 4.37 × 1011cm-2/ 55K, 4.61 × 1011cm-2/ 80K, 12.1 × 1011cm-2/125K；
The mixed solution of hydrofluoric acid and water that step S21 treated SiC MOSFET element is put into volume ratio is 1: 10 by S22
Rinsing, removes the SiO on surface2Layer, the concentration of the hydrofluoric acid are 40%；
S23 source and drain high temperature tension, is specifically implemented according to the following steps:
Step S22 treated SiC MOSFET element using plasma enhancing chemical vapour deposition technique is carried out table by S231
Face SiO2The deposit of layer, the SiO2Layer with a thickness of 60~70nm；
S232 deposited SiO2The SiC MOSFET element surface resist coating of layer, and make source, drain region by lithography；
The SiO that S233 protects SiC MOSFET element without photoresist in HF acid solution2Layer washes, and it is high to expose source and drain
Warm ion implanted regions；
Treated that SiC MOSFET element is put into high temperature tension machine by step S233 by S234,400 DEG C at a temperature of point
Four progress high temperature N~+ implantations, carry out high temperature As ion implanting in four times at 400 DEG C, the N~+ implantation dosage and
Energy is respectively as follows: 5 × 1014cm-2/ 30K, 6.0 × 1014cm-2/ 60K, 8 × 1014cm-2/ 120K, 1.5 × 1015cm-2/190K；
Treated that SiC MOSFET element is cleaned in HF solution by step S234 by S235, removes SiC MOSFET element
The SiO on surface2Barrier layer；
Step S4 specifically includes the following steps:
Treated that SiC MOSFET element is put in high-temperature annealing furnace by step S3 by S41, down by have carbon film one, takes out true
Sky is to 10-7Torr, applying argon gas are gradually warming up to 1600 DEG C, stop 30 minutes at 1600 DEG C, carry out high temperature tension annealing,
It is taken out after being down to room temperature；
S42 is removed the carbon film on treated the SiC MOSFET element surface step S41 using reactive ion etching method；Then,
Also carry out step B5: by the growth process of step S42 treated SiC MOSFET element sacrificial oxide layer, then by the oxygen on surface
Change layer to wash.
2. a kind of method for improving SiC MOSFET element channel mobility according to claim 1, which is characterized in that institute
State step S3 specifically includes the following steps:
S31 is put into step S2 treated SiC MOSFET element surface resist coating, and after carrying out whirl coating processing with whirl coating
In oven at 90 DEG C front baking 1 minute；
Treated that SiC MOSFET element is put into high-temperature annealing furnace by step S31 by S32, is kept for 30 minutes at 600 DEG C, into
After row carbonization treatment, cooling processing is carried out.
3. a kind of method for improving SiC MOSFET element channel mobility according to claim 1, which is characterized in that institute
State step S5 specifically includes the following steps:
By treated in step S4, SiC MOSFET element is put into high temperature oxidation furnace S51, is passed through oxygen under the conditions of 1180 DEG C
Gas, aoxidizes SiC MOSFET element front 10 hours under the conditions of dry oxygen, generates the SiO with a thickness of 51nm2Oxidation film；
The SiO that S52 generates step S51 treated SiC MOSFET element2Oxidation film carries out 2 hours under the conditions of 1175 DEG C
NO annealing.
4. a kind of method for improving SiC MOSFET element channel mobility according to claim 1, which is characterized in that institute
State step B5 specifically includes the following steps:
Treated that SiC MOSFET element is put into high temperature oxidation furnace by step S4 by B51, under the conditions of 1200 DEG C of pure dry oxygen
Oxidized surface 30min makes Surface Creation with a thickness of the SiO of 20nm2Oxidation film；
B52 washes the oxide layer on surface in step B51 treated SiC MOSFET element is put into HF acid.
5. a kind of method for improving SiC MOSFET element channel mobility according to claim 1, which is characterized in that institute
State step S6 specifically includes the following steps:
S61 applies removing glue to treated the SiC MOSFET element surface step S5, and carries out whirl coating processing with whirl coating；
S62 is in step S61 treated SiC MOSFET element surface resist coating, and after carrying out whirl coating processing with whirl coating, light
Carve source and drain ohmic contact hole；
S63 is respectively the Al/ of 150nm/50nm/200nm to evaporation thickness on SiC MOSFET element surface after step S62 processing
Ni/Au is as metal ohmic contact；
Treated that SiC MOSFET element is removed to step S63 by S64, forms source and drain Ohmic contact pattern；
Treated that SiC MOSFET element is placed in annealing furnace by step S64 by S65, and alloy is annealed 30 minutes at 950 DEG C.
6. a kind of method for improving SiC MOSFET element channel mobility according to claim 1, which is characterized in that institute
State step S7 specifically includes the following steps:
S71 applies removing glue to treated the SiC MOSFET element surface step S5, and carries out whirl coating processing with whirl coating；
S72 is in step S71 treated SiC MOSFET element surface resist coating, and after carrying out whirl coating processing with whirl coating, benefit
Grid metal region is made by lithography with grid version；
S73 is respectively the Ni/Au conduct of 20nm/240nm to evaporation thickness on SiC MOSFET element surface after step S72 processing
Grid contact metal；
S74 forms gate figure using stripping means.
7. a kind of method for improving SiC MOSFET element channel mobility according to claim 1, which is characterized in that institute
State step S8 specifically includes the following steps:
S81 applies removing glue in treated the SiC MOSFET element surface step S8, and carries out whirl coating processing with whirl coating；
S82 is in step S91 treated SiC MOSFET element surface resist coating, and after carrying out whirl coating processing with whirl coating, benefit
Interconnection area is carved with interconnection electrode reticle；
S83 is respectively the Ti/Au conduct of 50nm/200nm to evaporation thickness on SiC MOSFET element surface after step S92 processing
Interconnection contact metal；
S84 forms grid, source, leakage interconnection graph using stripping means, that is, completes the improvement of iC MOSFET element channel mobility.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510221211.2A CN104882367B (en) | 2015-05-05 | 2015-05-05 | A method of improving SiC MOSFET element channel mobility |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510221211.2A CN104882367B (en) | 2015-05-05 | 2015-05-05 | A method of improving SiC MOSFET element channel mobility |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104882367A CN104882367A (en) | 2015-09-02 |
| CN104882367B true CN104882367B (en) | 2019-03-29 |
Family
ID=53949815
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510221211.2A Active CN104882367B (en) | 2015-05-05 | 2015-05-05 | A method of improving SiC MOSFET element channel mobility |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104882367B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105428223B (en) * | 2015-12-09 | 2017-12-29 | 西安电子科技大学 | One kind improves SiC/SiO2The method of interface state density |
| CN109742649B (en) * | 2018-12-10 | 2020-06-23 | 西安理工大学 | Semiconductor laser epitaxial wafer annealing method based on carbon protective film |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101542688A (en) * | 2007-03-29 | 2009-09-23 | 松下电器产业株式会社 | Method for manufacturing silicon carbide semiconductor element |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8674439B2 (en) * | 2010-08-02 | 2014-03-18 | Microsemi Corporation | Low loss SiC MOSFET |
| WO2014207793A1 (en) * | 2013-06-24 | 2014-12-31 | 株式会社日立製作所 | Semiconductor device, and method for manufacturing same |
| CN105577891B (en) * | 2014-10-11 | 2018-12-21 | 北大方正集团有限公司 | Mobile phone screen setting method, device and mobile phone terminal |
-
2015
- 2015-05-05 CN CN201510221211.2A patent/CN104882367B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101542688A (en) * | 2007-03-29 | 2009-09-23 | 松下电器产业株式会社 | Method for manufacturing silicon carbide semiconductor element |
Non-Patent Citations (1)
| Title |
|---|
| 《SiC MOS器件和电路温度特性的研究》;刘莉;《中国博士学位论文全文数据库（电子期刊）》;20081231;文章75-80页工艺流程部分以及器件结构部分以及图5.3-5.4 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104882367A (en) | 2015-09-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104347418B (en) | The forming method of MOS transistor | |
| CN103730359A (en) | Manufacturing method of composite gate media SiC MISFET | |
| CN105810722A (en) | SiC metal-oxide-semiconductor field-effect transistor (MOSFET) device and fabrication method thereof | |
| KR100706798B1 (en) | Method of cleaning substrate having exposed surfaces of silicon and silicon germanium and method of forming semiconductor device using the same | |
| CN102629559B (en) | Manufacture method of stacked gate SiC-metal insulator semiconductor (MIS) capacitor | |
| JP2016537816A (en) | Method for selectively etching a mask deposited on a silicon substrate | |
| CN105470288B (en) | Delta channel doping SiC vertical power MOS device production methods | |
| US20230377898A1 (en) | Methods for reducing scratch defects in chemical mechanical planarization | |
| CN105047539B (en) | The method for improving SiC MOSFET channel mobilities | |
| CN102142369A (en) | Method for improving performance of SiC (Semiconductor Integrated Circuit) device | |
| CN114256065A (en) | Method for manufacturing gate oxide layer of SiC MOSFET device | |
| CN104882367B (en) | A method of improving SiC MOSFET element channel mobility | |
| CN112993029B (en) | Method for improving GaN HEMT interface quality | |
| CN108615731A (en) | A kind of semiconductor devices and its manufacturing method | |
| CN105280503B (en) | The method for improving transverse conductance structure SIC MOSFET channel mobilities | |
| US6878578B1 (en) | Method for forming a high quality chemical oxide on a freshly cleaned silicon surface as a native oxide replacement | |
| TW407309B (en) | MOSFET manufacturing process | |
| CN105161526B (en) | The method for improving vertical conductive structure SiC MOSFET channel mobilities | |
| TWI238475B (en) | High temperature hydrogen annealing of a gate insulator layer to increase etching selectivity between conductive gate structure and gate insulator layer | |
| CN114023633A (en) | Preparation method of gate oxide layer of silicon carbide device and silicon carbide device | |
| JP3571160B2 (en) | Method for forming oxide film on semiconductor surface and method for manufacturing semiconductor device | |
| CN102543823B (en) | Production method of shallow trench isolation | |
| KR20050000059A (en) | Method of manufacturing semicondutor device | |
| CN105140285B (en) | A kind of vertical conductive structure SiC MOSFET power devices | |
| CN107068762A (en) | The preparation method of 4H SiC metal semiconductor field effect transis with many depression cushions |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20180416 Address after: 710071 Shaanxi city of Xi'an province Taibai Road No. two Applicant after: Xidian University Address before: 710075 grade 2002, No. two Taibai Road, Yanta District, Xi'an, Shaanxi Applicant before: Liu Li |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |