CN113299641B - SiC MOS device capable of improving ESD protection loop backwash characteristic - Google Patents
SiC MOS device capable of improving ESD protection loop backwash characteristic Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention discloses a SiCMOS device capable of improving the back flushing characteristic of an ESD protection loop, which comprises an N-type SiC substrate (9), wherein an N-type SiC epitaxial region (8) is arranged on the SiC substrate (9) to form an epitaxial wafer, and the SiCMOS device is characterized in that a source P-type region (6) and a drain P-type region (7) which are mutually spaced are arranged on the SiC epitaxial region (8), a first nMOSFET (MN 1) is arranged on the drain P-type region (7), and a second nMOSFET (MN 2) is arranged on the source P-type region (6). The structure device can improve the backwash characteristic of the ESD protection circuit of the high-voltage SiCMOS device.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a structure and a manufacturing method of a SiC MOS device capable of improving the backwash characteristic of an ESD protection loop so as to reduce the trigger voltage of the device under the action of ESD and have high holding voltage.
Background
SiC has unique physical, chemical and electrical properties, and is a semiconductor material with great development potential in the extreme application fields of high temperature, high frequency, high power, radiation resistance and the like. ESD is an important reliability topic that can create over-voltage and over-current in the circuit, leading to thermal damage of the gate oxide failure device. ESD in silicon has been studied very much, but there is limited research in SiC. At present, SKYoung-II proposes a SiC grid floating NMOS device which has low on-resistance, low trigger voltage and high temperature stability. Denis studied on SiC junction barrier Schottky diodes under ESD HBM stress in order to emphasize the limitations of SiC devices and processes. T.P and the like have studied failure mechanisms of three types of transistors, and work of a MOS device under ESD stress has been studied by using methods such as PE and SPE. 15V sicnmosfesd device characteristics were previously reported to investigate the robustness of ESD and the way it was protected. However, ESD protection for SiC power devices remains only a few. It is well known that SiC materials have a critical electric field of about 10 times ec=2.4 MV/cm, si is 0.25MV/cm, and the pn junction built-in potential is about 3 times that of Si materials about 3.4V at 300K, so this material property results in a large difference between the trigger voltage and the holding voltage and has a strong back-flushing effect, which is very detrimental for optimizing the ESD design and protecting the IC core.
Disclosure of Invention
The present invention aims to solve the above-mentioned drawbacks of the prior art and to provide a SiC MOS device capable of improving the back-flushing characteristic of an ESD protection circuit to improve the trigger voltage of the device under the ESD effect and to have a high holding voltage.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
an SiC MOS device capable of improving the back flushing characteristic of an ESD protection loop comprises an N-type SiC substrate (9), wherein an N-type SiC epitaxial region (8) is arranged on the SiC substrate (9) to form an epitaxial wafer, and the SiC MOS device is characterized in that a source P-type region (6) and a drain P-type region (7) which are mutually spaced are arranged on the SiC epitaxial region (8), a first nMOSFET (MN 1) is arranged on the drain P-type region (7), and a second nMOSFET (MN 2) is arranged on the source P-type region (6);
the first nMOSFET (MN 1) comprises: a drain electrode N+ region (1) and an N+/P+ region (2) which are arranged on the source electrode P-type region (6), a first grid electrode oxide layer (10) is arranged on the drain electrode N+ region (1) and the N+/P+ region (2), and contact electrodes are respectively arranged on the drain electrode N+ region (1) and the N+/P+ region (2); a gate electrode is provided on the first gate oxide layer (10);
the second nMOSFET (MN 2) comprises: a first source N+ region (3), a second source N+ region (4) and a P+ region (5) which are sequentially arranged, wherein a second gate oxide layer (11) is arranged on the upper surface between the first source N+ region (3) and the second source N+ region (4), and contact electrodes are respectively arranged on the upper surfaces of the first source N+ region (3), the second source N+ region (4) and the P+ region (5); a gate electrode is provided on the second gate oxide layer (11);
a drain lead (D) is arranged on the contact electrode above the drain N+ region (1);
the gate electrode on the first gate oxide layer (10) is interconnected with the contact electrode on the first N+ region (3) of the source electrode through a first interconnection electrode (12), and a gate outgoing line (G) is arranged;
the N+/P+ region (2), the contact electrode on the source second N+ region (4) and the source P+ region (5) and the gate electrode on the second gate oxide layer (11) are all interconnected through a second interconnection electrode (13), and a source outgoing line (S) is arranged.
The concentration of the SiC epitaxial region (8) is 5e+15cm < -3 >, and the concentration of the N-type SiC substrate (9) is 5e+18cm < -3 >.
The manufacturing method of the SiC MOS device capable of improving the back flushing characteristic of the ESD protection loop is characterized by comprising the following steps of:
step 1, cleaning the surface of an epitaxial wafer: carrying out standard wet process cleaning on the surface of the epitaxial wafer;
step 2, manufacturing a source electrode P type region (6) and a drain electrode P type region (7): coating photoresist on the surface of a SiC epitaxial region (8) of the epitaxial wafer with the surface cleaned, etching high-temperature ion implantation regions of a source electrode P-type region (6) and a drain electrode P-type region (7), and then carrying out high-temperature Al ion implantation;
step 3, high-temperature nitrogen ion implantation is performed on the drain electrode N+ region (1), the source electrode first N+ region (3) and the source electrode second N+ region (4), N+ doped source and drain regions are carved out after high-temperature ion implantation is performed on the P-BODY region, and then high-temperature N ion implantation is performed on the N+ source and drain regions;
step 4, P type ion implantation of a source P+ region (5) and an N+/P+ region (2) is formed: after ion implantation of N+ source and drain regions, etching a P-type doped contact region, and then carrying out P-type doped high-temperature Al ion implantation;
step 5, forming a surface carbon protective film: after P-type ion implantation, forming a carbon protective film on the surface of the SiC epitaxial layer;
step 6, high-temperature ion implantation activation: carrying out 1600 ℃ high-temperature ion implantation annealing on a sample with a carbon protective film formed on the surface of the SiC epitaxial layer;
step 7, removing the surface carbon film: removing a carbon film on the surface of the SiC sample after the high-temperature ion implantation annealing;
step 8, preparing a first gate oxide layer (10) and a second gate oxide layer (11): carrying out large-area HF acid cleaning on the SiC sample from which the surface carbon film is removed, and then growing a SiO2 gate dielectric layer;
step 9, forming contact electrodes of the drain electrode N+ region (1), the N+/P+ region (2), the source electrode first N+ region (3), the source electrode second N+ region (4) and the source electrode P+ region (5): after the growth of the gate dielectric layer is finished, coating stripping glue and photoresist on the surface of the sample, etching an ohmic contact hole, carrying out ohmic contact metal deposition, stripping to form an ohmic contact pattern, and carrying out ohmic contact annealing;
step 10, forming a gate electrode: forming a gate electrode on the SiC sample subjected to the ohmic contact electrode annealing;
step 11, forming an interconnection electrode: and (3) coating stripping glue and photoresist on the surface of the SiC sample for forming the gate electrode, etching a gate and a source contact hole, depositing a gate, a source drain and a P-type ohmic contact region, and stripping to form interconnection patterns of the gate, the source drain and the P-type ohmic contact region.
The specific process of the step A2 is as follows,
a21, placing the N-/N+ type SiC epitaxial wafer sample with the surface cleaned into PECVD, and depositing a SiO2 layer with the thickness of 60nm in a large area;
a22, coating photoresist on the surface of the SiC sample deposited with SiO2, and photoetching a P-BODY region; then cleaning the SiO2 layer which is not protected by photoresist in HF acid solution to expose the high-temperature ion implantation area of the P-BODY area;
a23, placing the SiC sample exposed out of the source electrode P-type region (6) and the drain electrode P-type region (7) into a high-temperature ion implanter, and carrying out high-temperature phosphorus ion implantation at 400 ℃ for four times to form a P-BODY region, wherein the depth is about 0.7 mu m, and the concentration is 5 multiplied by 1018cm & lt-3 >
a24, cleaning the sample subjected to high-temperature ion implantation in an HF solution to remove the SiO2 barrier layer on the surface;
the specific process of the step A3 is as follows:
a31, placing the SiC sample with the SiO2 barrier layer removed on the surface into PECVD, and depositing the SiO2 layer in a large area with the thickness of 60nm;
a32, coating photoresist and spin coating on the surface of the SiC sample deposited with SiO2, and photoetching a source injection region; then the SiO2 layer which is not protected by photoresist is washed away in HF acid solution, and the source injection region is exposed;
a33, placing the SiC sample exposed from the source electrode P-type region (6) and the drain electrode P-type region (7) into a high-temperature ion implanter, and carrying out high-temperature nitrogen ion implantation at 400 ℃ for four times to form a junction depth of 0.3 mu m and a concentration of about 3X 1019cm < -3 >;
a34, cleaning the sample subjected to high-temperature ion implantation in an HF acid solution to remove the SiO2 barrier layer on the surface.
The specific process of the step A4 is as follows:
a41, placing the SiC sample with the SiO2 barrier layer on the surface removed into PECVD, and depositing the SiO2 layer in a large area with the thickness of 60nm;
a42, coating photoresist and spin coating on the surface of the SiC sample deposited with SiO2, and photoetching a P-type injection region; then cleaning the SiO2 layer which is not protected by photoresist in HF acid solution to expose the P-type injection region;
a43, placing the SiC sample with the exposed source electrode P+ region (5) and drain electrode P type region (2) into a high-temperature ion implanter, and carrying out high-temperature aluminum ion implantation at 400 ℃ for four times to form a concentration of about 1.5X11019 cm < -3 > and a depth of about 0.2 mu m;
a44, cleaning the sample subjected to high-temperature ion implantation in an HF acid solution to remove the SiO2 barrier layer on the surface.
The specific process of the step A5 is as follows:
a51, coating photoresist on the surface of the SiC epitaxial wafer sample with the SiO2 barrier layer removed, spin-coating, and pre-baking for 1 minute at 90 ℃ in an oven;
a52, placing the pre-baked SiC sample into a high-temperature annealing furnace, and keeping the temperature at 600 ℃ for 30 minutes for carbonization;
a53 cooling the carbonized SiC sample.
The specific process of the step A6 is as follows:
placing a sample carbonized on the surface of SiC in a high-temperature annealing furnace, vacuumizing the surface with the carbon film downwards to 10 < -7 > Torr, filling Ar gas, gradually heating to 1600 ℃, and staying at 1600 ℃ for 30 minutes for high-temperature ion implantation annealing;
a62, cooling the high-temperature ion implantation annealing furnace loaded with the sample to normal temperature, and taking the SiC sample out of the high-temperature annealing furnace.
The specific process of the step A7 is as follows:
a71, placing the SiC sample subjected to high-temperature ion implantation annealing into an RIE reaction chamber, turning on a valve of the reaction chamber when the surface with the carbon film is upward, opening an N2 valve to 1/4, introducing N for 260 seconds, and then turning off a nitrogen valve;
a72 after the SiC sample with the carbon film is subjected to N2 flushing for 60 seconds, the oil pump is started, the oil pump valve is completely opened until the sound of the oil pump becomes loud and becomes stable, and the pump is stable for 20-30 minutes;
a73, opening an oxygen valve until the pressure in the chamber reaches 9-12mT;
a74, opening a cooling system, and adjusting the oxygen flow to 47sccm;
a75, opening a radio frequency network adapter, and removing the carbon film on the surface of the SiC sample for 90 minutes;
a76, switching off the power supply of the network adapter and switching off O2;
a77, the system is depressurized to normal pressure, the cooling system is turned off, the inside of the RIE reaction chamber is filled with N2 until the door of the reaction chamber can be opened, and the sample is taken out.
The specific process of the step A8 is as follows:
a81, performing HF acid cleaning on the SiC sample from which the surface carbon film is removed;
a82, placing the SiC sample subjected to HF acid cleaning into a high-temperature oxidation furnace, introducing pure oxygen at 1180 ℃, and oxidizing the front surface of the SiC epitaxial wafer for 10 hours under the dry oxygen condition to generate a SiO2 oxide film with the thickness of 50 nm;
a83 nitriding the grown oxide film: NO annealing is carried out on the growing SiO2 oxide film for 2 hours at 1175 ℃;
a84 forms a gate dielectric pattern using the gate dielectric plate.
The step A9 adopts two metals of Ni/Au with the concentration of 20nm/240nm as source and drain and P-type ohmic contact metal; the specific process is as follows:
a91, coating stripping photoresist and photoetching on the front surface of the SiC sample manufactured by the gate dielectric layer, cleaning the photoresist and the stripping photoresist to expose the effective source drain and the P-type ohmic contact area;
a92 Placing the SiC sample into an electron beam evaporation chamber;
a93 evaporating Ni/Au with the thickness of 20nm/240nm on the front surface of the SiC sample to serve as source drain and P-type ohmic contact metal;
a94 stripping to form a source drain and a P-type ohmic contact metal pattern;
a95 the SiC sample subjected to the source drain and P-type ohmic contact electrode was placed in an annealing furnace and alloy annealed at 950 ℃ for 30 minutes.
The step A10 adopts two metals of Ni/Au with the wavelength of 20nm/240nm as gate metals; the specific process is as follows:
a101, coating stripping adhesive and spin coating adhesive on the surface of the SiC sample subjected to source-drain and P-type ohmic contact;
a102, coating photoresist on the surface of the SiC sample coated with the stripping photoresist, throwing photoresist, and photoetching a gate metal area by using a gate plate;
a103, evaporating Ni/Au with the thickness of 20nm/240nm on the surface of the SiC sample with the etched gate contact holes as gate contact metal;
a104 forms a gate pattern by a lift-off method.
The step A11 is that the manufacture of the interconnection electrode adopts Ti/Au two metals, and the thickness is 50nm/200nm respectively; the method comprises the following steps:
a111, coating stripping adhesive and photoresist on the surface of the SiC sample after the gate metal is manufactured;
a112, etching a grid, a source, a drain and a P-type ohmic contact electrode interconnection window by utilizing interconnection photoetching;
a113 evaporating Ti/Au with the thickness of 30nm/200nm on the surface of the SiC sample on which the grid, the source, the drain and the P-type ohmic contact holes are carved to be used as grid, source, drain and P-type ohmic contact metals;
a114 forms gate, source, drain and P-type ohmic contact interconnection patterns using a lift-off method.
Compared with the prior art, the invention has the following advantages: according to the invention, through improving the traditional SiC MOS structure, the trigger voltage of the device under the action of ESD is reduced, and the device has high holding voltage, so that the back flushing effect of an ESD protection loop of the device can be effectively restrained.
Drawings
FIG. 1 is a schematic diagram of the structure of the device of the present invention;
FIG. 2 is a schematic diagram of an equivalent circuit of the device of the present invention;
fig. 3 is a schematic flow chart of a method for manufacturing a device according to the present invention, wherein (a) - (g) show the contents of the processing of each step (cross-sectional view of the device), and wherein: (a) drawing shows the cleaned epitaxial wafer; (b) after implantation of the source P-type region 6 and the drain P-type region 7; (c) The diagram shows the completed drain N + Zone 1, N + /P + Region 2, source electrode first N + Region 3, drain electrode second N + Region 4 and drain electrode P + After ion implantation in region 5; (d) The figure shows the first gate oxide layer 10 and the second gate oxide layer 11 after completion; (e) The diagram shows the completed drain N + Zone 1, N + /P + Region 2, source electrode first N + Region 3, drain electrode second N + Region 4 and drain electrode P + After the contact electrode 15 of zone 5; (f) after completing the gate electrode; (g) drawing shows the interconnection electrode after completion.
Reference numerals illustrate: 1. drain N + Region 2, N + /P + Region 3, source electrode first N + Region 4, source electrode second N + Region 5, source electrode P + Region 6, source electrode P type region, 7, drain electrode P type region, 8, siC epitaxial region, 9, siC substrate, 10, first gate oxide layer, 11, second gate oxide layer, 12, first interconnection electrode, 13, second interconnection electrode, 14, gate electrode, 15, contact electrode, D, drain electrode lead, G, gate lead, S, source lead.
Detailed Description
Referring to fig. 1, the high-voltage SiC power MOS device capable of improving ESD protection backwash effect of the present invention includes an N-type SiC substrate 9, an N-type SiC epitaxial region 8 is provided on the SiC substrate 9 to form an epitaxial wafer, and is characterized in that a source P-type region 6 and a drain P-type region 7 spaced apart from each other are provided on the SiC epitaxial region 8, a first nMOSFET, denoted as MN1 (located in the left half of fig. 1), is provided on the drain P-type region 7, and a second nMOSFET, denoted as MN2 (located in the right half of fig. 1), is provided on the source P-type region 6.
The first nMOSFET labeled MN1 comprises: a drain N arranged on the source P-type region 6 + Regions 1 and N + /P + Region 2 at the drain N + Regions 1 and N + /P + A first gate oxide layer 10 is provided between the regions 2, on the drain N + Regions 1 and N + /P + Contact electrodes 15 are provided on the upper surfaces of the regions 2, respectively, and gate electrodes 14 are provided on the upper surface of the first gate oxide layer 10.
The second nmosfet MN2, labeled MN2, includes: sequentially arranged source electrodes of first N + Region 3, source electrode second N + Region 4 and source electrode P + Region 5, at the source electrode first N + Region 3 and source second N + A second gate oxide layer 11 is provided on the upper surface between the regions 4, a first N is provided at the source + Region 3, source electrode second N + Region 4, source electrode P + A contact electrode 15 is provided on each of the regions 5, and a further gate electrode 14 is provided on the second gate oxide 11.
At the drain electrode N + A drain lead D is provided on the contact electrode 15 above the region 1.
A gate electrode 14 on the first gate oxide layer 10 and a source electrode first N + The contact electrodes 15 over the regions 3 are interconnected by means of the first interconnect electrode 12 and are provided with gate lead-out lines G.
Said N + /P + Region 2, source electrode second N + Region 4 and source electrode P + The contact electrode 15 above the region 5 and the gate electrode above the second gate oxide layer (11) are interconnected by means of a second interconnect electrode 13 and provided with a source lead-out S.
The equivalent circuit of the above device of the present invention is shown in FIG. 2, in which the drain N of MN1 + Zone 1, N + /P + N of zone 2 + The region and drain P-type region 7 form an NPN transistor QN1,the base electrode and N of the triode QN1 + /P + P of zone 2 + A resistor Rp is formed between the regions. Source first N of MN2 in device + Region 3 and source second N + The region 4 forms a diode D1 and a diode D2 with the source electrode P type region respectively, and the positive electrode of the two diodes D1 and D2 and the source electrode P + The regions 5 correspond to interconnections. The gate of MN1 is connected to the drain region (drain N) of MN2 via the first interconnection electrode 12 + Region 3) is connected to the drain region (drain N) of MN1 + Region 1) has drain lead D connected, which discharges most of the ESD current from drain D to source S of the device through equivalent NPN transistor QN 1.
In the normal operation mode without electrostatic discharge, MN1 does not operate because of the high potential of the reverse junction, but when ESD (electrostatic discharge) occurs, the drain N + The PN junction between the region 1 and the drain P-type region 7 shows avalanche breakdown, and the generated hole current drives the triode QN1 to release ESD current.
N of MN1 + /P + Zone 2 employs N + /P + The cross doping can effectively improve the emitter injection effect of two parasitic bipolar transistors in the conventionally used SCR structure. And the body and source regions in the SCR structure are in a hold state at the same time. N of MN1 + /P + N of zone 2 + The narrower of the emitter region of the region QN1, reduces the emitter injection efficiency of QN 1. The reduction in emitter injection efficiency increases the voltage drop of the device in the on state, thereby increasing the holding voltage. And N is + /P + P of zone 2 + The reduction of the doping concentration of the region relative to the N+ region limits the conduction of the vertical NPN parasitic transistor under the junction, increases the forward bias of QN1, promotes more current to flow from the QN1 tube to the source electrode, reduces the trigger voltage and plays a role in inhibiting ESD. The gate of MN1 is connected to the drain of MN2 to achieve gate coupling, so when MN1 discharges ESD current, the reverse junction of MN2 supports the voltage between the source second n+ region 4 and the source p+ region 5 to reduce the trigger voltage.
Referring to fig. 3, the process flow of the first embodiment of the method for manufacturing a device according to the present invention is as follows (the specific operations of each step of the following process belong to the conventional technology):
step 1, surface cleaning is performed on a 4H-SiC P-/N+ type epitaxial wafer sample by adopting a standard cleaning method RCA (see a graph in FIG. 3).
And 2, manufacturing a high-temperature ion implantation region (see b diagram) of a source electrode P type region (6) and a drain electrode P type region (7) on an epitaxial surface on the front surface of the epitaxial wafer sample.
(2a) Placing the cleaned epitaxial wafer into a P-BODY reaction chamber, and depositing SiO on the surface at 300 deg.C 2 A layer having a thickness of 60nm;
(2b) At the moment of depositing SiO 2 Coating photoresist on the epitaxial wafer of the layer;
(2c) Photoresist is thrown, and then, the epitaxial wafer after the photoresist throwing is pre-baked at 90 ℃; the pre-baking time is 1min;
(2d) Exposing the epitaxial wafer sample after pre-baking by using an N-WELL injection photoetching plate;
(2e) Developing in positive developing solution at 20 deg.c for 20s;
(2f) Hardening the developed epitaxial wafer in ultrapure water at the water temperature of 20 ℃ for 20s;
(2g) Removing the exposed photoresist in a plasma photoresist remover to expose an effective N-WELL area;
(2h) The exposed SiO is then exposed to an HF acid solution 2 The layers are washed away;
(2i) Will wash off SiO 2 The epitaxial wafer of the layer is put into a high temperature ion implantation chamber to carry out P-BODY ion implantation, the temperature is adjusted to 400 ℃ to form a P-BODY region, the depth is about 0.7 mu m, and the concentration is 5 multiplied by 10 18 cm- 3 ；
(2j) The volume ratio of the injected sample is 1:10 (concentration of 40%) and water to remove SiO on the surface 2 A layer;
step 3, performing source-drain region ion implantation on the source electrode P-type region (6) and the drain electrode P-type region (7) + Zone 1, N + /P + Zone 2, middle N + Region 3, source N + Zone 4 (see panel c in fig. 3):
(3a) Placing the cleaned epitaxial wafer into a PECVD reaction chamber, and depositing Si on the surface at 300 DEG CO 2 A layer having a thickness of 60nm;
(3b) At the moment of depositing SiO 2 Coating photoresist on the epitaxial wafer of the layer;
(3c) Photoresist is thrown, and then, the epitaxial wafer after the photoresist throwing is pre-baked at 90 ℃; the pre-baking time is 1min;
(3d) Exposing the epitaxial wafer sample after pre-baking by using an N-source injection photomask;
(3e) Developing in positive developing solution at 20 deg.c for 20s;
(3f) Hardening the developed epitaxial wafer in ultrapure water at the water temperature of 20 ℃ for 20s;
(3g) Removing the exposed photoresist in a plasma photoresist remover to expose an effective N-source region;
(3h) The exposed SiO is then exposed to an HF acid solution 2 The layers are washed away;
(3i) Will clean the source drain region SiO 2 Placing the epitaxial wafer into a high temperature ion implantation chamber for source N ion implantation, adjusting temperature to 400 deg.C, and performing high temperature nitrogen ion implantation to form junction depth of 0.3 μm and concentration of about 3×10 19 cm- 3 。
(3j) The volume ratio of the injected sample is 1:10 (concentration of 40%) and water to remove SiO on the surface 2 A layer;
step 4, P-type region ion implantation N is carried out on the source electrode P-type region (6) and the drain electrode P-type region (7) + /P + Region 2, source electrode P + Zone 5 (see panel c in fig. 3):
(4a) Placing the cleaned epitaxial wafer into a PECVD reaction chamber, and depositing SiO on the surface at 300 DEG C 2 A layer having a thickness of 60nm;
(4b) At the moment of depositing SiO 2 Coating photoresist on the epitaxial wafer of the layer;
(4c) Photoresist is thrown, and then, the epitaxial wafer after the photoresist throwing is pre-baked at 90 ℃; the pre-baking time is 1min;
(4d) Exposing the epitaxial wafer sample after pre-baking by using a P-type injection photoetching plate;
(4e) Developing in positive developing solution at 20 deg.c for 20s;
(4f) Hardening the developed epitaxial wafer in ultrapure water at the water temperature of 20 ℃ for 20s;
(4g) Removing the exposed photoresist in a plasma photoresist remover to expose an effective P+ region;
(4h) The exposed SiO is then exposed to an HF acid solution 2 The layers are washed away;
(4i) Will clean the source drain region SiO 2 The epitaxial wafer of the layer is put into a high-temperature ion implantation chamber to implant Al ions in a source P-type region (6) and a drain P-type region (7), the temperature is adjusted to 400 ℃, and the concentration is formed to be about 1.5 multiplied by 10 19 cm- 3 The depth is about 0.2 μm.
(4j) The volume ratio of the injected sample is 1:10 (concentration of 40%) and water to remove SiO on the surface 2 A layer;
the following steps 5-9 are process flows for preparing the first gate oxide layer 10 and the second gate oxide layer 11 (see d diagram in fig. 3):
step 5, manufacturing a high-temperature ion implantation annealing carbon protection film on the front surface of the N-/N+ epitaxial wafer sample:
(5a) Removing SiO on the surface 2 Coating photoresist on the surface of the SiC epitaxial wafer sample of the barrier layer;
(5b) Spin coating, and pre-baking in an oven at 90 ℃ for 1 minute;
(5c) Placing the pre-baked SiC sample into a high-temperature annealing furnace with the carbon surface facing upwards;
(5d) Vacuumizing for 2 hours, wherein the pressure reaches 4-5E-7 Torr;
(5e) Ar gas is filled, and the output pressure is set to be 12psi;
(5f) Turning on a fan;
(5g) Firstly, regulating the power of a power supply to 10%, then regulating the power of the power supply to 30% according to the speed of 5%/2min, then regulating the power of the power supply to the temperature of 600 ℃ according to the power of 2%/2min, and keeping the temperature at 600 ℃ for 30 minutes;
(5h) Turning off a heating power supply power adjusting knob;
(5i) Taking out the SiC sample with the carbon film;
step 6, high-temperature ion implantation annealing;
(6a) Placing a SiC sample with a carbon protective film into a high-temperature annealing furnace, wherein the surface with a carbon surface faces downwards;
(6b) Vacuumizing, wherein the pressure reaches 4-5E-7 Torr;
(6c) Ar gas is filled, and the output pressure is set to be 12psi;
(6d) Turning on a fan;
(6e) Firstly, regulating the power of a power supply to 60%, then regulating the power to the temperature to 1600 ℃ according to the speed of 1%/10s, and keeping the power at 1600 ℃ for 30 minutes;
(6f) Turning off a heating power supply power adjusting knob;
(6i) Taking out the SiC sample with the carbon film after high-temperature ion implantation annealing;
step 7, removing the carbon protective film on the front surface of the N-/N+SiC epitaxial sample:
(7a) Filling the RIE chamber with N 2 Opening the RIE reaction chamber door;
(7b) Placing the sample in the center, pressing the sample with the carbon film upwards by forceps, closing the reaction chamber door and then screwing the valve;
(7c) Start to open O 2 A flow rate of 47sccm;
(7d) Opening a radio frequency network adapter, and adjusting the power to be 18+/-3W;
(7e) Starting timing for 90 minutes to remove the carbon film on the surface of the SiC sample;
(7f) Turning off the radio frequency network adapter, turning off O 2 ；
(7g) N-filled 2 Until the reaction chamber door can be automatically opened, taking out the sample;
(7h) Performing RCA cleaning on the SiC sample from which the surface carbon film is removed;
step 8, preparing a first gate oxide layer 10 and a second gate oxide layer 11:
(8a) Placing the SiC sample subjected to RCA cleaning into a high-temperature oxidation furnace, and adding N at 750 DEG C 2 Pushing the mixture into a constant temperature area of an oxidation furnace in the environment;
(8b) Heating the constant temperature area at a speed of 3 ℃/min;
(8c) Introducing oxygen when the temperature is increased to 1150 ℃, the flow rate of the oxygen is 0.5l/min, oxidizing the surface of the epitaxial wafer for 10 hours under the pure dry oxygen condition, and generating SiO with the thickness of 50nm on the front surface of the epitaxial wafer 2 And (3) an oxide film.
(8d) Shut off O 2 Ar is opened, and Ar gas is introduced for 15 minutes;
(8e) Heating the constant temperature area according to the speed of 3 ℃/min;
(8f) When the temperature rises to 1175 ℃, opening NO, and controlling the flow to 577sccm for 2 hours;
(8h) Turning off NO gas and reducing the furnace temperature to 900 ℃;
(8i) Closing Ar gas, and taking out a sample;
(8j) In the process of growing SiO in large area 2 Coating photoresist on the surface of the epitaxial wafer of the gate dielectric; photoresist is thrown, and then, the epitaxial wafer after the photoresist throwing is pre-baked at 80 ℃; the pre-baking time is 10-15 min;
(8k) Exposing the epitaxial wafer after the pre-baking by using a gate oxide photoetching plate;
(8 l) developing in a positive developing solution at a solution temperature of 20 ℃ for 85s;
(8 m) hardening the developed epitaxial wafer in ultrapure water at the water temperature of 20 ℃ for 85s;
(8 n) removing the exposed photoresist in a plasma photoresist remover, and then immersing the photoresist-removed epitaxial wafer in acetone for 5 hours and using acetone for ultrasonic treatment for 1 minute to expose the effective gate region.
Step 9, manufacturing a drain electrode N + Zone 1, N + /P + Region 2, source electrode first N + Region 3, drain electrode second N + Region 4 and drain electrode P + Contact electrode 15 of zone 5, see e-plot in fig. 3):
(9a) Coating stripping adhesive and throwing adhesive on the surface of the epitaxial wafer subjected to high-temperature annealing;
(9b) Coating photoresist and spin coating on the surface of the epitaxial wafer coated with the stripping adhesive, and then pre-baking the spin coated epitaxial wafer sample at 80 ℃; the pre-baking time is 10-15 min;
(9c) Exposing the epitaxial wafer after the pre-baking by using an ohmic contact photoetching plate;
(9d) Developing in positive developing solution at 20 deg.c for 85s;
(9e) Hardening the developed epitaxial wafer in ultrapure water at the water temperature of 20 ℃ for 85s;
(9f) Removing the exposed photoresist in a plasma photoresist remover to expose the effective source drain region and the P-type ohmic contact region;
(9g) Soaking the epitaxial wafer with the photoresist removed in acetone for 5 hours, performing ultrasonic treatment by using the acetone for 1 minute, then cleaning the epitaxial wafer with acetone and alcohol for one time, and removing the stripping adhesive of the source-drain ohmic contact area and the P-type ohmic contact area; exposing the active contact area;
(9h) Placing the photoresist-removed epitaxial wafer into an electron beam evaporation chamber, evaporating three metals Al/Ni/Au in a large area to form ohmic contact electrodes, wherein the thicknesses of the ohmic contact electrodes are respectively 150nm, 50nm and 70nm, and then realizing ohmic contact patterns by using a stripping method;
(9i) Finally, placing the epitaxial wafer with the source electrode in an annealing furnace to perform alloy annealing for 30 minutes at 950 ℃;
step 10, preparation of gate electrode 14 (see f-chart in fig. 3):
(10a) Coating stripping photoresist and photoresist on the front surface of the SiC sample subjected to ohmic electrode annealing, throwing the photoresist, and then pre-baking the epitaxial wafer subjected to the throwing at 80 ℃; the pre-baking time is 10-15 min;
(10b) Etching a gate pattern by using a gate electrode photoetching plate;
(10c) Developing in positive developing solution at 20 deg.c for 85s;
(10d) Hardening the developed epitaxial wafer in ultrapure water at the water temperature of 20 ℃ for 85s;
(10e) Removing the exposed photoresist in a plasma photoresist remover, and then cleaning by using deionized water;
(10f) Soaking the epitaxial wafer with the photoresist removed in acetone for 5 hours, carrying out ultrasonic treatment on the epitaxial wafer for 1 minute by using the acetone, then washing the epitaxial wafer with the acetone and alcohol for one time, and removing the stripping adhesive in the gate electrode area; exposing the active contact area;
(10g) Placing the epitaxial wafer from which the photoresist and the stripping adhesive are removed into an electron beam evaporation chamber, and evaporating Ti/Au in a large area, wherein the thickness is 50nm/200nm;
(10 m) the final gate electrode 14 was formed by a lift-off method.
Step 11, manufacturing the first interconnect electrode 12 and the second interconnect electrode 13 the interconnect electrode 14 (see g-diagram in fig. 3):
(11a) Coating stripping adhesive and throwing adhesive on the surface of the epitaxial wafer deposited with the gate metal; coating photoresist, spin coating, and then pre-baking the spin coated epitaxial wafer at 80 ℃; the pre-baking time is 10-15 min;
(11b) Exposing the epitaxial wafer after the pre-baking by using the interconnection contact plate;
(11c) Developing in positive developing solution at 20 deg.c for 85s;
(11d) Hardening the developed epitaxial wafer in ultrapure water at the water temperature of 20 ℃ for 85s;
(11e) Removing the exposed photoresist in a plasma photoresist remover, soaking the epitaxial wafer after photoresist removal in acetone for 5 hours, carrying out ultrasonic treatment by using the acetone for 1 minute, then cleaning the epitaxial wafer by using the acetone and alcohol for one time, and removing the stripping photoresist in the contact interconnection area; exposing the active contact area;
(11f) Placing the epitaxial wafer from which the photoresist and the stripping adhesive are removed into an electron beam evaporation chamber, and evaporating Ti/Au in a large area, wherein the thickness is 50nm/200nm;
(11g) The final electrode contact is formed by a lift-off process.
Example 2 of the preparation method:
in the embodiment, after the step 6 in the embodiment 1, a sacrificial oxidation step is added before the step 7, so that the interface damage caused by high-temperature ion implantation annealing can be reduced more effectively, and the interface flatness can be improved effectively. While the remaining steps will be exactly the same as in case 1.
The sacrificial oxidation of this embodiment is accomplished as follows:
(1) Placing the epitaxial wafer subjected to high-temperature annealing into a high-temperature oxidation furnace, oxidizing the surface of the epitaxial wafer at 1200 ℃ under the pure dry oxygen condition for 30min, and generating SiO with the thickness of 20nm on the front surface of the epitaxial wafer 2 An oxide film;
(2) And (3) placing the epitaxial wafer after the SiO2 oxide film grows into HF acid, and cleaning the oxide layer on the surface.
Claims (10)
1. An SiC MOS device capable of improving the back flushing characteristic of an ESD protection loop comprises an N-type SiC substrate (9), wherein an N-type SiC epitaxial region (8) is arranged on the SiC substrate (9) to form an epitaxial wafer, and the SiC MOS device is characterized in that a source P-type region (6) and a drain P-type region (7) which are mutually spaced are arranged on the SiC epitaxial region (8), a first nMOSFET (MN 1) is arranged on the drain P-type region (7), and a second nMOSFET (MN 2) is arranged on the source P-type region (6);
the first nMOSFET (MN 1) comprises: a drain N arranged on the source P-type region (6) + Zone (1) and N + /P + Region (2) at the drain N + Regions (1) and N + /P + A first gate oxide layer (10) is arranged between the regions (2), and a drain electrode N is arranged on the first gate oxide layer + Zone (1) and N + /P + Contact electrodes are respectively arranged on the upper surfaces of the areas (2); a gate electrode is provided on the first gate oxide layer (10);
the second nMOSFET (MN 2) comprises: sequentially arranged source electrodes of first N + Region (3), source electrode second N + Region (4) and source electrode P + A region (5) at the source electrode of the first N + Region (3) and source electrode second N + A second gate oxide layer (11) is arranged between the regions (4), a first N is arranged at the source electrode + Region (3), source electrode second N + Region (4) and source electrode P + Contact electrodes are respectively arranged on the upper surfaces of the areas (5); a gate electrode is provided on the second gate oxide layer (11);
at the drain electrode N + A drain lead (D) is arranged on the contact electrode above the region (1);
a gate electrode on the first gate oxide layer (10) and a first N of the source electrode + The contact electrodes above the region (3) are interconnected by a first interconnection electrode (12) and provided withA gate lead (G);
said N + /P + Region (2), source electrode second N + Region (4) and source electrode P + The contact electrode above the region (5) and the gate electrode above the second gate oxide layer (11) are interconnected by a second interconnect electrode (13) and provided with a source lead-out wire (S).
2. The SiC MOS device capable of improving ESD protection loop back flushing characteristics of claim 1, wherein said SiC epitaxial region (8) has a concentration of 5e+15cm -3 The concentration of the N-type SiC substrate (9) is 5e+18cm -3 。
3. A method of fabricating a SiC MOS device capable of improving the ESD protection loop backwash characteristics of claim 1 comprising the steps of:
step A1, cleaning the surface of an epitaxial wafer: carrying out standard wet process cleaning on the surface of the epitaxial wafer;
step A2, manufacturing a source electrode P type region (6) and a drain electrode P type region (7): coating photoresist on the surface of a SiC epitaxial region (8) of the epitaxial wafer with the surface cleaned, etching high-temperature ion implantation regions of a source electrode P-type region (6) and a drain electrode P-type region (7), and then carrying out high-temperature Al ion implantation;
step A3, drain electrode N + Region (1), source electrode first N + Region (3) and source second N + High-temperature nitrogen ion implantation of the region (4), after P-BODY region high-temperature ion implantation, etching N+ doped source and drain regions, and then performing N+ source and drain region high-temperature N ion implantation;
step A4, source electrode P + Zone (5) and N + /P + Formation of P-type ion implantation of region (2): after ion implantation of N+ source and drain regions, etching a P-type doped contact region, and then carrying out P-type doped high-temperature Al ion implantation;
step A5, forming a surface carbon protective film: after P-type ion implantation, forming a carbon protective film on the surface of the SiC epitaxial layer;
step A6, high-temperature ion implantation activation: carrying out 1600 ℃ high-temperature ion implantation annealing on a sample with a carbon protective film formed on the surface of the SiC epitaxial layer;
step A7, removing the carbon film on the surface: removing a carbon film on the surface of the SiC sample after the high-temperature ion implantation annealing;
step A8, preparing a first gate oxide layer (10) and a second gate oxide layer (11): performing HF acid cleaning on the SiC sample with the carbon film removed, and then performing SiO 2 Growing a gate dielectric layer;
step A9, drain N+ region (1), N+/P+ region (2), source first N + Region (3), source electrode second N + Region (4) and source electrode P + Formation of contact electrode of zone (5): after the growth of the gate dielectric layer is finished, coating stripping glue and photoresist on the surface of the sample, etching an ohmic contact hole, carrying out ohmic contact metal deposition, stripping to form an ohmic contact pattern, and carrying out ohmic contact annealing;
step A10, forming a gate electrode: forming a gate electrode on the SiC sample subjected to the ohmic contact electrode annealing;
step A11, forming an interconnection electrode: and (3) coating stripping glue and photoresist on the surface of the SiC sample for forming the gate electrode, etching a gate and a source contact hole, depositing a gate, a source drain and a P-type ohmic contact region, and stripping to form interconnection patterns of the gate, the source drain and the P-type ohmic contact region.
4. The method according to claim 3, wherein the step A2 is performed as follows,
a21, placing the N-/N+ type SiC epitaxial wafer sample with the surface cleaned into PECVD, and depositing SiO 2 A layer having a thickness of 60nm;
a22 SiO is deposited 2 Coating photoresist on the surface of the SiC sample, and photoetching a P-BODY region; the unprotected SiO of the photoresist is then treated in an HF acid solution 2 The layer is cleaned to expose the high-temperature ion implantation area of the P-BODY area;
a23 placing SiC sample exposing the source electrode P type region (6) and drain electrode P type region (7) into a high temperature ion implanter, and performing high temperature phosphorus ion implantation at 400deg.C for four times to form P-BODY region with depth of 0.7 μm and concentration of 5×10 18 cm -3 ；
A24, cleaning the sample subjected to high-temperature ion implantation in HF solution to remove SiO on the surface 2 A barrier layer.
5. The method according to claim 3, wherein the specific process of step A3 is as follows:
a31 will remove surface SiO 2 Placing the SiC sample of the barrier layer into PECVD, and depositing SiO 2 A layer having a thickness of 60nm;
a32 SiO is deposited 2 Coating photoresist and spin coating on the surface of the SiC sample, and photoetching a source injection region; the unprotected SiO of the photoresist is then treated in an HF acid solution 2 The layer is cleaned off, and the source injection region is exposed;
a33 placing SiC sample with exposed source electrode P type region (6) and drain electrode P type region (7) into high temperature ion implanter, and performing high temperature nitrogen ion implantation at 400deg.C four times to form junction depth of 0.3 μm and concentration of 3×10 19 cm -3 ；
A34, cleaning the sample subjected to high-temperature ion implantation in an HF acid solution to remove SiO on the surface 2 A barrier layer.
6. The method according to claim 3, wherein the specific process of step A4 is as follows:
a41 will remove the surface SiO 2 Placing the SiC sample of the barrier layer into PECVD, and depositing SiO 2 A layer having a thickness of 60nm;
a42 SiO is deposited 2 Coating photoresist and spin coating on the surface of the SiC sample, and photoetching a P-type injection region; the unprotected SiO of the photoresist is then treated in an HF acid solution 2 The layer is cleaned off, and the P-type injection region is exposed;
a43 will expose source P + Placing SiC samples of the region (5) and the drain electrode P-type region (2) into a high-temperature ion implanter, and carrying out high-temperature aluminum ion implantation four times at 400 ℃ to form a concentration of 1.5 multiplied by 10 19 cm -3 Depth 0.2 μm;
a44 is used for dissolving the sample subjected to high-temperature ion implantation in HF acidCleaning in liquid to remove SiO on surface 2 A barrier layer.
7. The method according to claim 3, wherein the specific process of step A5 is as follows:
a51 SiO removal from the surface 2 Coating photoresist on the surface of the SiC epitaxial wafer sample of the barrier layer, throwing the SiC epitaxial wafer sample into an oven, and pre-baking the SiC epitaxial wafer sample for 1 minute at 90 ℃;
a52, placing the pre-baked SiC sample into a high-temperature annealing furnace, and keeping the temperature at 600 ℃ for 30 minutes for carbonization;
a53 cooling the carbonized SiC sample.
8. The manufacturing method according to claim 7, wherein the specific process of step A6 is as follows:
a61 placing the sample carbonized on the SiC surface in a high-temperature annealing furnace, placing the surface with the carbon film downwards, vacuumizing to 10 -7 Torr, filling Ar gas, gradually heating to 1600 ℃, staying at 1600 ℃ for 30 minutes, and carrying out high-temperature ion implantation annealing;
a62, cooling the high-temperature ion implantation annealing furnace loaded with the sample to normal temperature, and taking the SiC sample out of the high-temperature annealing furnace.
9. The method according to claim 3, wherein the specific process of step A7 is as follows:
a71 placing the SiC sample subjected to high-temperature ion implantation annealing into an RIE reaction chamber, turning on a valve of the reaction chamber and opening N, wherein the surface with the carbon film faces upwards 2 Valve to 1/4, let in N 2 60 seconds, then the nitrogen valve was turned off;
A72N for 60 seconds on SiC sample with carbon film 2 After flushing, the oil pump is opened, the oil pump valve is completely opened until the oil pump sound becomes loud and becomes stable, and the pump is stable for 20-30 minutes;
a73, opening an oxygen valve until the pressure in the chamber reaches 9-12mT;
a74, opening a cooling system, and adjusting the oxygen flow to 47sccm;
a75, opening a radio frequency network adapter, and removing the carbon film on the surface of the SiC sample for 90 minutes;
a76 turns off the power supply of the network adapter and O 2 ；
A77 depressurizing the system to normal pressure, turning off the cooling system, and filling N into the RIE reaction chamber 2 Until the reaction chamber door can be opened, the sample is taken.
10. The method according to claim 3, wherein the specific process of step A8 is as follows:
a81, performing HF acid cleaning on the SiC sample from which the surface carbon film is removed;
a82 placing the SiC sample subjected to HF acid cleaning into a high-temperature oxidation furnace, introducing pure oxygen at 1180 ℃, oxidizing the front surface of the SiC epitaxial wafer for 10 hours under the dry oxygen condition to generate SiO with the thickness of 50nm 2 An oxide film;
a83 nitriding the grown oxide film: for grown SiO 2 The oxide film was subjected to NO annealing at 1175 ℃ for 2 hours;
a84, forming a gate dielectric pattern by using the gate dielectric plate;
the step A9 adopts two metals of Ni/Au with the concentration of 20nm/240nm as source and drain and P-type ohmic contact metal; the specific process is as follows:
a91, coating stripping photoresist and photoetching on the front surface of the SiC sample manufactured by the gate dielectric layer, cleaning the photoresist and the stripping photoresist to expose the effective source drain and the P-type ohmic contact area;
a92 Placing the SiC sample into an electron beam evaporation chamber;
a93 evaporating Ni/Au with the thickness of 20nm/240nm on the front surface of the SiC sample to serve as source drain and P-type ohmic contact metal;
a94 stripping to form a source drain and a P-type ohmic contact metal pattern;
a95, placing the SiC sample subjected to source and drain and the P-type ohmic contact electrode in an annealing furnace, and carrying out alloy annealing for 30 minutes at 950 ℃;
the step A10 adopts two metals of Ni/Au with the wavelength of 20nm/240nm as gate metals; the specific process is as follows:
a101, coating stripping adhesive and spin coating adhesive on the surface of the SiC sample subjected to source-drain and P-type ohmic contact;
a102, coating photoresist on the surface of the SiC sample coated with the stripping photoresist, throwing photoresist, and photoetching a gate metal area by using a gate plate;
a103, evaporating Ni/Au with the thickness of 20nm/240nm on the surface of the SiC sample with the etched gate contact holes as gate contact metal;
a104, forming a gate pattern by using a stripping method;
the step A11 is that the manufacture of the interconnection electrode adopts Ti/Au two metals, and the thickness is 50nm/200nm respectively; the method comprises the following steps:
a111, coating stripping adhesive and photoresist on the surface of the SiC sample after the gate metal is manufactured;
a112, etching a grid, a source, a drain and a P-type ohmic contact electrode interconnection window by utilizing interconnection photoetching;
a113 evaporating Ti/Au with the thickness of 30nm/200nm on the surface of the SiC sample on which the grid, the source, the drain and the P-type ohmic contact holes are carved to be used as grid, source, drain and P-type ohmic contact metals;
a114 forms gate, source, drain and P-type ohmic contact interconnection patterns using a lift-off method.
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| US5960290A (en) * | 1998-10-29 | 1999-09-28 | United Microelectronics Corp. | Method for fabricating a protection circuit of electrostatic discharge on a field device |
| CN110473911A (en) * | 2019-09-06 | 2019-11-19 | 芜湖启迪半导体有限公司 | A kind of SiC MOSFET element and preparation method thereof |
| CN111900160A (en) * | 2020-08-26 | 2020-11-06 | 璨隆科技发展有限公司 | Electrostatic discharge protection circuit of power device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5960290A (en) * | 1998-10-29 | 1999-09-28 | United Microelectronics Corp. | Method for fabricating a protection circuit of electrostatic discharge on a field device |
| CN110473911A (en) * | 2019-09-06 | 2019-11-19 | 芜湖启迪半导体有限公司 | A kind of SiC MOSFET element and preparation method thereof |
| CN111900160A (en) * | 2020-08-26 | 2020-11-06 | 璨隆科技发展有限公司 | Electrostatic discharge protection circuit of power device |
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