CN113299641A - SiC MOS device capable of improving ESD protection loop back-flushing characteristic - Google Patents

SiC MOS device capable of improving ESD protection loop back-flushing characteristic Download PDF

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CN113299641A
CN113299641A CN202110563716.2A CN202110563716A CN113299641A CN 113299641 A CN113299641 A CN 113299641A CN 202110563716 A CN202110563716 A CN 202110563716A CN 113299641 A CN113299641 A CN 113299641A
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sic
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CN113299641B (en
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刘莉
常帅军
王梓名
马海伦
钟铭浩
郭建飞
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Power Engineering (AREA)
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  • General Physics & Mathematics (AREA)
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Abstract

The invention discloses a SiCMOS device capable of improving the recoil characteristic of an ESD protection loop, which comprises an N-type SiC substrate (9), wherein an N-type SiC epitaxial region (8) is arranged on the SiC substrate (9) to form an epitaxial wafer, and the SiCMOS device is characterized in that a source P-type region (6) and a drain P-type region (7) which are mutually separated are arranged on the SiC epitaxial region (8), a first nMOSFET (MN1) is arranged on the drain P-type region (7), and a second nMOSFET (MN2) is arranged on the source P-type region (6). The device with the structure can improve the back-flushing characteristic of an ESD protection circuit of a high-voltage SiCMOS device.

Description

SiC MOS device capable of improving ESD protection loop back-flushing characteristic
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a structure and a manufacturing method of a SiC MOS device capable of improving the recoil characteristic of an ESD (electro-static discharge) protection circuit, so as to reduce the trigger voltage of the device under the action of ESD and have high holding voltage.
Background
SiC has unique physical, chemical and electrical properties, and is a semiconductor material with great development potential in extreme application fields such as high temperature, high frequency, high power, radiation resistance and the like. ESD is an important reliability topic and can generate overvoltage and overcurrent in a circuit, which leads to thermal damage of a gate oxide failure device. ESD in silicon has been studied much, but SiC has been studied only a limited amount. Currently, internationally, SKyoung-II proposes a SiC gate floating NMOS device with low on-resistance, low trigger voltage and high temperature stability. Denis studied SiC junction barrier schottky diodes under ESD HBM stress in order to emphasize the limitations of SiC devices and processes. T.P, etc. research the failure mechanism of three types of transistors, and the work of MOS devices under ESD stress is researched by using methods such as PE and SPE, etc. The 15V sicnmoesd device characteristics were previously reported to study ESD robustness and protection. But ESD protection for SiC power devices remains only documented. It is well known that SiC materials have about 10 times the critical electric field, Ec 2.4MV/cm and Si 0.25MV/cm, and that Si materials have about 3 times the built-in potential of the pn junction about 3.4V at 300K, so this material characteristic results in a large difference between the trigger and holding voltages and has a strong kickback effect, which is very disadvantageous for optimizing the ESD design and protecting the IC core.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a SiC MOS device capable of improving the back-flushing characteristic of an ESD protection loop so as to improve the trigger voltage of the device under the action of ESD and have high holding voltage.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a SiC MOS device capable of improving the recoil characteristic of an ESD protection loop comprises an N-type SiC substrate (9), an N-type SiC epitaxial region (8) is arranged on the SiC substrate (9) to form an epitaxial wafer, and is characterized in that a source P-type region (6) and a drain P-type region (7) which are mutually separated are arranged on the SiC epitaxial region (8), a first nMOSFET (MN1) is arranged on the drain P-type region (7), and a second nMOSFET (MN2) is arranged on the source P-type region (6);
the first nMOSFET (MN1) comprises: a drain N + region (1) and an N +/P + region (2) which are arranged on the source P-type region (6), wherein a first grid oxide layer (10) is arranged on the upper surface between the drain N + region (1) and the N +/P + region (2), and contact electrodes are respectively arranged on the drain N + region (1) and the N +/P + region (2); a gate electrode is arranged on the first gate oxide layer (10);
the second nMOSFET (MN2) comprises: the transistor comprises a source electrode first N + region (3), a source electrode second N + region (4) and a source electrode P + region (5) which are sequentially arranged, wherein a second grid oxide layer (11) is arranged on the upper surface between the source electrode first N + region (3) and the source electrode second N + region (4), and contact electrodes are respectively arranged on the source electrode first N + region (3), the source electrode second N + region (4) and the source electrode P + region (5); a gate electrode is arranged on the second gate oxide layer (11);
a drain lead (D) is arranged on the contact electrode above the drain N + region (1);
the gate electrode on the first gate oxide layer (10) and the contact electrode on the first N + region (3) of the source are interconnected through a first interconnection electrode (12), and a gate lead-out wire (G) is arranged;
and the contact electrodes on the N +/P + region (2), the second source N + region (4) and the P + source region (5) and the gate electrode on the second gate oxide layer (11) are all interconnected through a second interconnection electrode (13) and are provided with a source lead-out wire (S).
The SiC epitaxial region (8) has the concentration of 5e +15cm < -3 >, and the N-type SiC substrate (9) has the concentration of 5e +18cm < -3 >.
The method for manufacturing the SiC MOS device capable of improving the back-flushing characteristic of the ESD protection loop is characterized by comprising the following steps of:
step 1, epitaxial wafer surface cleaning: cleaning the surface of the epitaxial wafer by a standard wet process;
step 2, manufacturing a source electrode P-type region (6) and a drain electrode P-type region (7): coating photoresist on the surface of the SiC epitaxial region (8) of the epitaxial wafer with the cleaned surface, etching high-temperature ion implantation regions of a source electrode P-type region (6) and a drain electrode P-type region (7), and then performing high-temperature Al ion implantation;
step 3, injecting high-temperature nitrogen ions into the drain electrode N + region (1), the source electrode first N + region (3) and the source electrode second N + region (4), etching an N + doped source region and a drain region after the high-temperature ions of the P-BODY region are injected, and then injecting the high-temperature N ions into the N + source region and the drain region;
and 4, forming P-type ion implantation of the source P + region (5) and the N +/P + region (2): after N + source and drain region ion implantation, etching a P-type doped contact region, and then performing P-type doped high-temperature Al ion implantation;
and 5, forming a surface carbon protective film: forming a carbon protective film on the surface of the SiC epitaxial layer after the P-type ion implantation;
and 6, high-temperature ion implantation activation: carrying out 1600 ℃ high-temperature ion implantation annealing on the sample with the carbon protective film formed on the surface of the SiC epitaxial layer;
and 7, removing the surface carbon film: removing a surface carbon film of the SiC sample subjected to high-temperature ion implantation annealing;
step 8, preparing a first grid oxide layer (10) and a second grid oxide layer (11): carrying out large-area HF acid cleaning on the SiC sample without the surface carbon film, and then growing a SiO2 gate dielectric layer;
step 9, forming contact electrodes of a drain electrode N + region (1), an N +/P + region (2), a source electrode first N + region (3), a source electrode second N + region (4) and a source electrode P + region (5): after the growth of the gate dielectric layer is finished, coating a stripping glue and a photoresist on the surface of a sample, etching an ohmic contact hole, carrying out ohmic contact metal deposition, stripping to form an ohmic contact pattern, and carrying out ohmic contact annealing;
step 10, forming a gate electrode: forming a gate electrode on the SiC sample subjected to the ohmic contact electrode annealing;
step 11, formation of interconnection electrodes: and coating a stripping glue and a photoresist on the surface of the SiC sample for forming the gate electrode, etching a gate contact hole and a source contact hole, depositing a gate, source drain contact and P-type ohmic contact region, and stripping to form an interconnection pattern of the gate, source drain contact and P-type ohmic contact region.
The specific process of the step a2 is as follows,
a21, putting the N-/N + type SiC epitaxial wafer sample with the cleaned surface into PECVD, and depositing a SiO2 layer with the thickness of 60nm in a large area;
a22 coating photoresist on the surface of the SiC sample deposited with SiO2 and photoetching a P-BODY region; then cleaning the SiO2 layer which is not protected by the photoresist in HF acid solution to expose the high-temperature ion injection area of the P-BODY area;
a23, putting the SiC sample with the exposed source P-type region (6) and drain P-type region (7) into a high-temperature ion implanter, and performing high-temperature phosphorus ion implantation at 400 ℃ for four times to form a P-BODY region with the depth of about 0.7 mu m and the concentration of 5 multiplied by 1018cm < -3 >;
a24, cleaning the sample subjected to high-temperature ion implantation in HF solution to remove the SiO2 barrier layer on the surface;
the specific process of the step A3 is as follows:
a31, putting the SiC sample with the SiO2 barrier layer on the surface removed into PECVD, and depositing a SiO2 layer in a large area with the thickness of 60 nm;
a32 coating photoresist on the surface of the SiC sample deposited with SiO2, spin coating the photoresist, and photoetching a source injection region; then cleaning the SiO2 layer without the protection of the photoresist in HF acid solution to expose a source injection area;
a33, putting the SiC sample with the source electrode P-type region (6) and the drain electrode P-type region (7) exposed into a high-temperature ion implanter, and performing high-temperature nitrogen ion implantation at 400 ℃ for four times to form a junction with the depth of 0.3 mu m and the concentration of about 3 multiplied by 1019cm < -3 >;
a34 the sample after high-temperature ion implantation is cleaned in HF acid solution to remove the SiO2 barrier layer on the surface.
The specific process of the step A4 is as follows:
a41, putting the SiC sample with the SiO2 barrier layer on the surface removed into PECVD, and depositing a SiO2 layer in a large area with the thickness of 60 nm;
a42 coating photoresist and spin coating on the surface of the SiC sample deposited with SiO2, and photoetching a P-type injection region; then cleaning the SiO2 layer without the protection of the photoresist in HF acid solution to expose a P-type injection region;
a43 placing the SiC sample with the source P + region (5) and the drain P-type region (2) exposed into a high-temperature ion implanter, and performing high-temperature aluminum ion implantation at 400 ℃ for four times to form a SiC sample with a concentration of about 1.5X 1019cm-3 and a depth of about 0.2 μm;
a44 the sample after high-temperature ion implantation is cleaned in HF acid solution to remove the SiO2 barrier layer on the surface.
The specific process of the step A5 is as follows:
a51 coating photoresist on the surface of the SiC epitaxial wafer sample with the SiO2 barrier layer removed, spin coating, and placing in an oven for pre-baking for 1 minute at 90 ℃;
a52, putting the pre-baked SiC sample into a high-temperature annealing furnace, keeping the temperature at 600 ℃ for 30 minutes, and carbonizing;
a53 is to cool the SiC sample that has undergone carbonization.
The specific process of the step A6 is as follows:
a61 placing the sample with carbonized SiC surface in a high temperature annealing furnace, vacuumizing the surface with carbon film to 10-7Torr, charging Ar gas, gradually heating to 1600 ℃, staying at 1600 ℃ for 30 minutes, and carrying out high temperature ion implantation annealing;
a62, cooling the high-temperature ion implantation annealing furnace loaded with the sample to normal temperature, and taking the SiC sample out of the high-temperature annealing furnace.
The specific process of the step A7 is as follows:
a71, putting the SiC sample subjected to high-temperature ion implantation annealing into an RIE reaction chamber, turning off a valve of the reaction chamber, opening N2 to 1/4, introducing N for 260 seconds, and then turning off a nitrogen valve, wherein the surface with the carbon film faces upwards;
after a 72N 2 flushing for 60 seconds on SiC samples with carbon film, the oil pump was turned on, the oil pump valve was fully opened until the sound of the oil pump became loud and stable, and the pump was stable for 20-30 minutes;
a73 opening the oxygen valve until the pressure inside the chamber reaches 9-12 mT;
a74 opening a cooling system, and adjusting the oxygen flow to 47 sccm;
a75, opening the radio frequency network adapter, timing for 90 minutes, and removing the carbon film on the surface of the SiC sample;
a76 turns off the network adapter power supply and O2;
a77 depressurizes the system to atmospheric pressure, turns off the cooling system, fills the RIE chamber with N2 until the chamber door can be opened, and removes the sample.
The specific process of the step A8 is as follows:
a81, performing HF acid cleaning on the SiC sample with the surface carbon film removed;
a82, putting the SiC sample subjected to HF acid cleaning into a high-temperature oxidation furnace, introducing pure oxygen at 1180 ℃, and oxidizing the front side of the SiC epitaxial wafer for 10 hours under the dry oxygen condition to generate a SiO2 oxide film with the thickness of 50 nm;
a83 nitriding the grown oxide film: carrying out NO annealing on the grown SiO2 oxide film at 1175 ℃ for 2 hours;
a84 uses a gate dielectric plate to form a gate dielectric pattern.
In the step A9, two metals of Ni/Au with the thickness of 20nm/240nm are used as source/drain and P-type ohmic contact metals; the specific process is as follows:
a91 coating a stripping glue and a photoresist on the front surface of the SiC sample subjected to gate dielectric layer manufacturing, photoetching, cleaning the photoresist and the stripping glue, and exposing effective source drain and P-type ohmic contact areas;
placing an A92SiC sample into an electron beam evaporation chamber;
a93 evaporating Ni/Au with the thickness of 20nm/240nm on the front surface of the SiC sample to be used as source drain and P-type ohmic contact metal;
a94 is stripped to form a source drain and P type ohmic contact metal pattern;
a95 SiC samples with source and drain and P-type ohmic contact electrodes were alloy annealed at 950 ℃ for 30 minutes in an annealing furnace.
In the step A10, two metals of Ni/Au with the thickness of 20nm/240nm are used as gate metals; the specific process is as follows:
a101, coating stripping glue on the surface of a SiC sample subjected to source drain and P-type ohmic contact, and spinning the glue;
a102, coating photoresist on the surface of the SiC sample coated with the stripping glue, spinning the photoresist, and photoetching a gate metal region by using a gate plate;
a103, evaporating Ni/Au with the thickness of 20nm/240nm on the surface of the SiC sample with the etched gate contact hole to be used as gate contact metal;
a104, forming a gate pattern by using a lift-off method.
In the step A11, two metals of Ti/Au are adopted for manufacturing the interconnection electrode, and the thicknesses of the two metals are respectively 50nm/200 nm; the method comprises the following steps:
a111 coating stripping glue and photoresist on the surface of the SiC sample with the manufactured gate metal;
a112, etching a grid, a source, a drain and a P-type ohmic contact electrode interconnection window by using an interconnection photoetching plate;
a113 evaporating Ti/Au with the thickness of 30nm/200nm on the surface of the SiC sample with the grid, source, drain and P-type ohmic contact holes as grid, source, drain and P-type ohmic contact metal;
a114, forming a grid, a source, a drain and a P-type ohmic contact interconnection pattern by using a stripping method.
Compared with the prior art, the invention has the following advantages: according to the invention, the traditional SiC MOS structure is improved, so that the trigger voltage of the device under the action of ESD is reduced, the high holding voltage is realized, and the back-flushing effect of an ESD protection circuit of the device can be effectively inhibited.
Drawings
FIG. 1 is a schematic diagram of the structure of the device of the present invention;
FIG. 2 is a schematic diagram of an equivalent circuit of the device of the present invention;
fig. 3 is a schematic flow chart of a method for manufacturing a device of the present invention, in which (a) to (g) are diagrams showing the contents of processes in respective steps (device sectional view), wherein: (a) the figure is the cleaned epitaxial wafer; (b) after the source P-type region 6 and the drain P-type region 7 are implanted; (c) the figure shows the completed drain N+Region 1, N+/P+Region 2, source first N+Region 3, drain second N+Region 4 and drain P+After ion implantation in region 5; (d) after the first gate oxide layer 10 and the second gate oxide layer 11 are completed; (e) the figure shows the completed drain N+Region 1, N+/P+Region 2, source first N+Region 3, drain second N+Region 4 and drain P+After contacting electrode 15 of region 5; (f) after the gate electrode is completed; (g) after the interconnection electrode is completed.
Description of reference numerals: 1. drain electrode N+Region, 2, N+/P+Region, 3, source first N+Region, 4, second N of source+Region, 5, source P+Region, 6, source P-type region, 7, drain P-type region, 8, SiC epitaxial region, 9, SiC substrate, 10, first gate oxide layer, 11, second gate oxide layer, 12, first interconnection electrode, 13, second interconnection electrode, 14, gate electrode, 15, contact electrode, D, drain lead, G, gate lead, S, source lead.
Detailed Description
Referring to fig. 1, the high-voltage SiC power MOS device capable of improving the ESD protection snapback effect of the present invention includes an N-type SiC substrate 9, an N-type SiC epitaxial region 8 is provided on the SiC substrate 9 to form an epitaxial wafer, and is characterized in that a source P-type region 6 and a drain P-type region 7 are provided on the SiC epitaxial region 8 at a distance from each other, a first nMOSFET, designated as MN1 (located in the left half of fig. 1), is provided on the drain P-type region 7, and a second nMOSFET, designated as MN2 (located in the right half of fig. 1) is provided on the source P-type region 6.
The first nMOSFET labeled MN1 includes: a drain N disposed on the source P-type region 6+ Region 1 and N+/P+Region 2 of the drain N+Region 1 and N+/P+A first gate oxide layer 10 is provided over the region 2, and a drain N is provided+ Region 1 and N+/P+Contact electrodes 15 are provided on the regions 2, respectively, and a gate electrode 14 is provided on the first gate oxide layer 10.
A second nmosfet MN2, labeled MN2, includes: sequentially arranged source electrodes N+Region 3, source second N+Region 4 and source P+Region 5 at the first N of the source+Region 3 and source second N+Between the regions 4, there is provided a second gate oxide layer 11 on top of which is a first N+Region 3, source electrodeTwo N+Region 4, source P+Contact electrodes 15 are provided on the upper side of the regions 5, and a further gate electrode 14 is provided on the upper side of the second gate oxide layer 11.
At the drain electrode N+A drain lead D is provided on the contact electrode 15 above the region 1.
A gate electrode 14 and a first N of the source on the first gate oxide layer 10+The contact electrodes 15 above the region 3 are interconnected by a first interconnection electrode 12 and provided with a gate lead-out G.
Said N+/P+Region 2, source second N+Region 4 and source P+The contact electrode 15 above the region 5, and the gate electrode above the second gate oxide layer (11) are interconnected by a second interconnection electrode 13, and provided with a source lead-out wire S.
The equivalent circuit of the above device of the present invention is shown in FIG. 2, in which the drain N of MN1+Region 1, N+/P+N of region 2+The region and the drain P-type region 7 form an NPN transistor QN1, the base of the transistor QN1 and N+/P+P of region 2+A resistance Rp is formed between the regions. Source first N of MN2 in device+Region 3 and source second N+One diode D1 and D2 are formed between the region 4 and the source P type region, and the anodes of two diodes D1 and D2 and the source P+The zones 5 correspond to interconnections. The gate of MN1 is connected to the drain region (drain N) of MN2 via the first interconnection electrode 12+Region 3), drain region (drain N) of MN1+Region 1) has a drain lead D connected to it, and most of the ESD current is discharged from the drain D to the source S of the device through an equivalent NPN transistor QN 1.
In the normal operation mode without electrostatic discharge, MN1 does not operate because of the high potential of the reverse junction, but when ESD (electrostatic discharge) occurs, the drain N+Avalanche breakdown occurs at the PN junction between region 1 and drain P-type region 7, and the resulting hole current drives transistor QN1 to discharge ESD current.
N of MN1+/P+Zone 2 with N+/P+The cross doping can effectively improve the generation of two parasitic bipolar transistors in the SCR structure which is conventionally usedEmitter implant effect. And the body and source regions in the SCR structure are in the hold state at the same time. N of MN1+/P+N of region 2+The region, the emitter region of QN1, becomes narrower, reducing the emitter injection efficiency of QN 1. The reduction in emitter injection efficiency increases the voltage drop of the device in the on-state, thereby increasing the holding voltage. And N is+/P+P of region 2+The reduction of the doping concentration of the region relative to the N + region limits the conduction of a longitudinal NPN parasitic transistor under the junction, increases the forward bias of QN1, promotes more current to flow from a QN1 tube to a source electrode, reduces the trigger voltage and plays a role in inhibiting ESD. The gate of MN1 is connected to the drain of MN2 for gate coupling, so that when MN1 discharges ESD current, the reverse junction of MN2 supports the voltage between the source second N + region 4 and the source P + region 5 to reduce the trigger voltage.
Referring to fig. 3, the process flow of the first embodiment of the method for manufacturing the device according to the present invention is as follows (the specific operations of the following steps of the process are all conventional):
step 1, surface cleaning is carried out on a 4H-SiC P-/N + type epitaxial wafer sample by adopting a standard cleaning method RCA (see a picture in figure 3).
And 2, manufacturing a source P-type region (6) and a drain P-type region (7) high-temperature ion implantation region on the epitaxial surface of the front surface of the epitaxial wafer sample (see a figure b).
(2a) Putting the cleaned epitaxial wafer into a P-BODY reaction chamber, and depositing SiO on the surface of the epitaxial wafer at 300 DEG C2A layer having a thickness of 60 nm;
(2b) on depositing SiO2Coating photoresist on the epitaxial wafer surface of the layer;
(2c) throwing photoresist, and then pre-baking the epitaxial wafer after throwing the photoresist at 90 ℃; the pre-drying time is 1 min;
(2d) injecting an N-WELL into a photoetching plate to expose the epitaxial wafer sample after the pre-baking;
(2e) developing in positive developing solution at 20 deg.C for 20 s;
(2f) hardening the developed epitaxial wafer in ultrapure water at the temperature of 20 ℃ for 20 s;
(2g) removing the exposed photoresist in a plasma photoresist remover to expose an effective N-WELL region;
(2h) the exposed SiO is then treated in HF acid solution2Cleaning off the layer;
(2i) will wash off SiO2Placing the epitaxial wafer of the layer into a high-temperature ion implantation chamber for P-BODY ion implantation, adjusting the temperature to 400 deg.C to form a P-BODY region with a depth of about 0.7 μm and a concentration of 5 × 1018cm-3；
(2j) The volume ratio of the injected sample is 1: rinsing with 10% mixed solution of HF (40% concentration) and water to remove SiO on the surface2A layer;
step 3, performing source drain region ion implantation on the source P-type region (6) and the drain P-type region (7) to form a drain N+Region 1, N+/P+Region 2, intermediate N+Region 3, source N+Zone 4 (see panel c in fig. 3):
(3a) placing the cleaned epitaxial wafer into a PECVD reaction chamber, and depositing SiO on the surface at 300 DEG C2A layer having a thickness of 60 nm;
(3b) on depositing SiO2Coating photoresist on the epitaxial wafer surface of the layer;
(3c) throwing photoresist, and then pre-baking the epitaxial wafer after throwing the photoresist at 90 ℃; the pre-drying time is 1 min;
(3d) exposing the epitaxial wafer sample after the pre-baking by using an N-source injection photoetching plate;
(3e) developing in positive developing solution at 20 deg.C for 20 s;
(3f) hardening the developed epitaxial wafer in ultrapure water at the temperature of 20 ℃ for 20 s;
(3g) removing the exposed photoresist in a plasma photoresist remover to expose an effective N-source region;
(3h) the exposed SiO is then treated in HF acid solution2Cleaning off the layer;
(3i) cleaning off SiO in the source/drain region2The epitaxial wafer of the layer is placed into a high-temperature ion implantation chamber for source N ion implantation, the temperature is adjusted to 400 ℃, high-temperature nitrogen ion implantation is carried out to form a junction depth of 0.3 mu m,the concentration is about 3X 1019cm-3。
(3j) The volume ratio of the injected sample is 1: rinsing with 10% mixed solution of HF (40% concentration) and water to remove SiO on the surface2A layer;
step 4, performing P-type region ion implantation N on the source P-type region (6) and the drain P-type region (7)+/P+Region 2, source P+Zone 5 (see panel c in fig. 3):
(4a) placing the cleaned epitaxial wafer into a PECVD reaction chamber, and depositing SiO on the surface at 300 DEG C2A layer having a thickness of 60 nm;
(4b) on depositing SiO2Coating photoresist on the epitaxial wafer surface of the layer;
(4c) throwing photoresist, and then pre-baking the epitaxial wafer after throwing the photoresist at 90 ℃; the pre-drying time is 1 min;
(4d) exposing the epitaxial wafer sample after the pre-baking by using a P-type injection photoetching plate;
(4e) developing in positive developing solution at 20 deg.C for 20 s;
(4f) hardening the developed epitaxial wafer in ultrapure water at the temperature of 20 ℃ for 20 s;
(4g) removing the exposed photoresist in a plasma photoresist remover to expose an effective P + region;
(4h) the exposed SiO is then treated in HF acid solution2Cleaning off the layer;
(4i) cleaning off SiO in the source/drain region2The epitaxial wafer of the layer is placed into a high-temperature ion implantation chamber for Al ion implantation in a source P-type region (6) and a drain P-type region (7), the temperature is adjusted to 400 ℃, and the concentration is formed to be about 1.5 multiplied by 1019cm-3And a depth of about 0.2 μm.
(4j) The volume ratio of the injected sample is 1: rinsing with 10% mixed solution of HF (40% concentration) and water to remove SiO on the surface2A layer;
the following steps 5-9 are a process flow for preparing the first gate oxide layer 10 and the second gate oxide layer 11 (see diagram d in fig. 3):
step 5, manufacturing a high-temperature ion implantation annealing carbon protective film on the front surface of the N-/N + epitaxial wafer sample:
(5a) in removing SiO from the surface2Coating photoresist on the surface of the SiC epitaxial wafer sample of the barrier layer;
(5b) spin coating, and placing the mixture into an oven to be pre-dried for 1 minute at the temperature of 90 ℃;
(5c) putting the pre-baked SiC sample into a high-temperature annealing furnace, wherein the carbon surface faces upwards;
(5d) vacuumizing for 2 hours, wherein the pressure reaches 4-5E-7 Torr;
(5e) filling Ar gas, and setting the output pressure to be 12 psi;
(5f) turning on the fan;
(5g) firstly, regulating the power of a power supply to 10%, then regulating the power of the power supply to 30% according to the speed of 5%/2 min, then finely regulating the power of the power supply to the temperature of 600 ℃ according to the power of 2%/2 min, and keeping the temperature at 600 ℃ for 30 minutes;
(5h) turning off a power adjusting knob of a heating power supply;
(5i) taking out the SiC sample with the carbon film;
step 6, high-temperature ion implantation annealing;
(6a) putting the SiC sample with the carbon protective film into a high-temperature annealing furnace, wherein the surface with the carbon surface faces downwards;
(6b) vacuumizing, wherein the pressure reaches 4-5E-7 Torr;
(6c) filling Ar gas, and setting the output pressure to be 12 psi;
(6d) turning on the fan;
(6e) firstly, adjusting the power of a power supply to 60%, then adjusting the temperature to 1600 ℃ according to the speed of 1%/10 s, and keeping the temperature at 1600 ℃ for 30 minutes;
(6f) turning off a power adjusting knob of a heating power supply;
(6i) taking out the SiC sample with the carbon film after high-temperature ion implantation annealing;
and 7, removing the carbon protective film on the front surface of the N-/N + SiC epitaxial sample:
(7a) charging N into RIE chamber2Opening the door of the RIE reaction chamber;
(7b) placing the sample in the center, enabling the surface with the carbon film to face upwards, pressing the sample by using tweezers, closing the reaction chamber door and then screwing the valve tightly;
(7c) start to communicate with2Flow rate 47 sccm;
(7d) turning on the radio frequency network adapter, and adjusting the power to 18 +/-3W;
(7e) timing for 90 minutes to remove the carbon film on the surface of the SiC sample;
(7f) turn off RF network adapter, turn off O2；
(7g) Charging N2Until the chamber door of the reaction chamber can be automatically opened, taking out the sample;
(7h) performing RCA cleaning on the SiC sample with the surface carbon film removed;
step 8, preparing a first gate oxide layer 10 and a second gate oxide layer 11:
(8a) putting the SiC sample subjected to RCA cleaning into a high-temperature oxidation furnace, and carrying out N treatment at the temperature of 750 DEG C2Pushing the mixture into a constant-temperature area of an oxidation furnace in the environment;
(8b) heating the constant temperature area at the speed of 3 ℃/min;
(8c) when the temperature rises to 1150 ℃, oxygen is introduced, the oxygen flow is 0.5l/min, the surface of the epitaxial wafer is oxidized for 10 hours under the pure dry oxygen condition, and SiO with the thickness of 50nm is generated on the front surface of the epitaxial wafer2And (5) oxidizing the film.
(8d) Turn off O2Opening Ar, and introducing Ar gas for 15 minutes;
(8e) heating the constant temperature area at the speed of 3 ℃/min;
(8f) when the temperature rises to 1175 ℃, opening NO, and controlling the flow rate to be 577sccm for 2 hours;
(8h) turning off NO gas, and reducing the furnace temperature to 900 ℃;
(8i) turning off Ar gas and taking out a sample;
(8j) in large area grown SiO2Coating photoresist on the surface of the epitaxial wafer of the gate dielectric; throwing photoresist, and then pre-baking the epitaxial wafer after throwing the photoresist at 80 ℃; the pre-drying time is 10-15 min;
(8k) exposing the epitaxial wafer after the pre-baking by using a gate oxide photoetching plate;
(8l) developing in a positive developing solution, wherein the solution temperature is 20 ℃, and the developing time is 85 s;
(8m) hardening the developed epitaxial wafer in ultrapure water at the temperature of 20 ℃ for 85 s;
(8n) removing the exposed photoresist in a plasma photoresist remover, and then soaking the epitaxial wafer with the photoresist removed in acetone for 5 hours and carrying out ultrasonic treatment by using the acetone for 1 minute to expose an effective grid region.
Step 9, manufacturing a drain N+Region 1, N+/P+Region 2, source first N+Region 3, drain second N+Region 4 and drain P+Contact electrode 15 of region 5, see e-diagram in fig. 3):
(9a) coating stripping glue on the surface of the epitaxial wafer subjected to high-temperature annealing, and spinning the glue;
(9b) coating photoresist on the surface of the epitaxial wafer coated with the stripping glue, spinning the photoresist, and then prebaking the epitaxial wafer sample subjected to spinning at 80 ℃; the pre-drying time is 10-15 min;
(9c) exposing the epitaxial wafer after the pre-baking by using an ohmic contact photoetching plate;
(9d) developing in positive developing solution at 20 deg.C for 85 s;
(9e) hardening the developed epitaxial wafer in ultrapure water at the temperature of 20 ℃ for 85 s;
(9f) removing the exposed photoresist in a plasma photoresist remover to expose an effective source drain region and a P-type ohmic contact region;
(9g) soaking the epitaxial wafer without the photoresist in acetone for 5 hours, carrying out ultrasonic treatment for 1 minute by using the acetone, then cleaning the epitaxial wafer with the acetone and the alcohol once respectively, and removing the stripping glue of a source drain ohmic contact area and a P-type ohmic contact area; exposing the effective contact area;
(9h) putting the epitaxial wafer without the glue into an electron beam evaporation chamber, evaporating three metals Al/Ni/Au in a large area to be used as ohmic contact electrodes, wherein the thicknesses of the ohmic contact electrodes are respectively 150nm, 50nm and 70nm, and then realizing an ohmic contact pattern by utilizing a stripping method;
(9i) finally, the epitaxial wafer which is used as the source electrode is placed in an annealing furnace to carry out alloy annealing for 30 minutes at 950 ℃;
step 10, preparation of the gate electrode 14 (see diagram f in fig. 3):
(10a) coating stripping glue and photoresist on the front surface of the SiC sample subjected to ohmic electrode annealing, throwing glue, and then pre-baking the epitaxial wafer after glue throwing at 80 ℃; the pre-drying time is 10-15 min;
(10b) etching a gate pattern by using a gate electrode photoetching plate;
(10c) developing in positive developing solution at 20 deg.C for 85 s;
(10d) hardening the developed epitaxial wafer in ultrapure water at the temperature of 20 ℃ for 85 s;
(10e) removing the exposed photoresist in a plasma photoresist remover, and then cleaning by using deionized water;
(10f) then soaking the epitaxial wafer without the photoresist in acetone for 5 hours, carrying out ultrasonic treatment for 1 minute by using the acetone, then cleaning the epitaxial wafer with acetone and alcohol once respectively, and removing the stripping glue in the gate electrode area; exposing the effective contact area;
(10g) placing the epitaxial wafer with the photoresist and the stripping glue removed into an electron beam evaporation chamber, and evaporating Ti/Au in a large area with the thickness of 50nm/200 nm;
(10m) the final gate electrode 14 is formed by a lift-off method.
Step 11, fabrication of the first interconnection electrode 12 and the second interconnection electrode 13, interconnection electrode 14 (see g diagram in fig. 3):
(11a) coating stripping glue and spin coating glue on the surface of the epitaxial wafer deposited with the gate metal; coating photoresist, spin-coating, and pre-baking the spin-coated epitaxial wafer at 80 ℃; the pre-drying time is 10-15 min;
(11b) exposing the epitaxial wafer after the pre-baking by using an interconnection contact plate;
(11c) developing in positive developing solution at 20 deg.C for 85 s;
(11d) hardening the developed epitaxial wafer in ultrapure water at the temperature of 20 ℃ for 85 s;
(11e) removing the exposed photoresist in a plasma photoresist remover, soaking the epitaxial wafer without the photoresist in acetone for 5 hours, carrying out ultrasonic treatment for 1 minute by using the acetone, and then cleaning the epitaxial wafer with acetone and alcohol once to remove the stripping glue in the contact interconnection area; exposing the effective contact area;
(11f) placing the epitaxial wafer with the photoresist and the stripping glue removed into an electron beam evaporation chamber, and evaporating Ti/Au in a large area with the thickness of 50nm/200 nm;
(11g) the final electrode contact is formed by a lift-off process.
Example 2 of the preparation method:
in the embodiment, a sacrificial oxidation process is added after the step 6 and before the step 7 in the embodiment 1, so that the interface damage caused by high-temperature ion implantation annealing can be more effectively reduced, and the interface flatness can be effectively improved. While the remaining steps will be exactly the same as in case 1.
The sacrificial oxidation implementation steps of this embodiment are as follows:
(1) placing the epitaxial wafer subjected to high temperature annealing into a high temperature oxidation furnace, oxidizing the surface of the epitaxial wafer for 30min at 1200 ℃ under the condition of pure dry oxygen, and generating SiO with the thickness of 20nm on the front surface of the epitaxial wafer2An oxide film;
(2) and (3) putting the epitaxial wafer on which the SiO2 oxide film grows into HF acid, and cleaning the oxide layer on the surface.

Claims (10)

1. A SiCMOS device capable of improving the back-flushing characteristic of an ESD protection loop comprises an N-type SiC substrate (9), an N-type SiC epitaxial region (8) is arranged on the SiC substrate (9) to form an epitaxial wafer, and is characterized in that a source P-type region (6) and a drain P-type region (7) which are mutually separated are arranged on the SiC epitaxial region (8), a first nMOSFET (MN1) is arranged on the drain P-type region (7), and a second nMOSFET (MN2) is arranged on the source P-type region (6);
the first nMOSFET (MN1) comprises: a drain N disposed above the source P-type region (6)+Region (1) and N+/P+A region (2) in the drain N+Region (1) and N+/P+A first gate oxide layer (2)10) At the drain electrode N+Region (1) and N+/P+Contact electrodes are respectively arranged on the upper surfaces of the regions (2); a gate electrode is arranged on the first gate oxide layer (10);
the second nMOSFET (MN2) comprises: sequentially arranged source electrodes N+Region (3), source second N+Region (4) and source P+A region (5) at the first N of the source+Region (3) and source second N+A second gate oxide layer (11) is provided over the regions (4) and over the source first N+Region (3), source second N+Region (4) and source P+Contact electrodes are respectively arranged on the upper surfaces of the regions (5); a gate electrode is arranged on the second gate oxide layer (11);
at the drain electrode N+A drain electrode lead (D) is arranged on the contact electrode above the region (1);
a gate electrode on the first gate oxide layer (10) and a first N of the source+The contact electrodes on the region (3) are interconnected through a first interconnection electrode (12) and provided with a grid lead-out wire (G);
said N+/P+Region (2), source second N+Region (4) and source P+The contact electrode above the region (5) and the gate electrode above the second gate oxide layer (11) are interconnected by a second interconnection electrode (13) and provided with a source lead-out wire (S).
2. SiCMOS device with improved ESD protection loop-back characteristics as claimed in claim 1, characterized in that the SiC epitaxial region (8) has a concentration of 5e +15cm-3The concentration of the N-type SiC substrate (9) is 5e +18cm-3。
3. A method for fabricating a SiCMOS device capable of improving a snapback characteristic of an ESD protection circuit as set forth in claim 1, comprising the steps of:
step 1, epitaxial wafer surface cleaning: cleaning the surface of the epitaxial wafer by a standard wet process;
step 2, manufacturing a source electrode P-type region (6) and a drain electrode P-type region (7): coating photoresist on the surface of the SiC epitaxial region (8) of the epitaxial wafer with the cleaned surface, etching high-temperature ion implantation regions of a source electrode P-type region (6) and a drain electrode P-type region (7), and then performing high-temperature Al ion implantation;
step 3, drain electrode N+Region (1), source first N+Region (3) and source second N+High-temperature nitrogen ion implantation of the region (4), after the high-temperature ion implantation of the P-BODY region is carried out, an N + doping source region and a drain region are carved out, and then the high-temperature N ion implantation of the N + source region and the drain region is carried out;
step 4, source P+Region (5) and N+/P+Formation of P-type ion implantation of region (2): after N + source and drain region ion implantation, etching a P-type doped contact region, and then performing P-type doped high-temperature Al ion implantation;
and 5, forming a surface carbon protective film: forming a carbon protective film on the surface of the SiC epitaxial layer after the P-type ion implantation;
and 6, high-temperature ion implantation activation: carrying out 1600 ℃ high-temperature ion implantation annealing on the sample with the carbon protective film formed on the surface of the SiC epitaxial layer;
and 7, removing the surface carbon film: removing a surface carbon film of the SiC sample subjected to high-temperature ion implantation annealing;
step 8, preparing a first grid oxide layer (10) and a second grid oxide layer (11): the SiC sample with the surface carbon film removed is subjected to large-area HF acid cleaning, and then SiO is carried out2Growing a gate dielectric layer;
step 9, drain electrode N + region (1), N +/P + region (2), first N of source electrode+Region (3), source second N+Region (4) and source P+Formation of the contact electrode of the region (5): after the growth of the gate dielectric layer is finished, coating a stripping glue and a photoresist on the surface of a sample, etching an ohmic contact hole, carrying out ohmic contact metal deposition, stripping to form an ohmic contact pattern, and carrying out ohmic contact annealing;
step 10, forming a gate electrode: forming a gate electrode on the SiC sample subjected to the ohmic contact electrode annealing;
step 11, formation of interconnection electrodes: and coating a stripping glue and a photoresist on the surface of the SiC sample for forming the gate electrode, etching a gate contact hole and a source contact hole, depositing a gate, source drain contact and P-type ohmic contact region, and stripping to form an interconnection pattern of the gate, source drain contact and P-type ohmic contact region.
4. The manufacturing method according to claim 3, wherein the step A2 is specifically performed as follows,
a21 the surface cleaned N-/N + type SiC epitaxial wafer sample is put into PECVD for large-area SiO deposition2A layer having a thickness of 60 nm;
a22 is formed by depositing SiO2Coating photoresist on the surface of the SiC sample, and photoetching a P-BODY region; then the SiO without the protection of the photoresist is put in HF acid solution2Cleaning the layer to expose the high-temperature ion implantation area of the P-BODY area;
a23 the SiC sample with the exposed source P-type region (6) and drain P-type region (7) was placed in a high temperature ion implanter and high temperature phosphorus ion implantation was carried out at 400 ℃ four times to form P-BODY regions with a depth of about 0.7 μm and a concentration of 5X 1018cm-3；
A24 cleaning the sample after high-temperature ion implantation in HF solution to remove SiO on the surface2And a barrier layer.
5. The manufacturing method according to claim 3, wherein the step A3 comprises the following steps:
a31 will remove surface SiO2Placing the SiC sample of the barrier layer into PECVD, and depositing SiO in a large area2A layer having a thickness of 60 nm;
a32 is formed by depositing SiO2Coating photoresist on the surface of the SiC sample, spin coating the photoresist, and photoetching a source injection region; then the SiO without the protection of the photoresist is put in HF acid solution2Cleaning the layer to expose the source injection region;
A33A SiC sample with the exposed source P-type region (6) and drain P-type region (7) was placed in a high temperature ion implanter and high temperature nitrogen ion implantation was carried out at 400 ℃ in four times to form a junction having a depth of 0.3 μm and a concentration of approximately 3X 1019cm-3；
A34 pair was subjected to high-temperature ion implantationCleaning the sample in HF acid solution to remove SiO on the surface2And a barrier layer.
6. The manufacturing method according to claim 3, wherein the step A4 comprises the following steps:
a41 will remove surface SiO2Placing the SiC sample of the barrier layer into PECVD, and depositing SiO in a large area2A layer having a thickness of 60 nm;
a42 is formed by depositing SiO2Coating photoresist on the surface of the SiC sample, throwing photoresist, and photoetching to form a P-type injection region; then the SiO without the protection of the photoresist is put in HF acid solution2Cleaning the layer to expose the P-type injection region;
a43 exposing the source P+The SiC samples of the region (5) and the drain P-type region (2) are placed in a high temperature ion implanter and subjected to high temperature aluminum ion implantation at 400 ℃ for four times to form a SiC sample having a concentration of about 1.5X 1019cm-3A depth of about 0.2 μm;
a44 cleaning the sample after high-temperature ion implantation in HF acid solution to remove SiO on the surface2And a barrier layer.
7. The manufacturing method according to claim 3, wherein the step A5 comprises the following steps:
a51 removing SiO on surface2Coating photoresist on the surface of the SiC epitaxial wafer sample of the barrier layer, spin coating, and placing the SiC epitaxial wafer sample in an oven to be baked for 1 minute at 90 ℃;
a52, putting the pre-baked SiC sample into a high-temperature annealing furnace, keeping the temperature at 600 ℃ for 30 minutes, and carbonizing;
a53, cooling the carbonized SiC sample;
8. the manufacturing method according to claim 3, wherein the step A6 comprises the following steps:
A61A sample with carbonized SiC surface was placed in a high-temperature annealing furnace, and the side with carbon film was made to face downward and evacuated to 10 deg.C-7Charging Ar gas, gradually heating to 1600 ℃, and staying at 1600 ℃ for 30 DEG CPerforming high-temperature ion implantation annealing;
a62, cooling the high-temperature ion implantation annealing furnace loaded with the sample to normal temperature, and taking the SiC sample out of the high-temperature annealing furnace.
9. The manufacturing method according to claim 1, wherein the step a7 comprises the following steps:
a71 placing the SiC sample subjected to high-temperature ion implantation annealing into a RIE reaction chamber with the carbon film side facing upwards, closing the valve of the reaction chamber, and opening N2Valves to 1/4, N2After 60 seconds, the nitrogen valve is closed;
A72N for 60 seconds on SiC samples with carbon film2After flushing, the oil pump is opened, the valve of the oil pump is completely opened when the sound of the oil pump becomes large and becomes stable, and the pump is stable for 20-30 minutes;
a73 opening the oxygen valve until the pressure inside the chamber reaches 9-12 mT;
a74 opening a cooling system, and adjusting the oxygen flow to 47 sccm;
a75, opening the radio frequency network adapter, timing for 90 minutes, and removing the carbon film on the surface of the SiC sample;
a76 turning off network adapter power and O2；
A77 depressurizing the system to normal pressure, turning off the cooling system, and filling N into the RIE reaction chamber2Until the reaction chamber door can be opened, taking out the sample;
10. the manufacturing method according to claim 1, wherein the step A8 comprises the following steps:
a81, performing HF acid cleaning on the SiC sample with the surface carbon film removed;
a82 placing the SiC sample cleaned by HF acid into a high temperature oxidation furnace, introducing pure oxygen at 1180 ℃, oxidizing the front side of the SiC epitaxial wafer for 10 hours under the condition of dry oxygen, and generating SiO with the thickness of 50nm2An oxide film;
a83 nitriding the grown oxide film: for growing SiO2Oxide film formationNO annealing at 1175 ℃ for 2 hours;
a84 forming a gate dielectric pattern by using a gate dielectric plate;
in the step A9, two metals of Ni/Au with the thickness of 20nm/240nm are used as source/drain and P-type ohmic contact metals; the specific process is as follows:
a91 coating a stripping glue and a photoresist on the front surface of the SiC sample subjected to gate dielectric layer manufacturing, photoetching, cleaning the photoresist and the stripping glue, and exposing effective source drain and P-type ohmic contact areas;
putting an A92SiC sample into an electron beam evaporation chamber;
a93 evaporating Ni/Au with the thickness of 20nm/240nm on the front surface of the SiC sample to be used as source drain and P-type ohmic contact metal;
a94 is stripped to form a source drain and P type ohmic contact metal pattern;
a95, placing the SiC sample with the source-drain and P-type ohmic contact electrodes in an annealing furnace, and carrying out alloy annealing at 950 ℃ for 30 minutes;
in the step A10, two metals of Ni/Au with the thickness of 20nm/240nm are used as gate metals; the specific process is as follows:
a101, coating stripping glue on the surface of a SiC sample subjected to source drain and P-type ohmic contact, and spinning the glue;
a102, coating photoresist on the surface of the SiC sample coated with the stripping glue, spinning the photoresist, and photoetching a gate metal region by using a gate plate;
a103, evaporating Ni/Au with the thickness of 20nm/240nm on the surface of the SiC sample with the etched gate contact hole to be used as gate contact metal;
a104, forming a gate pattern by using a stripping method;
in the step A11, two metals of Ti/Au are adopted for manufacturing the interconnection electrode, and the thicknesses of the two metals are respectively 50nm/200 nm; the method comprises the following steps:
a111 coating stripping glue and photoresist on the surface of the SiC sample with the manufactured gate metal;
a112, etching a grid, a source, a drain and a P-type ohmic contact electrode interconnection window by using an interconnection photoetching plate;
a113 evaporating Ti/Au with the thickness of 30nm/200nm on the surface of the SiC sample with the grid, source, drain and P-type ohmic contact holes as grid, source, drain and P-type ohmic contact metal;
a114, forming a grid, a source, a drain and a P-type ohmic contact interconnection pattern by using a stripping method.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5960290A (en) * 1998-10-29 1999-09-28 United Microelectronics Corp. Method for fabricating a protection circuit of electrostatic discharge on a field device
CN110473911A (en) * 2019-09-06 2019-11-19 芜湖启迪半导体有限公司 A kind of SiC MOSFET element and preparation method thereof
CN111900160A (en) * 2020-08-26 2020-11-06 璨隆科技发展有限公司 Electrostatic discharge protection circuit of power device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5960290A (en) * 1998-10-29 1999-09-28 United Microelectronics Corp. Method for fabricating a protection circuit of electrostatic discharge on a field device
CN110473911A (en) * 2019-09-06 2019-11-19 芜湖启迪半导体有限公司 A kind of SiC MOSFET element and preparation method thereof
CN111900160A (en) * 2020-08-26 2020-11-06 璨隆科技发展有限公司 Electrostatic discharge protection circuit of power device

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