CN105261642B - Hetero-junctions high electron mobility spin fet and manufacturing method - Google Patents
Hetero-junctions high electron mobility spin fet and manufacturing method Download PDFInfo
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- CN105261642B CN105261642B CN201510518311.1A CN201510518311A CN105261642B CN 105261642 B CN105261642 B CN 105261642B CN 201510518311 A CN201510518311 A CN 201510518311A CN 105261642 B CN105261642 B CN 105261642B
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- 229910010271 silicon carbide Inorganic materials 0.000 claims description 94
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- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 claims description 6
- -1 Nitrogen ion Chemical class 0.000 claims description 5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The present invention relates to hetero-junctions high electron mobility spin fet and manufacturing methods.Transistor include: include: the drain region 3C-SiC, 3C-SiC source region, 3C-SiC channel region, Schottky contacts gate electrode, 4H-SiC substrate, drain electrode, source electrode, SiN separation layer；The drain region 3C-SiC, 3C-SiC source region, 3C-SiC channel region are located on 4H-SiC substrate；Source electrode is located in 3C-SiC source region, and Schottky contacts gate electrode is located on 3C-SiC channel region, and drain electrode is located on the drain region 3C-SiC；SiN separation layer is located between source electrode and Schottky contacts gate electrode and Schottky contacts gate electrode and drain electrode.Hetero-junctions high electron mobility spin fet of the present invention and manufacturing method can change doping concentration and defect concentration in source and drain material by the dosage and annealing time for adjusting ion implanting, to optimize the spin polarizability in drain region and source region at room temperature.
Description
Technical field
The present invention relates to a kind of hetero-junctions high electron mobility spin fet and manufacturing methods more particularly to one
Kind receives the hetero-junctions height electricity of spinning polarized electron using injecting to tool defective 3C-SiC doping nitrogen-atoms production source-drain electrode
Transport factor spin fet and manufacturing method.
Background technique
With the rapid update of modern electronic technology, the integrated still operation of the development of conventional electronics, either scale
In terms of speed, microelectronics the reach of science is seriously limited.Emerging spintronics is easily to regulate and control electron spin
Main target opens the frontier to realize information storage and transmission using electron spin, causes physics, materialogy with
And the common concern of researcher and broad interest in more scientific domains such as electronic informatics.
In recent years, the spin field effect pipe proposed based on two-dimensional electron gas, theoretical and experimental study relate to electronics certainly
Rotation transports and many-sided complicated factors influenced such as material property, causes the concern and exploration of numerous researchers.Its basic structure
Want for by the electrical type of electrooptic modulator spin field transistor more so-called than proposition.By the electron spin of source electrode input along 3C-
The direction SiC, it can be expressed as the combination of positive and negative automatic rotary component in the z-direction, by electron effective mass Hamilton
The electron energy division for spinning up and spinning downward caused by Rashba, generates electronics in transport process and passes through field-effect
The phase difference of pipe, in the electronic phase angle along the spin of positive negative z direction that can regard as along the spin of the direction 3C-SiC that drain electrode receives
Variation is generated, to carry out current regulation.And the electricity of Rashba coefficients R ashba coefficient η and heterojunction boundary in Rashba
Field is directly proportional, therefore can control size of current by adding grid voltage.
But spinning electron is injected into semiconductor by general spin fet by ferromagnetic material, but due to iron
The band structure of magnetic material such as Fe and semiconductor material such as Sm mismatch so that the efficiency of spin injection only has a few percent.Cause
This, makes band structure matching to improve injection efficiency in spin field effect crystal using identical source-drain electrode and channel material
The application and research of tube device are particularly important.
N-type doping point defect 3C-SiC material has certain Spin Polarization Effect, can substitute existing technique, improves
Spin injection and received efficiency, to improve the performance of device.
Summary of the invention
The purpose of the present invention is in view of the drawbacks of the prior art, provide a kind of hetero-junctions high electron mobility spin field effect
Transistor and manufacturing method.The spin polarizability of material at room temperature can be optimized.
To achieve the above object, the present invention provides a kind of hetero-junctions high electron mobility spin fet, packets
Include: the drain region 3C-SiC, 3C-SiC source region, 3C-SiC channel region, Schottky contacts gate electrode, 4H-SiC substrate, drain electrode, source electrode,
SiN separation layer；
The drain region 3C-SiC, 3C-SiC source region, 3C-SiC channel region are located on the 4H-SiC substrate；The source bit
In in the 3C-SiC source region, the Schottky contacts gate electrode is located on the 3C-SiC channel region, and the drain electrode is located at institute
It states on the drain region 3C-SiC；The SiN separation layer be located at source electrode and Schottky contacts gate electrode and Schottky contacts gate electrode and
Between drain electrode.
Further, it is 1 × 10 that the material in the drain region 3C-SiC, which is n-type doping concentration,17cm-3-1×1020cm-3Tool
Defective 3C-SiC material, with a thickness of 0.5 μm.
Further, it is 1 × 10 that the material of the 3C-SiC source region, which is n-type doping concentration,17cm-3-1×1020cm-3Tool
Defective 3C-SiC material, with a thickness of 0.5 μm.
Further, the 3C-SiC channel region is 1 × 10 by n-type doping concentration15-1×1017cm-3Epitaxial layer is constituted.
Further, the Schottky contacts gate electrode is by depositing the Ni Schottky contacts with a thickness of 300nm formed
Gate electrode.
Further, it is 1 × 10 that the 4H-SiC substrate, which is doping concentration,14cm-34H-SiC material.
The present invention also provides a kind of manufacturing method of hetero-junctions high electron mobility spin fet, the sides
Method includes:
Step 1, successively 4H-SiC substrate is cleaned by ultrasonic using acetone, dehydrated alcohol and deionized water；
Step 2,0.5 μm of the chemical vapor deposition 3C-SiC epitaxial layer being lightly doped, doping concentration 1 on 4H-SiC substrate
×1015-1×1017cm-3；Reaction temperature is 1570 DEG C, pressure 100mbar, and reaction gas uses silane and propane, carrying gas
Body uses pure hydrogen, and impurity source uses gaseous nitrogen atmosphere；
Step 3, four Nitrogen ion Selective implantations are formed into drain region and source region:
Step 4, gluing, development are carried out to entire silicon carbide epitaxial layers, forms ohmic contact regions above source region and drain region
Domain deposits the Ni metal of 300nm, forms it into source electrode and drain electrode metal layer by ultrasonic wave removing later；In 1100 DEG C of argon
It in gas atmosphere, anneals 3 minutes to entire sample, forms source, leakage Ohm contact electrode；
Step 5, the SiN layer of 200nm thickness is deposited above epitaxial layer using plasma enhanced CVD method, it
Photoetching and CF are used afterwards4Plasma etching goes out 1 μm of grid region；
Step 6, using the method for magnetron sputtering in 3C-SiC channel surface splash-proofing sputtering metal 300nm W metal as Schottky
Gate electrode is contacted, then short annealing is handled in argon atmosphere.
Further, the step 3 specifically includes:
Step 31, Al that a layer thickness is 1 μm is deposited on silicon carbide epitaxial layers as drain region and source region ion implanting
Barrier layer forms drain region and source region injection region by lithography and etching；
Step 32,500 DEG C at a temperature of to silicon carbide epitaxial layers carry out four N~+ implantations, successively use
The Implantation Energy of 200keV, 140keV, 100keV and 65keV, are injected into silicon carbide epitaxial layers, and forming depth is 0.5 μm, doping
Concentration is 1 × 1017cm-3-1×1020cm-3Drain region and source region；
Step 33, using the Al on phosphoric acid removal silicon carbide epitaxial layers；
Step 34, silicon carbide epitaxy layer surface is cleaned using RCA cleaning standard, the protection of C film is made after drying；So
Ion-activated annealing 10min is carried out in 850 DEG C of argon atmospheres again afterwards.
Hetero-junctions high electron mobility spin fet of the present invention and manufacturing method, can be by adjusting ion implanting
Dosage and annealing time change doping concentration and defect concentration in source and drain material, thus the spin pole of optimization material at room temperature
Rate.
Detailed description of the invention
Fig. 1 is the schematic diagram of hetero-junctions high electron mobility spin fet of the present invention；
Fig. 2 is the flow chart of the manufacturing method of hetero-junctions high electron mobility spin fet of the present invention.
Specific embodiment
Below by drawings and examples, technical scheme of the present invention will be described in further detail.
Fig. 1 is the schematic diagram of hetero-junctions high electron mobility spin fet of the present invention, as shown, specific packet
Include the drain region 3C-SiC 1,3C-SiC source region 2,3C-SiC channel region 3, Schottky contacts gate electrode 4,4H-SiC substrate 5, drain electrode 6,
Source electrode 7 and SiN separation layer 8.
The drain region 3C-SiC 1,3C-SiC source region 2,3C-SiC channel region 3 are located on 4H-SiC substrate 5；Source electrode 7 is located at 3C-
In SiC source region 2, Schottky contacts gate electrode 4 is located on 3C-SiC channel region 3, and drain electrode 6 is located on the drain region 3C-SiC 1；SiN every
Absciss layer 8 is located between source electrode 7 and Schottky contacts gate electrode 4 and Schottky contacts gate electrode 4 and drain electrode 6.
Wherein, the drain region 3C-SiC 1 and 3C-SiC source region 2 are with a thickness of 0.5 μm, and n-type doping concentration is 1 × 1017cm-3-1
×1020cm-3, preferably 1 × 1019cm-3, the 3C-SiC material with defects, by three times or the selection of four Nitrogen ions
Property ion implanting is formed；3C-SiC channel region 3 is 1 × 10 by n-type doping concentration15-1×1017cm-3Epitaxial layer is constituted.3C-SiC
It is by depositing the Ni Schottky contacts grid 4 with a thickness of 300nm formed above channel region 3；Drain electrode 6 and source electrode 7 are located at 1 He of drain region
2 top of source region, the Ni by depositing 300nm are formed, and SiN is located at Schottky contacts grid 4 and source electrode 6 and drain electrode 7 as separation layer
Between, using plasma chemical vapor deposition generates.
4H-SiC substrate 5 is that doping concentration is 1 × 1014cm-34H-SiC material.
Hetero-junctions high electron mobility spin fet of the invention can by adjust ion implanting dosage and
Annealing time changes the doping concentration and defect concentration in source and drain material, to optimize the spin polarizability of material at room temperature.
Fig. 2 is the flow chart of the manufacturing method of hetero-junctions high electron mobility spin fet of the present invention, is such as schemed
It is shown, specifically comprise the following steps:
Step 1, successively 4H-SiC substrate is cleaned by ultrasonic using acetone, dehydrated alcohol and deionized water；
Step 2, on 4H-SiC substrate growth thickness be 0.5 μm of 3C-SiC epitaxial layer being lightly doped, doping concentration be 1 ×
1015-1×1017cm-3, process conditions are: reaction temperature is 1570 DEG C, pressure 100mbar, reaction gas using silane and
Propane, carrier gas use pure hydrogen, and impurity source uses gaseous nitrogen atmosphere；
Step 3, four Nitrogen ion Selective implantations form drain region and source region:
Specifically, including: step 3.1, it is 1 μm of Al as drain region and source that a layer thickness is deposited on silicon carbide epitaxial layers
The barrier layer of area's ion implanting forms drain region and source region injection region by lithography and etching；
Step 3.2,500 DEG C at a temperature of to silicon carbide epitaxial layers carry out four N~+ implantations, successively use
The Implantation Energy of 200keV, 140keV, 100keV and 65keV, are injected into silicon carbide epitaxial layers, and forming depth is 0.5 μm, doping
Concentration is 1 × 1017cm-3-1×1020cm-3Drain region and source region；
Step 3.3, using the Al on phosphoric acid removal silicon carbide epitaxial layers；
Step 3.4, silicon carbide epitaxy layer surface is cleaned using RCA cleaning standard, the protection of C film is made after drying；
Then ion-activated annealing 10min is carried out in 850 DEG C of argon atmospheres.
Step 4, gluing, development are carried out to entire silicon carbide epitaxial layers, forms ohmic contact regions above source region and drain region
Domain deposits the Ni metal of 300nm, forms it into source electrode and drain electrode metal layer by ultrasonic wave removing later；In 1100 DEG C of argon
It in gas atmosphere, anneals 3 minutes to entire sample, forms source, leakage Ohm contact electrode；
It specifically includes:
Step 4.1, gluing, development are carried out to entire silicon carbide epitaxial layers, forms Ohmic contact above source region and drain region
Region deposits the Ni metal of 300nm, forms it into source electrode and drain electrode metal layer by ultrasonic wave removing later；
Step 4.2, it in 1100 DEG C of argon atmosphere, anneals 3 minutes to entire sample, forms source, leakage Ohmic contact electricity
Pole；
Step 5, the SiN layer of 200nm thickness is deposited above epitaxial layer using plasma enhanced CVD method, it
Photoetching and CF are used afterwards4Plasma etching goes out 1 μm of grid region；
Step 6, using the method for magnetron sputtering in 3C-SiC channel surface splash-proofing sputtering metal 300nm W metal as Schottky
Gate electrode is contacted, then short annealing is handled in argon atmosphere.
Hetero-junctions high electron mobility spin fet machine manufacturing method of the present invention, since channel and source and drain are adopted
With same material, epitaxial growth can be directly carried out on substrate, while source and drain is using selection region ion implanting nitrogen-atoms
Mode is formed, have it is compatible with common process, be simple to manufacture, the small advantage of skin effect, at the same can be improved spin inject and connect
It produces effects rate.
Above-described specific embodiment has carried out further the purpose of the present invention, technical scheme and beneficial effects
It is described in detail, it should be understood that being not intended to limit the present invention the foregoing is merely a specific embodiment of the invention
Protection scope, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (8)
1. a kind of hetero-junctions high electron mobility spin fet characterized by comprising the drain region 3C-SiC, 3C-
SiC source region, 3C-SiC channel region, Schottky contacts gate electrode, 4H-SiC substrate, drain electrode, source electrode, SiN separation layer；
The drain region 3C-SiC, 3C-SiC source region, 3C-SiC channel region are formed at outside the 3C-SiC of the 4H-SiC substrate
Prolong on layer；The thickness of the depth in the drain region 3C-SiC, 3C-SiC source region and 3C-SiC channel region and the 3C-SiC epitaxial layer
It is identical；The source electrode is located in the 3C-SiC source region, and the Schottky contacts gate electrode is located on the 3C-SiC channel region,
The drain electrode is located on the drain region 3C-SiC；The SiN separation layer is located at source electrode and Schottky contacts gate electrode and Xiao Te
Base contacts between gate electrode and drain electrode；The drain region 3C-SiC and 3C-SiC source region are by three times or four Nitrogen ion selectivity ions
Injection is formed.
2. hetero-junctions high electron mobility spin fet according to claim 1, which is characterized in that described
The material in the drain region 3C-SiC is that n-type doping concentration is 1 × 1017cm-3-1×1020cm-3The defective 3C-SiC material of tool, it is thick
Degree is 0.5 μm.
3. hetero-junctions high electron mobility spin fet according to claim 1, which is characterized in that described
The material of 3C-SiC source region is that n-type doping concentration is 1 × 1017cm-3-1×1020cm-3The defective 3C-SiC material of tool, it is thick
Degree is 0.5 μm.
4. hetero-junctions high electron mobility spin fet according to claim 1, which is characterized in that described
3C-SiC channel region is 1 × 10 by n-type doping concentration15-1×1017cm-3Epitaxial layer is constituted.
5. hetero-junctions high electron mobility spin fet according to claim 1, which is characterized in that Xiao
Te Ji contact gate electrode is by depositing the Ni Schottky contacts gate electrode with a thickness of 300nm formed.
6. hetero-junctions high electron mobility spin fet according to claim 1, which is characterized in that described
4H-SiC substrate is that n-type doping concentration is 1 × 1014cm-34H-SiC material.
7. a kind of manufacturing method of hetero-junctions high electron mobility spin fet, which is characterized in that the method packet
It includes:
Step 1, successively 4H-SiC substrate is cleaned by ultrasonic using acetone, dehydrated alcohol and deionized water；
Step 2, the 3C-SiC epitaxial layer that chemical vapor deposition is lightly doped on 4H-SiC substrate with a thickness of 0.5 μm, doping concentration
It is 1 × 1015-1×1017cm-3；Reaction temperature is 1570 DEG C, pressure 100mbar, and reaction gas uses silane and propane, is carried
Fortune body uses pure hydrogen, and impurity source uses gaseous nitrogen atmosphere；
Step 3, four Selective implantations of Nitrogen ion are formed into drain region and source region；The source region and the depth in drain region and the extension
Layer is equal；
Step 4, gluing, development are carried out to entire silicon carbide epitaxial layers, forms ohmic contact regions above source region and drain region, formed sediment
The Ni metal of product 300nm forms it into source electrode and drain electrode metal layer by ultrasonic wave removing later；In 1100 DEG C of argon atmosphere
In, it anneals 3 minutes to entire sample, forms source, leakage Ohm contact electrode；
Step 5, the SiN layer for being deposited 200nm thickness above epitaxial layer using plasma enhanced CVD method, is made later
With photoetching and CF4Plasma etching goes out 1 μm of grid region；
Step 6, using the method for magnetron sputtering in 3C-SiC channel surface splash-proofing sputtering metal 300nm W metal as Schottky contacts
Gate electrode, then short annealing is handled in argon atmosphere.
8. the method according to the description of claim 7 is characterized in that the step 3 specifically includes:
Step 31, blocking of the Al that deposit a layer thickness is 1 μm on silicon carbide epitaxial layers as drain region and source region ion implanting
Layer forms drain region and source region injection region by lithography and etching；
Step 32,500 DEG C at a temperature of to silicon carbide epitaxial layers carry out four N~+ implantations, successively using 200keV,
The Implantation Energy of 140keV, 100keV and 65keV, are injected into silicon carbide epitaxial layers, and forming depth is 0.5 μm, doping concentration 1
×1017cm-3~1 × 1020cm-3Drain region and source region；
Step 33, using the Al on phosphoric acid removal silicon carbide epitaxial layers；
Step 34, silicon carbide epitaxy layer surface is cleaned using RCA cleaning standard, the protection of C film is made after drying；Then exist
Ion-activated annealing 10min is carried out in 850 DEG C of argon atmospheres.
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| CN107425059B (en) * | 2017-06-07 | 2020-05-22 | 西安电子科技大学 | Cr-doped heterojunction spin field effect transistor and preparation method thereof |
| CN107359122B (en) * | 2017-06-07 | 2020-09-08 | 西安电子科技大学 | Preparation method of Mn-doped heterojunction spin field effect transistor |
| CN107369707B (en) * | 2017-06-07 | 2020-03-24 | 西安电子科技大学 | Heterojunction spin field effect transistor based on 4H-SiC substrate and manufacturing method thereof |
| CN107359127B (en) * | 2017-06-07 | 2020-03-24 | 西安电子科技大学 | Fe-doped spin field effect transistor of sapphire substrate and manufacturing method thereof |
| CN107658337B (en) * | 2017-06-07 | 2020-09-08 | 西安电子科技大学 | High electron mobility spin field effect transistor and preparation method thereof |
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