CN103715232A - 用于半导体功率器件的沟槽式终端及其制备方法 - Google Patents

用于半导体功率器件的沟槽式终端及其制备方法 Download PDF

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CN103715232A
CN103715232A CN201210370720.8A CN201210370720A CN103715232A CN 103715232 A CN103715232 A CN 103715232A CN 201210370720 A CN201210370720 A CN 201210370720A CN 103715232 A CN103715232 A CN 103715232A
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terminal
groove
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power device
semiconductor power
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CN103715232B (zh
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褚为利
朱阳军
田晓丽
吴振兴
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Institute of Microelectronics of CAS
Jiangsu IoT Research and Development Center
Jiangsu CAS IGBT Technology Co Ltd
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Institute of Microelectronics of CAS
Jiangsu IoT Research and Development Center
Jiangsu CAS IGBT Technology Co Ltd
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Abstract

本发明公开了用于半导体功率器件的沟槽式终端，该终端包含至少一个沟槽，所述沟槽位于终端器件衬底内，终端表面由里及外覆盖有绝缘层和多晶硅，在所述终端区域的沟槽的端口和底部的周围具有P型区域，该P型区域与衬底的掺杂类型相反。本发明提供的用于半导体功率器件的沟槽式终端，通过在沟槽周围电场强烈集中的位置形成起保护作用的P型区域，该P型区域与衬底的掺杂类型相反，增强了该终端的可靠性。该沟槽式终端结构应用在元包结构为沟槽的功率器件中，能够减少器件制作的工艺步骤，从而降低制作成本。

Description

用于半导体功率器件的沟槽式终端及其制备方法
技术领域
本发明涉及半导体功率器件的终端技术领域，特别涉及半导体功率器件的沟槽式终端及其制备方法。
背景技术
优良的终端保护结构是功率器件，诸如功率二极管、功率MOS管、IGBT等，实现预定耐压的重要保障。在保证耐压的基础上，降低器件终端区域的面积是减低器件成本的有效措施。较早出现的终端结构是场限环（FLR），后有将场限环（FLR）和场板（FLR）结合的结构，以及结终端延伸技术（JTE）的终端结构。
专利US5949124-A所提出的终端结构，如图1所示。该专利提出一种沟槽的终端结构，但没有明确提出该种终端结构所适用的功率器件的栅极结构。具体实现：在距离主结12Pwell 0.5-100um的半导体表面，通过湿法刻蚀、反应离子刻蚀等方法形成纵向深度0.1-10um的沟槽14；沟槽14表面通过化学气相淀积等方法，淀积一层导电层16，导电层16与电极17是隔离的，该导电层16可以为掺杂类型与衬底11相反的半导体材料，也可以为Al或者其它类型的金属。这种终端结构，可使得器件承受耐压时耗尽层向外延伸，具体见图中的虚线，耐压范围可达到300V-2500V。
专利US5949124-A所提出的应用于平面结构的沟槽终端结构，需要额外的步骤去形成终端所需要的沟槽，与平面结构的制作过程兼容性不强。专利US5949124-A所提出的终端结构是利用导电材料对电场的屏蔽作用完成电场向芯片外延延伸，以达到实现预期耐压的目的；但是在图1中所示的A位置与B位置处，有强烈的电场集中现象，击穿非常容易发生，因此虽然该发明可以实现预定耐压，但是器件的可靠性却不高。
发明内容
本发明提供的用于半导体功率器件的沟槽式终端及其制备方法，解决了现有沟槽式终端存在的可靠性不高的问题。
为解决上述技术问题，本发明提供的用于半导体功率器件的沟槽式终端，该终端包含至少一个沟槽，所述沟槽位于终端器件衬底内，终端表面由里及外覆盖有绝缘层和多晶硅，在所述终端的沟槽的端口和底部的周围具有P型区，该P型区与衬底的掺杂类型相反。
进一步地，所述沟槽内还填充有钝化物。
进一步地，在所述沟槽的表面还具有一层导电层。
进一步地，所述沟槽式终端能用于沟槽式半导体功率器件，在有源区具有沟槽，在该沟槽端口的周围形成P基区。
为了解决上述问题，本发明还提供了该沟槽式终端应用于沟槽式半导体功率器件的制备方法，包含：将终端的沟槽形成过程与有源区的沟槽形成过程结合，在通过湿法刻蚀或反应离子刻蚀形成有源区的沟槽的同时形成终端区的沟槽。
进一步地，本制备方法还包含：在形成有源区沟槽端口周围的P基区的同时，形成终端区沟槽的端口和底部的周围的P型区。
本发明提供的用于半导体功率器件的沟槽式终端，通过在沟槽中电场强烈集中的位置形成起保护作用的P型区，该P型区与衬底的掺杂类型相反，增强了该终端的可靠性；进一步地，在沟槽中填充了钝化物，降低终端对界面电荷以及杂质离子电荷的敏感度；制备应用于沟槽式半导体功率器件的沟槽式终端的制备方法，在通过湿法刻蚀或反应离子刻蚀形成有源区的沟槽的同时形成终端区的沟槽，节省了步骤。
附图说明
图1为美国专利US5949124-A所提供的终端结构；
图2至图4为本发明实施例一提供的用于半导体IGBT功率器件的沟槽式终端的制备过程图；
图5为本发明实施例一提供的用于半导体IGBT功率器件的沟槽式终端；
图6和图7为本发明实施例二提供的用于半导体IGBT功率器件的沟槽式终端的制备方法部分步骤；
图8为本发明实施例二提供的用于半导体IGBT功率器件的沟槽式终端；
附图标记：
漂移区1，氧化层2，多晶硅层3，P基区4，P型区5，P型区6，填充物7，发射极8，集电区9，电极10，电极11，导电层12。
具体实施方式
本发明实施例提供的用于半导体功率器件的沟槽式终端，参见图5，适用于沟槽结构的功率器件，例如IGBT、VDMOS或者二极管等，但不限于仅仅应用于这些结构，也可用在平面结构的功率器件。
实施例一：
本发明实施例一提供的沟槽式终端，应用于半导体IGBT功率器件，参见图5，包含衬底结构1，氧化层2，多晶硅3，P基区4，P型区5，P型区6，填充物7，发射极8，集电区9，电极10和电极11。该终端表面由里及外覆盖有绝缘层2和多晶硅3。P型区5位于终端沟槽端口两侧的周围，P型区6位于终端沟槽底部的周围，二者的掺杂类型与漂移区1的衬底的相反，掺杂类型与漂移区1衬底的相反，并通过离子注入或者扩散的方法形成，并与P基区4的形成同步。填充物7为填充终端沟槽和有源区沟槽的钝化物，可以为SIPOS，也可以为SiO2、Si3N4或者两层Si3N4内夹着SiO2等的钝化层结构。发射极8为与衬底1掺杂类型相同的结构。集电区9为与漂移区1衬底的掺杂类型相同（对应VDMOS）或者相反（对应IGBT）的结构。电极10与P基区4连接，并位于P基区4的上方，电极11形成于集电区9，位于集电区9的下方。
为制备本发明提供的应用于半导体IGBT功率器件的沟槽式终端，本发明实施例一还提供了该沟槽式终端的制备方法，参见图2至图5，图中虚线左边是有源区，右侧是终端区：
本发明实施例一提供的沟槽式终端，应用于半导体IGBT功率器件，包含衬底结构1，氧化层2，多晶硅3，P基区4，P型区5，P型区6，填充物7，发射极8，集电区9，电极10和电极11。该终端表面由里及外覆盖有绝缘层2和多晶硅3。P型区5位于终端沟槽端口两侧的周围，P型区6位于终端沟槽底部的周围，二者的掺杂类型与漂移区1的衬底的相反，并通过离子注入或者扩散的方法形成，并与P基区4的形成同步。填充物7为填充终端沟槽和有源区沟槽的钝化物，可以为SIPOS、SiO2、Si3N4或者两层Si3N4内夹着SiO2等钝化层结构。发射极8为与衬底1掺杂类型相同的结构。集电区9为与漂移区1的衬底的掺杂类型相同（对应VDMOS）或者相反（对应IGBT）的结构。电极10与P基区4连接，并位于P基区4的上方，电极11形成于集电区9，位于集电区9的下方。
为制备本发明提供的应用于半导体IGBT功率器件的沟槽式终端，本发明实施例一还提供了该沟槽式终端的制备方法，参见图2至图5：
1、首先，参见图2，采用第一层掩膜版，分别在终端和有源区通过湿法刻蚀，或者反应离子刻蚀RIE等方法同步形成深度3～15μm的U型槽。该槽的深宽比，在终端位置和有源区位置可以相同，也可以不同。终端区的各个槽的深宽比，可相同，也可不同，深宽比为1～10。终端区所需要形成沟槽的个数，视器件结构的设计所需耐压而定，个数2～20。
2、其次，器件有源区位置的制作，参见图3。暂忽略对终端区的保护。采用以下工艺和步骤制备栅氧化层2和多晶硅层3：长牺牲氧化层→刻蚀牺牲氧化层→栅氧化层→淀积多晶硅，形成沟槽器件结构所需要的栅结构。
3、参见图4，利用第二层掩膜版，选择性刻蚀掉有源区硅片表面的多晶硅和栅氧化层以及终端区的多晶硅和栅氧化层，形成注入窗口。通过离子注入或者扩散的方法在有源区形成掺杂类型与衬底相反的P基区4，对应地同步在终端区沟槽的端口和底端的周围形成用于保护沟槽的P型区5和P型区6。P型区5形成于终端区域沟槽端口的两侧，掺杂类型与漂移区1相反的P型区。P型区6形成位于终端区域沟槽底端，掺杂类型与漂移区1相反。
4、利用化学气相淀积等方法形成填充物7，参见图5。填充物7可以为SIPOS，也可以为SiO2、Si3N4或者两层Si3N4内夹着SiO2等的钝化层结构。若填充物7为SIPOS，则接下来需要第三层掩膜版，将有源区内的SIPOS刻蚀掉，然后淀积氧化层，再利用第四层掩膜版，通过注入或扩散的方法形成发射极8，发射极8的掺杂类型与漂移区衬底1相同，并且进一步通过化学气相淀积的方法形成接触电极10。若填充物7为SiO2、Si3N4或者两层Si3N4内夹着SiO2等的钝化层结构，则接下来利用第三层掩膜版，刻蚀形成注入窗口，通过注入或扩散的方法形成掺杂类型与衬底相同的发射极8，并且进一步通过化学气相淀积的方法形成接触电极10。
5、背面结构集电区9，参见图6，可以通过离子注入或扩散的方法形成，也可为最初的衬底1材料，而漂移区衬底1是在集电区9的基础上淀积形成。最后通过化学气相淀积的方法形成电极11。
实施例二：
本发明实施例二提供的应用于半导体IGBT功率器件的沟槽式终端，在实施例一的基础上，还包含一层导电层12，该导电层12为通过化学气相淀积的导电物质，可以为掺杂类型与衬底材料1相反的半导体材料，也可以为Al、一定比例的钛镍银合金或者其它合适的金属或者合金材料。
为制备本发明提供的应用于半导体IGBT功率器件的沟槽式终端，本发明实施例二还提供了该沟槽式终端的制备方法，参见图2至图4、图6至图8，图中虚线左边是有源区，右侧是终端区：
1、首先，参见图2。采用第一层掩膜版，分别在终端和有源区通过湿法刻蚀，或者反应离子刻蚀（RIE）等方法形成深度3～15μm的U型槽。槽的深宽比在终端位置和有源区位置可以相同，也可以不同。终端区的各个槽的深宽比可相同，也可不同，深宽比1～10。终端区所需要形成沟槽的个数，视设计所需耐压而定，个数2～20。
2、其次，参见图3。器件有源区位置的栅氧化层2和多晶硅层3制作，暂忽略对终端区的保护。长牺牲氧化层→刻蚀牺牲氧化层→栅氧化层→淀积多晶硅，形成沟槽器件结构所需要的栅结构。
3、再次，参见图4，利用第二层掩膜版，选择性的刻蚀掉有源区硅片表面的多晶硅和栅氧化层以及终端区所有的多晶硅和栅氧化层，形成注入窗口；通过离子注入或者扩散的方法在有源区形成掺杂类型与衬底相反的P基区4，对应终端区形成P型区5和P型区6。
4、接下来，通过化学气相淀积的方法，在终端沟槽内壁形成一层均匀致密的导电层12，具体可以为掺杂类型与衬底材料1相反的半导体材料，也可以为Al、一定比列的钛镍银合金或者其它合适的金属或者合金材料，厚底0.1μm～1μm，见图6。
3、再次，参见图4，利用第二层掩膜版，刻蚀掉有源区硅片表面的多晶硅和栅氧化层以及终端区所有的多晶硅和栅氧化层；通过离子注入或者扩散的方法在有源区形成掺杂类型与衬底相反的P基区4，对应终端区形成P型区5和P型区6。
4、接下来，通过化学气相淀积的方法，在终端沟槽内壁形成一层均匀致密的导电层12，具体可以为掺杂类型与衬底材料1相反的半导体材料，也可以为Al、一定比列的钛镍银合金或者其它合适的金属或者合金材料，厚底0.1μm～1μm，见图6。
通过第三层掩膜版刻蚀掉不需要的导电层12，仅留下沟槽内壁以及沟槽边缘处的导电层，具体见图7。
在芯片的整个区域通过化学气相淀积形成钝化层7，并通过第四层掩膜版，通过离子注入或者扩散的方法形成掺杂类型与衬底相同的结构8，并淀积金属电极10。
背面结构9，可以与衬底1的掺杂类型相同，也可与衬底1的掺杂类型相反。背面结构9可以使通过离子注入或扩散的方法形成，也可为最初的衬底材料，而漂移区衬底1是在背面结构9的基础上淀积形成。最后通过化学气相淀积的方法形成集电区电极11。最终的结构参见图8。
本发明实施例提供的应用于半导体IGBT功率器件的沟槽式终端，与传统的场限环终端、含场限环的终端或JTE相比，更适用于沟槽型功率器件，将形成沟槽终端的步骤与形成有源区沟槽的步骤结合，这样减少了一个工艺步骤，降低了器件制作的成本。
本发明实施例提供的应用于半导体IGBT功率器件的沟槽式终端，利用U型槽将终端部分的峰值电场从半导体的表面延伸至半导体的内部，减小了器件受表面工艺缺陷影响较大的缺点；同时，与传统终端结构相比较，电场不仅仅在水平方向上延伸，在垂直方向上也有较大延伸，因此在规定耐压下，本发明实施例提供的终端结构需要较小的终端面积。
本发明实施例提供的应用于半导体IGBT功率器件的沟槽式终端，在有源区结构P基区4的形成过程中，在终端区沟槽的上侧两端以及沟槽底端分别同步形成P型区5和P型区6，这种结构可以防止终端沟槽电场集中的位置发生的提前击穿。
本发明实施例提供的应用于半导体IGBT功率器件的沟槽式终端，终端区域沟槽内的填充位置可以为SIPOS也可为SiO2、Si3N4或者两层Si3N4内夹着SiO2等的钝化层结构：填充物为SIPOS时，SIPOS连接功率器件耐压的两端，SIPOS内均匀分布的电场可以使终端区域内的电场分布更加；而填充物为各种钝化层时可以降低器件终端区域的漏电流。
本发明实施例提供的用于半导体功率器件的沟槽式终端，在具有沟槽结构的功率器件的应用中，能够减少器件制作的工艺步骤，减小器件终端的面积，从而降低器件的制作成本；在平面结构的应用中，虽然不能减少器件制作的工艺步骤，但是能够减低器件终端的面积，也可降低器件的制作成本。
最后所应说明的是，以上具体实施方式仅用以说明本发明的技术方案而非限制，尽管参照实例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换，而不脱离本发明技术方案的精神和范围，其均应涵盖在本发明的权利要求范围当中。

Claims (6)

1.用于半导体功率器件的沟槽式终端，其特征在于，终端包含至少一个沟槽，所述沟槽位于终端器件衬底内，终端表面由里及外覆盖有绝缘层和多晶硅，在所述终端的沟槽的端口和底部的周围具有P型区，该P型区与衬底的掺杂类型相反。
2.如权利要求1所述的用于半导体功率器件的沟槽式终端，其特征在于，所述沟槽内还填充有钝化物。
3.如权利要求1或2所述的用于半导体功率器件的沟槽式终端，其特征在于，在所述沟槽的表面还具有一层导电层。
4.如权利要求1或2所述的用于半导体功率器件的沟槽式终端，其特征在于，所述沟槽式终端能用于沟槽式半导体功率器件，在有源区具有沟槽，在该沟槽端口的周围形成P基区。
5.用于如权利要求4所述的半导体功率器件的沟槽式终端的制备方法，其特征在于，包含：在通过湿法刻蚀或反应离子刻蚀形成有源区的沟槽的同时形成终端区的沟槽。
6.如权利要求5所述的用于半导体功率器件的沟槽式终端的制备方法，其特征在于，还包含：在形成有源区沟槽端口周围的P基区的同时，形成终端区沟槽的端口和底部的周围的P型区。
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CN116544268B (zh) * 2023-07-06 2023-09-26 通威微电子有限公司 一种半导体器件结构及其制作方法

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