CN103703541A - 测试倒装芯片组合件背景中的集成电路的技术和结构 - Google Patents

测试倒装芯片组合件背景中的集成电路的技术和结构 Download PDF

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CN103703541A
CN103703541A CN201280036048.7A CN201280036048A CN103703541A CN 103703541 A CN103703541 A CN 103703541A CN 201280036048 A CN201280036048 A CN 201280036048A CN 103703541 A CN103703541 A CN 103703541A
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substrate
interconnection
conductive base
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CN103703541B (zh
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M·戴斯彻内斯
M·高温
E·吉谷尔瑞
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

这里公开了一种将从已有衬底（104）去除的IC管芯（102）重新接合到新衬底（106）的方法。在一实施例中，这样的方法包括：从IC管芯（102）研磨已有衬底（104）以产生暴露互连（202）和周围的底部填充材料（204）的基本平坦表面。提供具有从其突出的导电基座（300）的新衬底（106）。导电基座（300）定位成与暴露的互连（202）对准并且具有比互连（202）的熔点实质上更高的熔点。该方法将暴露的互连（202）安置为与导电基座（300）接触。然后，该方法应用回流工艺以将暴露的互连（202）熔化并且电接合到导电基座（300）。还公开了该方法所产生的结构。

Description

测试倒装芯片组合件背景中的集成电路的技术和结构
技术领域
本发明涉及半导体器件，更特别地，涉及用于测试倒装芯片组合件中的集成电路的技术和结构。
背景技术
故障分析是确定故障原因，收集和分析故障相关数据，并且得出结论以消除或减轻故障原因的过程。在半导体工业中，针对集成电路进行故障分析是改善集成电路的质量和设计以及生产集成电路的制造工艺必不可少的。集成电路的制造商需要清楚他们的电路和制造工艺的弱点，以便开发用于监测和消除这样的弱点的手段。
由于集成电路被包括到各种不同的电子封装中，因此对这样的集成电路进行故障分析可能是有挑战性的。例如，如现在很常见的，以多个倒装芯片组合件形式存在的多个集成电路可以安装到多芯片模块（MCM）衬底中。为了对安装到这样的MCM衬底上的集成电路执行故障分析，可以从MCM衬底去除集成电路管芯，并将集成电路管芯附接到更适于测试的单芯片模块（SCM）。然而，在从MCM衬底去除集成电路管芯之后在集成电路管芯与SCM衬底之间创建可靠的连接可能是有挑战性的。
从MCM衬底去除集成电路（IC）的一种方法是切割IC管芯周围的MCM衬底并研磨去除剩余的MCM衬底。这将暴露焊料互连（例如，C4互连）以及周围的底部填充材料。然后，可以在SCM衬底上沉积焊料凸块，以允许IC管芯电接合到该衬底。替选地，可以在IC管芯的互连上方沉积焊料凸块，以允许IC管芯电接合到SCM衬底。遗憾的是，这些技术不可靠，因为它们可能导致IC管芯的互连之间的短路。这种短路可能是由在回流工艺期间通过毛细管作用流到IC管芯和SCM衬底之间的间隙的焊料导致的结果。
鉴于前述内容，需要改善的用于测试倒装芯片组合件中的集成电路的技术和结构。具体而言，需要改善的技术和结构以将从诸如MCM衬底之类的已有衬底去除的IC管芯重新接合到诸如SCM衬底之类的新衬底。
发明内容
本发明是响应于当前技术状况，更特别地，响应于本领域中尚未被当前技术和结构完全解决的问题和需求而开发出来的。相应地，开发了本发明以提供用于将从诸如MCM衬底之类的已有衬底去除的IC管芯重新接合到诸如SCM衬底之类的新衬底的技术和结构。本发明的特点和优点将从下面的描述和所附权利要求变得显而易见，或者可通过如下所述地实践本发明而得到领悟。
根据前述内容，这里公开一种将从已有衬底去除的IC管芯重新接合到新衬底的方法。在一实施例中，这样的方法包括从IC管芯研磨已有衬底以产生暴露互连和周围的底部填充材料的基本平坦表面。提供具有从其突出的导电基座的新衬底。导电基座被定位成与暴露的互连对准，并且具有比互连的熔点实质上更高的熔点。该方法将所暴露的互连置于与导电基座接触，使得导电基座在新衬底和底部填充材料之间产生受控制的间隙。然后，该方法应用回流工艺以熔化所暴露的互连并将所暴露的互连与导电基座电接合。
在本发明的另一方面，根据本发明的微电子组合件包括IC管芯，IC管芯具有结合到其的互连。结合到IC管芯的第一底部填充层包围所述互连。所述微电子组合件还包括衬底，该衬底具有从其突出的导电基座。导电基座具有比互连的熔点实质上更高的熔点。导电基座与互连对准并且电连接到互连。第二底部填充层包围导电基座并且将第一底部填充层与衬底分隔开。
附图说明
为了容易地理解本发明的优点，将参照附图所示的特定实施例，提供对上面简述的本发明更具体的描述。将理解，这些附图只描绘了本发明的各典型实施例，因此不被认为是对其范围的限制，将通过使用附图，用附加特征和细节来描述和说明本发明，附图中：
图1A到1D示出了用于从MCM衬底去除IC管芯并将IC管芯重新接合到SCM衬底的过程的一实施例；
图2A是示出了用于将从已有衬底去除的IC管芯接合到新衬底的非理想技术和结构的截面侧视图；
图2B是示出了使用图2A的技术和结构所产生的微电子组合件的截面侧视图；
图3A是示出了用于将从已有衬底去除的IC管芯接合到新衬底的改善的技术和结构的截面侧视图；
图3B是示出了使用图3A的技术和结构所产生的微电子组合件的截面侧视图；
图3C是示出了使用图3A的技术和结构所产生的微电子组合件在IC管芯和衬底之间的受控制的间隙已经被底部填充之后的截面侧视图；
图4是示出了从衬底突出的导电基座的尺寸的一个示例的截面侧视图；
图5是示出了使用关于图2A和2B描述的非理想技术和结构接合的实际焊料互连和铜垫的图像；以及
图6A和6B是示出了使用关于图3A到3C描述的改善的技术和结构接合的实际焊料互连和铜基座的图像。
具体实施方式
可以容易地理解，本发明的组件（如这里一般地描述且示于图中的那些）可以按各种不同的构造来布置和设计。因此，下面对图中呈现的本发明的实施例的更详细的说明无意限制所要求保护的本发明的范围，而仅是根据本发明的当前构思的实施例的某些示例的代表。通过参考附图，将最好地理解目前所描述的各实施例，附图中类似的部分将始终由类似的数字指示。
参考图1A到1D，示出了用于从MCM衬底去除IC管芯并将IC管芯重新接合到SCM衬底的过程的一实施例。如图1A所示，多芯片模块（MCM）100可以包括安装到诸如多层层叠结构104之类的公共衬底104的多个IC管芯102。在某些实施例中，整个MCM100可被称为“芯片”，突显其集成本质。与其他电子组件类似，IC管芯102会发生故障。然而，由于MCM100的集成本质，测试或分析安装到MCM100的单个IC管芯102可能是有挑战性的。这是因为可能难以将发生故障的IC管芯102与衬底104上的其他组件隔离开，或难以访问发生故障的IC管芯102的互连或其他连接以执行测试。为了克服这些局限性，IC管芯102可被从MCM100去除，并被附接到更适于测试和分析的单芯片模块（SCM）衬底106。
如图1B所示，用于从MCM衬底104去除IC管芯102的一种方法是从衬底104切割IC管芯102（例如，通过切割紧绕IC管芯102周围的衬底104）。这将产生类似于图1B所示结构的结构108。然后，可以对结构108应用研磨机以研磨去除剩余的衬底104，并且暴露下面的互连和底部填充材料。替选地，可以使用热管芯去除工艺来熔化焊料互连并且断开下面的底部填充材料。
一旦已经从MCM100去除了IC管芯102，IC管芯102就可以接合到新SCM衬底106。在某些情况下，SCM衬底106提供与IC管芯102的接口连接，其更适于测试和/或分析IC管芯102。例如，SCM衬底106可以包括更适于耦合到诊断设备的连接或电路系统。
在常规实现中，为了允许IC管芯102电接合到SCM衬底106，可以在SCM衬底106上沉积焊料凸块。将关于图2A和2B来更详细地描述这样的过程。替选地，可以在IC管芯102上沉积焊料凸块（即，IC管芯102可以被再形成凸块），以允许IC管芯102电接合到SCM衬底106。遗憾的是，在IC管芯102上存在底部填充的情况下，这些传统技术可能是不可靠的，因为它们可能在互连之间产生电短路。这种短路可能是在回流工艺中焊料通过毛细管作用流入到底部填充（underfill）和SCM衬底106之间的狭窄间隙中的结果。这样的传统技术也可能是昂贵耗时并易于产生缺陷的多步骤工艺。
如下文将更详细地说明的那样，在根据本发明的某些实施例中，焊料凸块可被从SCM衬底106突出的导电基座110（诸如导电柱、栓或桩）代替。导电基座110可以由熔点实质上高于IC管芯102上的焊料互连（例如，C4互连）的熔点的材料制成。这将确保当回流工艺应用于单芯片模块112时，只有IC管芯102上的焊料互连将熔化和回流。将关于图3A到3C更详细地描述此过程。如图3A到3C所示，导电基座110通过在IC管芯102和SCM衬底106之间维持额外的分隔，在IC管芯102和SCM衬底106之间创建更可靠的连接，由此防止焊料互连之间的短路并允许引入新的底部填充。
图1C示出了在将IC管芯102接合到SCM衬底106之前的IC管芯102和SCM衬底106。图1D示出了在IC管芯102已经接合到SCM衬底106之后的单芯片模块112。
图2A是示出了用于将带有底部填充的IC管芯102接合到SCM衬底106的常规技术的示例的截面侧视图。描述了此技术以突显与将关于图3A到3C描述的改善技术的差异。如图所示，在IC管芯102已经被从MCM衬底104切割并且剩余衬底104已经被研磨去除之后，可以在IC管芯102上产生基本平坦的表面200。此平坦表面200可以暴露焊料互连202以及周围的底部填充材料204。
在这样的常规技术中，为使IC管芯102能连接到SCM衬底106，可以在SCM衬底106上的倒装芯片附连（FCA）垫208（例如，铜FCA垫208）或其他导电元件208上沉积焊料凸块206（例如，由焊膏制成的凸块206）。替选地，可以将焊料凸块206沉积到IC管芯102的暴露的焊料互连上（称为“凸块再形成”的工艺）。FCA垫208或其他元件208可以通过衬底106上的阻焊剂层210暴露，并且电连接到嵌入在衬底106内的诸如导电迹线或布线（未示出）之类的电路系统。
为了将IC管芯102接合到SCM衬底106，可以将焊料互连202置于与焊料凸块206接触。替选地，如果焊料凸块206初始附接到焊料互连202，则可将焊料凸块206置于与FCA垫208接触。然后，可以对组合件应用回流工艺。这将熔化并重新固化焊料互连202和焊料凸块206，以将IC管芯102电接合到SCM衬底106。此过程将产生与图2B所示的结构类似的结构。
如图2B所示，在应用回流工艺之后，焊料互连202和焊料凸块206将熔化并且重新固化以形成焊料接合212，类似于图2B所示的那些。由于在IC管芯102上存在已有的底部填充，所以在底部填充204和SCM衬底106之间产生狭窄间隙214（通常在二十到二十五微米的范围内）。由于间隙214的狭窄性，熔化的焊料在回流工艺中可通过毛细管作用被吸入到间隙214中。这会在焊料连接212之间产生不希望有的电桥216，如图2B所示。这样的短路将产生可能使单芯片模块112无法用于其计划用途的缺陷。IC管芯102和SCM衬底106之间的间隙214的狭窄性还可防止将新的底部填充材料引入到间隙214中，这取决于新的底部填充材料的颗粒尺寸和/或粘滞度。
图3A是示出了用于将带有底部填充204的IC管芯102接合到SCM衬底106的改善的技术的截面侧视图。类似于前一示例，可以首先从MCM衬底104去除IC管芯102，可以研磨去除剩余的MCM衬底104以提供基本平坦的表面200。平坦表面200暴露焊料互连202和周围的底部填充材料204。
代替在SCM衬底106或焊料互连202上沉积焊料凸块206（如在前一示例中所执行的那样），SCM衬底106可具有从其突出的导电基座300。这些导电基座300可以与焊料互连202对准，并且相对于阻焊剂层210突出指定距离（例如，至少三十微米，理想地，至少四十微米）。在某些实施例中，导电基座300被实现为从SCM衬底106延伸的导电柱、栓或桩。导电基座300可以从导电垫208延伸并且电连接到导电垫208，导电垫208又可以电连接到嵌入在衬底106内的电路系统。除了其他优点之外，导电基座300还可以在底部填充层204和阻焊剂层210之间创建更大的受控制的间隙。如将关于图3B和3C说明的那样，此更大的受控制的间隙可以防止短路，并且提供引入新的底部填充材料的空间。
如前所述，导电基座300可以由熔点实质上高于焊料互连202的熔点的导电材料制成。这将确保导电基座300在回流工艺期间是稳定的（即，将不会熔化）。在一个示例中，焊料互连202由基于铅的或无铅的、基于锡的焊料制成，导电基座300由铜制成。在某些实施例中，可以在铜基座300上应用锡镀304或其他焊料镀304。在某些实施例中，在衬底106上沉积阻焊剂层210之后，使用镀铜工艺（在铜垫208上）产生铜基座300。由于铜具有比基于铅或锡的焊料更高的熔点，所以可以应用熔化焊料互连202和镀材料304而不熔化导电基座300的回流工艺。
上面针对互连202、基座300、镀材304以及垫208给出的材料（即，锡、铜等）只作为示例提供，无意成为限制。实际上，此处所呈现的技术和结构可以与各种材料或材料组合一起使用，包括此处未特别指出的材料。
为了使用图3A的结构来将IC管芯102接合到SCM衬底106，焊料互连202可置于与导电基座300上的镀层304接触。然后，可以对组合件应用回流工艺。这将熔化并重新固化焊料互连202和镀材料304，以将焊料互连202接合到导电基座300。这将产生与图3B所示的结构类似的结构。
如图3B所示，在已经应用回流工艺之后，焊料互连202和镀材料304将熔化并且重新固化以形成焊料连接212。由于IC管芯102和SCM衬底106之间更大的受控制的间隙306以及基座材料（例如，铜）和焊料（例如，锡）之间潜在的吸引力，熔化的焊料将绕导电基座300流动并依附到导电基座300。更大的受控制的间隙306将减小毛细管作用，否则毛细管作用可能导致焊料流入到间隙中。因此，来自每一个互连202和对应的镀层304的焊料将依附到对应的导电基座300的顶部和侧面。这将减少电短路，并且提高单芯片模块112的可靠性。
IC管芯102和SCM衬底106之间的更大的受控制的间隙306还可以用诸如电绝缘环氧树脂302之类的电绝缘粘合剂302来进行底部填充，如图3C所示。除了其他优点之外，底部填充302还可以提供焊料连接212之间的额外绝缘，在IC管芯102和SCM衬底106之间产生更强的机械连接，在IC管芯102和SCM衬底106之间提供热桥，以及确保焊料连接212不会由于IC管芯102和SCM衬底106之间的差温加热（differential heating）而受应力。
参考图4，导电基座300的大小可设置为提供上述优点。图4示出了由发明人实施的导电铜基座300、镀锡304、铜垫208以及阻焊剂层210的尺寸（以微米为单位）。这些尺寸作为示例提供，无意成为限制。在所示实施例中，铜基座300相对于阻焊剂层210顶部的高度大致是四十微米。镀锡材料304大致是二十微米厚。在回流工艺已经熔化并且重新固化焊料互连202和镀材料304之后，将在底部填充层204和阻焊剂层210之间创建大约四十到四十五微米的受控制的间隙306。在某些实施例中，受控制的间隙306为至少三十微米，理想地，至少四十微米。发明人发现，四十微米的间隙306足以防止焊料沿底部填充层204和阻焊剂层210之间的间隙306流动，由此防止电短路。此间隙306也足以容纳新的底部填充材料302以进一步绝缘焊料连接212。
参考图5，示出了显示使用关于图2A和2B描述的非理想技术产生的焊料接合212的截面的图像。图像是使用暗视野光学成像产生的。在此示例中，通过对基于锡的焊料互连202和铜FCA垫208上的基于锡的焊料凸块206应用回流工艺，来创建焊料接合212。区域212表示由焊料凸块206和焊料互连202的结合所创建的焊料接合212。底部区域208表示铜FCA垫208。可以观察到，在IC管芯底部填充层204和阻焊剂层210之间存在大致二十五微米的狭窄间隙214。此狭窄间隙214对熔化的焊料产生毛细管效应，并且太窄而不能容纳新的底部填充材料。浅色区域214表示流入到间隙214中的焊料，有可能在焊料连接212之间产生导电桥（即，短路）。
参考图6A和6B，示出了显示使用关于图3A到3C描述的技术产生的焊料接合212的截面图的若干图像。在此示例中，通过向对着镀有锡的铜基座300放置的基于锡的焊料互连202应用回流工艺，来创建焊料接合212。区域212是表示基于锡的焊料互连202和镀锡材料304的结合的焊料接合212。区域300是附接到铜垫208的铜基座300。区域204是IC管芯102上的底部填充材料，区域210是SCM衬底106上的阻焊剂层210。区域306是底部填充材料204和阻焊剂层210之间的受控制的间隙306。在此示例中，受控制的间隙306为大致四十五微米宽。可以观察到，代替流入到受控制的间隙306中，来自焊料互连202和镀锡304的焊料包围并且依附到铜基座300，由此防止与其他焊料连接212电短路。受控制的间隙306还提供足够的空间以引入新的底部填充材料。
如上所述，在将IC管芯102重新安装到SCM衬底106时，导电基座300提供各种优点。导电基座300不仅减少短路和提供更受控制的间隙以容纳新的底部填充材料，而且导电基座300还可以降低当接合IC管芯102和SCM衬底106时平坦表面200所需的一致性。或许更重要的是，与常规过程相比，导电基座300减少了将IC管芯102重新安装到SCM衬底106所需的处理步骤的数量（例如，无需对IC管芯102或SCM衬底106“重新形成凸块（re-bump）”）。这又将降低对IC管芯102执行诊断所需的时间和成本。
此处所公开的技术和结构可以以其他特定形式实现，而不背离其精神或本质特性。所描述的实施例在所有方面都应被认为仅是说明性而非限制性的。因此，本发明的范围由所附权利要求书而非前述描述来指示。落入权利要求书的含义和等效范围内的所有改变应被权利要求书的范围所涵盖。

Claims (20)

1.一种将从已有衬底去除的IC管芯重新接合到新衬底的方法，所述方法包括：
从IC管芯研磨已有衬底，由此在所述IC管芯上产生暴露互连和周围的底部填充材料的基本平坦表面；
提供新衬底，所述新衬底包括从其突出的多个导电基座，所述导电基座具有比所述互连的熔点实质上更高的熔点，所述导电基座定位为与所暴露的互连对准；
将所暴露的互连置于与所述导电基座接触，所述导电基座产生所述新衬底和所述底部填充材料之间的受控制的间隙；以及
应用回流工艺以熔化所暴露的互连并且将所暴露的互连与所述导电基座电接合。
2.如权利要求1所述的方法，其中，所述导电基座是铜基座。
3.如权利要求2所述的方法，其中，所述铜基座被锡覆盖。
4.如权利要求1所述的方法，其中，所述导电基座是导电柱、栓和桩之一。
5.如权利要求4所述的方法，其中，所述导电基座相对于所述新衬底的高度是至少三十微米。
6.如权利要求5所述的方法，其中，所述导电基座相对于所述新衬底的高度是至少四十微米。
7.如权利要求1所述的方法，还包括通过用电绝缘材料填充所述受控制的间隙来对所述IC管芯进行底部填充。
8.如权利要求1所述的方法，其中，所述互连是C4互连。
9.如权利要求1所述的方法，其中，所述已有衬底是多组件模块（MCM）衬底。
10.如权利要求1所述的方法，其中，所述新衬底是单组件模块（SCM）衬底。
11.一种微电子组合件，包括：
集成电路（IC）管芯，包括结合到其的多个互连；
第一底部填充层，结合到所述IC管芯并且包围所述互连；
衬底，包括从其突出的多个导电基座，所述导电基座具有比所述互连的熔点实质上更高的熔点，所述导电基座与所述互连对准并且电连接到所述互连；以及
第二底部填充层，包围所述导电基座并且将所述第一底部填充层与所述衬底分隔开。
12.如权利要求11所述的微电子组合件，其中，所述导电基座是铜基座。
13.如权利要求12所述的微电子组合件，其中，所述铜基座被锡覆盖。
14.如权利要求11所述的微电子组合件，其中，所述导电基座是导电柱、栓和桩之一。
15.如权利要求14所述的微电子组合件，其中，所述导电基座相对于所述衬底的高度是至少三十微米。
16.如权利要求15所述的微电子组合件，其中，所述导电基座相对于所述衬底的高度是至少四十微米。
17.如权利要求11所述的微电子组合件，其中，所述第二底部填充层填充所述第一底部填充层和所述衬底之间的受控制的间隙。
18.如权利要求11所述的微电子组合件，其中，所述互连是C4互连。
19.如权利要求11所述的微电子组合件，其中，所述衬底是单组件模块（SCM）衬底。
20.如权利要求11所述的微电子组合件，其中，所述第一和第二底部填充层是电绝缘层。
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