CN103688354A - 用于宽带隙功率晶体管的改进的匹配技术 - Google Patents
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Abstract
公开了用于与微波功率晶体管进行阻抗匹配的阻抗匹配网络和技术。分布式电容器电感器网络被使用,以便与现有的集总电容器布置相比,特别是在电感值方面,提供高度的控制和精度。通过主要由电容器上的微带传输线提供电感,减少了键合线的使用。
Description
本申请涉及在分立的微波功率晶体管的前级和末级匹配中使用分布式电容及其阵列以改进功率放大器的性能。
背景技术
使用分立(未封装)宽带隙晶体管的微波功率放大器可以通过如下方式以混合布置实现:使用单个晶体管或使用与特定的分离的无源电子元件组合(并联)并组装以实现所规定的性能水平的若干个这样的晶体管。该混合微波集成电路(MIC)的实现对于集成解决方案(诸如微波单片集成电路或MMIC)常常是优选的,这是因为通过使用“Q”较高的外部嵌入电子元件,可以导致极大的性能改进。MIC布置的要求是通过使用许多键合线将分立晶体管连接到输入和输出匹配网络或元件。每个晶体管的输出包括大量本征并联馈电,并且因此具有低阻抗(较之低功率晶体管),而输入包括大量栅极,并且因此具有相对高的电容(较之低功率晶体管)。因此难于在晶体管和它的嵌入电路之间提供合适的阻抗匹配,该合适的阻抗匹配提供跨越所需频带的良好功率传输。这样的匹配需要应用规定的感抗和容抗。
MIC器件中的键合线被用于将各个分立元件连接在一起,并且键合线通常是使用传统的线键合设备组装的长度短的(例如50-500μm)、细的(例如直径为25μm)、高导电率(通常是金或铝)的线。这些键合线具有感抗,该感抗随工作频率增加(XL=ωL,其中XL是感抗,ω是频率,并且L是键合线的长度),并且该感抗关键取决于线的长度和取向。
然而,这导致了问题:使用键合线来形成阻抗变换的部分电感的设计对来自键合线制造生产公差的性能变化敏感。具体地,由键合线提供的电感关键由其长度和形状决定,即使是键合线长度或取向的轻微变化,也可以导致电感变化,尤其是在高频时。例如,在2GHz可能不会带来特别问题的键合线长度变化在20GHz时变得相当成问题的,其中对于同一长度的线,其电抗高10倍。
作为整个混合放大器电路的一部分,键合线电感需要被精确地控制,以确保可重复的和高产的电路性能。一些一致性和控制可以通过使用自动的线键合技术来达到,但是这对于小批量生产并不总是可能的,并且线的长度仍然受特定的制造公差支配。
因此,主要问题是怎样克服来自在重要的嵌入匹配网络内使用具有潜在地随机或系统变化的尺寸的键合线的MIC功率放大器的固有性能变化(以及因此对制造产量的限制)。换句话说,怎样显著降低这样的放大器的性能对放大器匹配网络中使用的键合线的制造变化的敏感性。
除了这个主要的问题,需要实现能够适应宽带隙晶体管的低输出阻抗和高输入电抗的匹配网络(虽然对于其他传统的FET器件也存在同一问题)。这可以通过使用外部“集总”支路电容匹配元件(芯片电容器)作为阻抗变换器来实现,但是这需要密切关注外部的键合线电感的影响。这样的匹配网络的示例从EP2197030可知,EP2197030公开了采用具有多个并行输入和多个并行输出的场效应晶体管(FET)形式的高频半导体器件,其中并行输入和并行输出均由多个键合线实现。
另一个问题是,使用分离的电感器(键合线)和芯片电容器来实现阻抗变换的集总设计与使用分布式网络相比,具有固有的带宽限制,除非电容和电感的级数增加。
发明内容
从一方面看,提供了一种用于微波功率晶体管的中间阻抗变换器件,该器件包括:介电基板,其承载或包含多个伸长的微波传输线,每个微波传输线具有长度且延伸越过或穿过基板,每个微波传输线具有第一末端和第二末端、每单位长度的预定的串联电感以及与电隔离导电板或层相结合的每单位长度的预定的支路电容,使得每个长度的微波传输线与导电板或层一起具有预定的特征阻抗和相位常数;器件,其被配置成使得,当具有相关联的阻抗的指定的最小实际长度的键合线连接在一个微波传输线的末端和微波功率晶体管之间时,键合线的阻抗被吸收到微波传输线的每单位长度的阻抗中。
从另一方面看,提供了一种阻抗变换布置,其包括在具有第一介电常数的第一介电基板上形成的微波功率晶体管以及至少一个以上方面的中间阻抗变换器件。
从另一方面看,提供了一种与微波功率晶体管结合的阻抗变换布置,该阻抗变换布置包括在具有第一介电常数的第一介电基板上形成的匹配网络以及至少一个中间阻抗变换器件。
从又一个方面看,本发明提供了一种与微波功率晶体管进行阻抗匹配的方法,其中,多个微波传输线通过键合线被连接,每个键合线对晶体管的栅极或漏极端子具有阻抗,微波传输线延伸越过或穿过介电基板,微波传输线具有预定的串联电感以及与电隔离导电板或层相结合的预定的支路电容,使得每个微波传输线与电隔离导电板或层一起具有预定的特征阻抗和相位常数,以及其中,每个键合线的阻抗被吸收到其连接的微波传输线的阻抗中。
在典型的实施方式中,阻抗匹配器件包括以并联形式并排布置的微波传输线的阵列。每个线可能具有通过电磁耦合影响它邻近的线的可能性,并且因此可以改变它的每单位长度的有效电容或电感。该阵列设置在晶体管的栅极侧或晶体管的漏极侧,或者可以设置两个阵列,在晶体管的每一侧上各设置一个阵列,用于前级和末级匹配。每个阵列可以在一片介电基板上形成,或者分别在分离的介电基板上的若干个阵列可以设置在晶体管的一侧或另一侧或两侧。该器件可以被制造为单个部件(用于晶体管的每侧),或者若干个相同的部件可以以并排的形式部署。
包括分布式电感和电容的阻抗变换器件可以被视为或配置成条形电容器的阵列,其通常采用矩形介电基板的形式,该介电基板具有基本上平行的第一和第二主表面,具有第一和第二表面上的金属化以形成电容器的极板。一个表面上的金属化可以基本上位于整个表面上,而另一相对表面上的金属化可以采用微波传输线的形式,诸如导电微带传输线,共面波导或导电带状线的传输线。整个形状可以是条形的(长,扁和薄),因此被称为条形电容器。微波传输线通常基本上沿矩形介电基板的整个长度延伸。
这种类型的器件的具体优点在于微波传输线并入了电感,以及提供针对介电基板的另一侧上的相对的金属化表面的电容。通过仔细地选择微波传输线的宽度和长度,以及它距离相对的金属化表面的间距和介电材料的介电常数,可以形成具有良好定义的每单位长度的电感和电容(或阻抗)的阻抗匹配元件。因为主要定义电感的微波传输线的长度被良好定义(由于它从介电基板的一个末端延伸到另一末端),因此电感被良好定义。此外,通过主要在条形电容器阵列,而不是在外部“集总”支路电容器中进行阻抗匹配,任何外部键合线的长度被显著减小。事实上,通常采用将分布式或条形电容器连结到晶体管所需的最小长度,并且该有限的键合线电感将被吸收到匹配网络中。这意味着,与条形电容器阵列(其主要部分是微带传输线)提供的整体电感相比,外部键合线的长度和附接点的轻微变化极小。
另一优点在于器件的介电基板可以通过介电常数高于诸如FR4或等的一般的PCB基板的材料制成。例如,在诸如使用GaAs的MMIC的单片环境中,单片基板的介电常数约为12.9。本实施方式的器件可以通过具有高于12.9的介电常数的高介电常数基板制成,例如13、20、30、40或更高的介电常数,并且在一些变型例中介电常数小于300。
该器件的某些实施方式可以在利用具有高介电常数的材料(如果单片电路环境被使用,例如MMIC,相对于那些通常被使用的材料,介电常数是高的)的(短)长度的传输线的方面来观察。该器件有效地使用有限长度的“微带”传输线来代替集总电容器,该传输线在其最简单的形式中可以被建模为采用串联电感器和支路电容器的单位元件的串行级联。“共面波导”或其他相似的传输线类型也可以被采用。本质上,总的线电容代替了集总电容,但是附加的好处是额外的“分布式”电感可以用在匹配解决方案中。事实上,传输线的阻抗被定义为每单位长度电感除以每单位长度电容的平方根,并且这也用在匹配解决方案中。以这种方式与具有高介电常数的基板(例如13、40或更高的介电常数,虽然在一些实施方式中介电常数不超过300)一起使用分离的或“分立”的传输线,较之平面集成电路(例如对于GaAs具有介电常数12.9)上能够实现的电容,允许使用每单位长度的较高的电容,并且导致更紧凑和更多样的阻抗变换网络。
在一些实施方式中,介电基板的一个主表面完全地或基本上完全地被金属化,而相对的主表面设置有具有微波传输线形式的平行的金属化轨道的阵列。
即使在可能的情况下,仍难于避免相邻微波传输带之间的耦合,但是如果能够可靠地确定耦合量,那么进行补偿是相对简单的。由于可以使用高精度技术将微波传输带印刷或光刻刻蚀或通过其他方式形成在介电基板上,以便均匀地和规则地隔开,因此耦合是可预测的。这与不能如此均匀地或规则地隔开的分别定位的键合线的阵列相反。
某些实施方式寻求将固有的和必要的键合线电感(连接到微波功率晶体管上的栅极和漏极连接)吸收到分立的微波宽带隙功率晶体管的前级和末级匹配网络之一(或两者)中的定制的高介电常数电容器阵列中。
与集总电容器和键合线对(图1)相反,条形电容器阵列(图2)有效地“吸收”所需的匹配电感并且显著减少线键合中所需的电感量,后者易受制造方差和公差的影响。使用精确的光刻技术可以制造条形电容器阵列,并且该条形电容器阵列的可重复性很高(或者可以被选择以具有规定的小的公差)并且减少了对更困难的键合线方法的高公差制造的依赖。
条形电容器阵列还可以利用范围广泛的高介电常数材料,以允许设计者设法使匹配阻抗最优化。此外,通过利用单个基板上的印刷的或刻蚀的电容器的“阵列”,输入和输出连接到功率晶体管的多个栅极和漏极的连接也可以被更好的控制—其包括施加到每个器件端子的电抗,并且还包括电容元件(其通常被分开组装)之间的电磁耦合。
以这种方式利用分布式或条形电容器阵列的整体效果在于,较之传统的集总元件或分立的芯片实现,改进了微波功率放大器的性能和制造产量。
预期该技术提供这种放大器的制造产量,导致成品的制造成本降低。此外,较之更传统的集总元件匹配技术,预期该技术还改进整体带宽性能。
某些实施方式的另外的优点在于,当在电路板基板上安装时,通过简单地对准接近微波功率晶体管边缘的条形电容器阵列的近端,容易组装具有可靠的和可再现的匹配性质的匹配网络。这可以在微波功率晶体管的栅极侧和漏极侧两者进行,并且进一步减小由于键合线长度不一引起的误差裕度。通过在连接到微波晶体管的漏极或栅极端子之前对准接近晶体管边缘的条形电容器阵列的近端,便利了微波传输线的正确取向,并且仅需要使用短的键合线将微带传输线连接到相关的晶体管端子。事实上,由于每个微带传输线的末端和它各自的晶体管端子之间的距离或多或少相同,因此可以使用相同长度的键合线。在一些实施方式中,可以使条形电容器阵列的近端与微波晶体管的边缘邻接,但是由于用于将元件放置和固定到电路板或其他基板上的方法,经常会有小的间隙。特别地,环氧树脂或焊料以及管芯处理夹头(die handling collets)的使用使得难于邻接条形电容器阵列的近端使得它们真正地接触晶体管元件的边缘。
在一些实施方式中,在功率晶体管和外部网络在同一介电基板上(例如在单片集成电路中)制造的情况下,中间阻抗变换器件可以以“倒装芯片”的方式被倒过来安装在功率晶体管和外部嵌入网络之间。在这种布置中,外部的键合线可以被“焊料凸点”、导电环氧树脂或预制导电轨道或者相似的连接方法代替,并且针对器件的接地面的附接可以通过器件内的导电过孔连接或者通过器件边缘上的“环绕式”连接来实现。
综上所述,本申请的实施例通过如下方式进行工作,将任何必须的键合线的电感吸收到介电基板上的精确制造的微波传输线的良好定义的串联电感中或者将其忽略,以及借助于相对的板或金属化来提供针对该串联电感的支路电容。通过使用介电常数高于MMIC和MIC实现中通常使用的基板的高介电常数的介电基板,获得每单位长度的改进的电容。通过这种方式,便利了与微波功率晶体管进行改进的阻抗匹配。
附图说明
以下参照附图进一步描述本发明的实施方式,其中:
图1是示出了现有技术的集总芯片电容器和外部键合线布置的示意图;
图2是示出了当前实施方式的分布式电感器电容器网络的示意图;
图3是另一实施方式的条形电容器阵列的示意图;以及
图4是当前实施方式的条形电容器阵列匹配网络和功率晶体管的示意图。
具体实施方式
图1示出了两个端口P1和P2之间的公知的阻抗变换布置。端口P1可以表示阻抗Z1的外部电路并且端口P2可以表示功率晶体管呈现的阻抗。这种布置与EP2197030中公开的阻抗变换布置相似。具有键合线1、2的形式的两个电感器将分立的或集总的电容器4分别连接到外部匹配网络和功率晶体管。第一键合线1将端口P1连接到集总电容器4的一个极板3和第二键合线2,第二键合线2将集总电容器4的极板3连接到端口P2。键合线1和5均被配置成电感器。通过选择适当的电感和电容性质,对于给定的信号频率,端口P1和P2处的阻抗可以互相匹配。然而,每个键合线1、2的电感主要取决于每个键合线的长度和配置,并且在某种程度上,取决于它的空间取向。当在显微镜下手动附接键合线时,难于控制到所期望的公差。即使在使用自动键合线的机器时,仍难于实现充分高程度的可重复性以便获得最可能的公差。
图2以示意性的形式示出了本申请的实施方式。这里,不同于图1中所示的集总电容器4,利用分布式电容器电感器网络或器件6。器件6以示意性的形式示出,并且等效于一连串良好定义的电感器7、8、9、10、11、12,其具有插入的到地的并联电容连接13、14、15、16、17。在实际的结构术语中,器件6包括长方形片的介电材料18作为基板,基板的金属化的底面作为接地面,并且微波传输线被印刷或刻蚀或以其他方式形成在相对的顶面上,微波传输线起串联电感器的作用。端口P1和P2通过键合线1、2仍然被连接到微波传输线的末端,但是这些键合线1、2仅形成整体电感器串的小部分,并且相应地键合线1、2的电感的任何变化对作为整体的器件6的整体电感的影响极小。
图3示出了本申请的实施方式,其包括印刷或刻蚀到具有高介电常数的介电基板(例如介电陶瓷材料)的矩形片32的顶表面上的通常平行的高导电的电容器带31(例如,微带传输线)的1x4的阵列30。片32的底面涂有高导电的接地面(未示出)。
图4示出了本申请的实施方式,其在微波功率晶体管41的输入侧40使用图2所示类型的1x4的第一阵列30,并且在晶体管41的输出侧42使用另一个1x4的阵列30’。每个阵列30、30’的近端33、33’与晶体管41的边缘对准,使得仅需要长度短的外部键合线43将每个电容器带31、31’连接到晶体管41上相关联的端子。每个阵列30、30’的远端34、34’面对晶体管41的任一侧的各自的网络图案,晶体管41在微波功率晶体管布置中是标准的,并且远端34、34’通过长度相对短的键合线44连接到网络图案。
虽然图4的实施方式示出了具有电容器带(微带传输线)31、31’的每个阵列30、30’,电容带31、31’在它们各自的介电基板32、32’的暴露面的最上面,但是在替选实施方式中可以将阵列30、30’倒过来安装。在在工业中被称为“倒装芯片”布置的这样的布置中,可以完全省去键合线,而依靠焊料凸点、导电环氧树脂和/或预制的导电轨道来形成从匹配网络穿过阵列30、30’到晶体管41的电连接。
在本说明书的描述和权利要求通篇中,词“包括”和“包含”以及它们的变化表示“包括但不限于”,并且它们并非旨在(并且绝不)排除其他的部分、添加物、元件、整体或步骤。在本说明书的描述和权利要求通篇中,否则单数涵盖复数。特别地,除非上下文另有所指,在使用不定冠词的情况下,本说明书应当理解为考虑复数和单数。
与本发明的特定方面、实施方式或示例相结合描述的特征、整体、特性、化合物、化学成分或化学基团应当理解为可应用于本文描述的任何其他方面、实施方式或示例,除非与其不相容。本说明书(包括任何所附权利要求、摘要和附图)中公开的所有特征,和/或这样公开的任何方法或处理的所有步骤,可以在任何组合中被组合,除了至少一些这样的特征和/或步骤互相排斥的组合以外。本发明不限于任何上述实施方式的细节。本发明延伸至本说明书(包括任何所附权利要求、摘要和附图)中公开的特征的任何新型的特征或任何新型的组合,或者延伸至这样公开的任何方法或处理的步骤的任何新型的步骤或任何新型的组合。
读者关注于与本申请所结合的说明书同时提交或在先提交的并且同本说明书一起向公众开放查阅的所有论文和文献,并且所有这样的论文和文献的内容通过引用合并于此。
Claims (21)
1.一种用于微波功率晶体管的中间阻抗变换器件,所述器件包括:
介电基板,其承载或包含多个伸长的微波传输线,每个微波传输线具有长度且延伸越过或穿过所述基板,每个微波传输线具有第一末端和第二末端、每单位长度的预定的串联电感以及与电隔离导电板或层相结合的每单位长度的预定的支路电容,使得每个长度的微波传输线与所述导电板或层一起具有预定的特征阻抗和相位常数;
所述器件被配置成使得,当具有相关联的阻抗的指定的最小实际长度的键合线连接在一个微波传输线的末端和微波功率晶体管之间时,所述键合线的阻抗被吸收到所述微波传输线的每单位长度的阻抗中。
2.如权利要求1所述的器件,其中,所述介电基板具有大于13,优选地大于40的介电常数。
3.如权利要求1或2所述的器件,其中,每个微波传输线是导电的微带传输线。
4.如权利要求1或2所述的器件,其中,每个微波传输线是共面波导。
5.如权利要求1或2所述的器件,其中,每个微波传输线是导电带状线的传输线。
6.如前面任一项权利要求所述的器件,包括大体上是长方形片的介电基板,所述介电基板具有第一主表面和第二相对主表面,所述第一表面被金属化,而所述第二表面承载至少一个越过其延伸的微波传输线。
7.如前面任一项权利要求所述的器件,其中,所述介电基板设置有越过其延伸或者穿过其延伸的多个基本上平行的微波传输线。
8.如前面任一项权利要求所述的器件,其中,每个微波传输线引起相同的预定的电感和相位常数。
9.如权利要求1到7中任一项所述的器件,其中,所述微波传输线被配置成引起不同的预定的电感和相位常数。
10.一种与微波功率晶体管结合的阻抗变换布置,所述阻抗变换布置包括在具有第一介电常数的第一介电基板上形成的匹配网络以及至少一个如权利要求1到7中任一项所述的中间阻抗变换器件。
11.如权利要求10所述的布置,其中,所述阻抗变换器件的介电基板具有大于所述第一介电常数的介电常数。
12.如权利要求10或11所述的布置,其中,至少一个器件是这样的器件的阵列的一部分。
13.如权利要求10到12中任一项所述的布置,其中,至少一个器件位于所述晶体管的栅极端子或输入侧。
14.如权利要求10到12中任一项所述的布置,其中,至少一个器件位于所述晶体管的漏极端子或输出侧。
15.如权利要求10到12中任一项所述的布置,其中,至少一个器件位于所述晶体管的栅极端子或输入侧,以及其中,至少一个器件位于晶体管的漏极端或输出侧。
16.如权利要求10到15中任一项所述的布置,其中,所述微波传输线或每个微波传输线具有第一末端和第二末端,以及其中,所述第一末端通过长度短于所述微波传输线的连接被电连接到所述晶体管。
17.如权利要求10到16中任一项所述的布置,其中,至少一个器件的一个末端基本上平行于所述晶体管的输入侧或输出侧。
18.一种与微波功率晶体管进行阻抗匹配的方法,其中,多个微波传输线通过键合线被连接,每个键合线对所述晶体管的栅极端子或漏极端子具有阻抗,所述微波传输线延伸越过或穿过介电基板,每个微波传输线具有预定的串联电感以及与电隔离导电板或层相结合的预定的支路电容,使得每个微波传输线与所述导电板或层一起具有预定的特征阻抗和相位常数,以及其中,每个键合线的阻抗被吸收到其连接的微波传输线的阻抗中。
19.一种基本上参照附图2到4描述的或者如附图2到4所示的用于微波功率晶体管的中间阻抗变换器件。
20.一种基本上参照附图2到4描述的或者如附图2到4所示的阻抗变换布置。
21.一种基本上参照附图2到4描述的或者如附图2到4所示的与微波功率晶体管进行阻抗匹配的方法。
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GBGB1105912.8A GB201105912D0 (en) | 2011-04-07 | 2011-04-07 | Improved matching techniques for power transistors |
PCT/EP2012/056202 WO2012136719A1 (en) | 2011-04-07 | 2012-04-04 | Improved matching techniques for wide-bandgap power transistors |
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CN108763703A (zh) * | 2018-05-18 | 2018-11-06 | 上海交通大学 | 一种基于阶梯阻抗传输线的键合线阻抗匹配方法 |
CN113838824A (zh) * | 2021-08-25 | 2021-12-24 | 北京普能微电子科技有限公司 | 功率放大器芯片 |
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GB201323159D0 (en) * | 2013-12-31 | 2014-02-12 | Diamond Microwave Devices Ltd | Improved matching techniques for wide-bandgap power transistors |
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JP6658429B2 (ja) * | 2016-09-27 | 2020-03-04 | 三菱電機株式会社 | 半導体装置 |
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Also Published As
Publication number | Publication date |
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EP2695191A1 (en) | 2014-02-12 |
US9799599B2 (en) | 2017-10-24 |
GB2504421B (en) | 2015-11-18 |
GB2504421A (en) | 2014-01-29 |
GB2489814B (en) | 2015-09-02 |
GB2489814A (en) | 2012-10-10 |
US20150041914A1 (en) | 2015-02-12 |
GB201105912D0 (en) | 2011-05-18 |
GB201206045D0 (en) | 2012-05-16 |
GB201319568D0 (en) | 2013-12-18 |
JP2014512135A (ja) | 2014-05-19 |
WO2012136719A1 (en) | 2012-10-11 |
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