CN103681452B - 沟渠绝缘工艺 - Google Patents

沟渠绝缘工艺 Download PDF

Info

Publication number
CN103681452B
CN103681452B CN201210378608.9A CN201210378608A CN103681452B CN 103681452 B CN103681452 B CN 103681452B CN 201210378608 A CN201210378608 A CN 201210378608A CN 103681452 B CN103681452 B CN 103681452B
Authority
CN
China
Prior art keywords
ditches
sidewall
irrigation canals
trench insulation
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201210378608.9A
Other languages
English (en)
Other versions
CN103681452A (zh
Inventor
林永发
张家豪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anpec Electronics Corp
Original Assignee
Anpec Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anpec Electronics Corp filed Critical Anpec Electronics Corp
Publication of CN103681452A publication Critical patent/CN103681452A/zh
Application granted granted Critical
Publication of CN103681452B publication Critical patent/CN103681452B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

本发明公开了一种沟渠绝缘工艺。首先提供一基底，其上设有一垫层以及一硬掩膜层；于所述硬掩膜层上形成至少一开口、经由所述开口刻蚀基底，以形成一第一沟渠、于所述第一沟渠的侧壁上形成一侧壁子；经所述第一沟渠刻蚀基底，于所述第一沟渠下方形成一第二沟渠、进行一热氧化工艺，以利用所述侧壁子作为一保护层来氧化所述第二沟渠内的基底，直到第二沟渠被一氧化层填满、移除所述侧壁子以裸露出第一沟渠的侧壁；于裸露出来的所述第一沟渠侧壁上形成一衬层、以及进行一化学气相沉积工艺来沉积一介电层，以填满所述第一沟渠。

Description

沟渠绝缘工艺
技术领域
本发明大体上关于一种半导体工艺技术领域，特别是一种沟渠绝缘工艺，其利用侧壁子工艺及/或热氧化技术来达到无孔隙的沟渠充填效果。
背景技术
在集成电路的应用中，不同的功能元件常被建构于单一芯片上，为了确保每个独立的元件可以不被周围其它元件所干扰，因此元件之间的电性隔绝显得特别重要。
区域性硅氧化(localoxidationofsilicon,LOCOS)技术是早期半导体工艺中常见的隔绝方法，其具有工艺简单以及低成本的优点，但随着工艺能力的进步以及元件的微缩，因LOCOS工艺造成的鸟嘴状结构以及场氧化层变薄等问题变得更为严重，因此，业界后续发展出浅沟渠绝缘(shallowtrenchisolation,STI)工艺來解决上述LOCOS工艺所造成的问题。
STI工艺作法是挖出沟渠后填入绝缘材料来隔绝有源区域，其虽可克服LOCOS的缺点，但也会有抛光浅碟凹陷(dishing)以及次启始电压突增(sub-thresholdkink)等固有问题要克服，且随着元件尺寸不断微缩，要做到无孔隙的沟渠填入品质变得更加困难。
发明内容
因此，本发明的目的即在于提供一种改良的沟渠绝缘工艺，其配合侧壁子工艺及/或热氧化工艺来达成沟渠填入的功效，而不会增加整体工艺的复杂度。
根据本发明一实施例，其提供了一种沟渠绝缘工艺，其步骤包含有：提供一基底，其上设有一垫层以及一硬掩膜层、于所述硬掩膜层形成至少一开口、经由所述开口刻蚀基底，以形成一第一沟渠、于所述第一沟渠的侧壁上形成一侧壁子、经所述第一沟渠刻蚀基底，以于所述第一沟渠下方形成一第二沟渠、进行一热氧化工艺，以利用所述侧壁子作为一保护层来氧化所述第二沟渠内的基底，直到所述第二沟渠被一氧化层填满、移除所述侧壁子，以裸露出第一沟渠的侧壁、于裸露出来的第一沟渠侧壁上形成一衬层、以及进行一化学气相沉积工艺来沉积一介电层，以填满所述第一沟渠。
根据本发明另一实施例，其提供了一种沟渠绝缘工艺，其步骤包含有：提供一基底，其上设有一垫层以及一硬掩膜层、于所述硬掩膜层形成至少一开口、于所述开口的侧壁上形成一侧壁子、经由所述开口刻蚀基底，以形成一沟渠、以及进行一热氧化工艺，以利用所述侧壁子作为一保护层来氧化所述沟渠内的基底，直到沟渠被一氧化层填满。
根据本发明又一实施例，其提供了一种沟渠绝缘工艺，包含有：提供一基底，其上设有一垫层以及一硬掩膜层、于所述硬掩膜层形成至少一开口、经由所述开口刻蚀基底直至一预定深度，以形成一凹陷区域、于所述开口的侧壁上形成一侧壁子、经由所述开口以及所述凹陷区域刻蚀基底，以形成一沟渠、以及进行一热氧化工艺，以利用所述侧壁子作为一保护层来氧化所述沟渠内的基底，直到所述沟渠被一氧化层填满。
为让本发明的上述目的、特征及优点能更为明显易懂，下文中特举数个优选实施方式，并配合附图作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明之用，其并非是用来对本发明加以限制。
附图说明
图1至图4为依据本发明一实施例所绘示的沟渠绝缘工艺示意图。
图5至图7为依据本发明另一实施例所绘示的沟渠绝缘工艺的示意图。
图8至图10为依据本发明又一实施例所绘示的沟渠绝缘工艺的示意图。
其中，附图标记说明如下：
10基底20氧化衬层
12硅氧垫层22介电层
14硬掩膜层102第一沟渠
14a开口104第二沟渠
16侧壁子114沟渠
18氧化层122凹陷区域
18a楔形凹陷结构124沟渠
18b鸟嘴状结构AA有源区域
具体实施方式
请参阅图1至图4，其为依据本发明一实施例所绘示的沟渠绝缘工艺的示意图。首先，如图1所示，提供一基底10，如一半导体基底，接着于基底10表面形成一硅氧垫层12以及一硬掩膜层14，如一氮化硅层。硬掩膜层14也可以是一多层结构，如一氮化硅层加上一硅氧层。然后利用光刻工艺于硬掩膜层14形成开口14a，图案化厚的硬掩膜层14以定义出有源区域AA的位置。再以硬掩膜层14为刻蚀掩膜，经由开口14a刻蚀硅氧垫层12以及基底10直到一第一预定深度，以形成一第一沟渠102。
如图2所示，接着于第一沟渠102的侧壁上形成侧壁子16，如一氮化硅侧壁子。形成侧壁子16方法，如先沉积一均厚的氮化硅层覆盖住硬掩膜层16，并顺应地覆盖住第一沟渠102的侧壁及底部，再以各向异性刻蚀工艺回刻蚀所述氮化硅层。接下来再进行一干刻蚀工艺，以利用侧壁子16作为刻蚀掩膜来继续经由第一沟渠102刻蚀基底10至一第二预定深度，如此会在第一沟渠102下方形成一第二沟渠104。第二沟渠104的开口宽度大小可以借由侧壁子16的厚度來控制。
如图3所示，接着进行一热氧化工艺，例如在温度介于800-1200℃，以水蒸气、氧气，或内含少量氯化氢或氮气的水蒸气或氧气，以及工艺压力介于600-760托(torr)的条件下，利用侧壁子16作为保护层来氧化第二沟渠104内的基底10，直到第二沟渠104最后被氧化层18填满，而在氧化层18表面上留下楔形凹陷结构18a。
如图4所示，接着移除侧壁子16以裸露出第一沟渠102的侧壁，再进行一氧化工艺于裸露出来的第一沟渠102侧壁上形成一氧化衬层20。随后，再进行一化学气相沉积(CVD)工艺全面性地沉积一介电层22，如一硅氧层，使介电层22填满第一沟渠102。由于第二沟渠104已为氧化层18所填满而降低了其深宽比，故后续以CVD工艺填充第一沟渠102时的工艺裕度较高，进而达到高质量、无孔隙的沟渠充填。
请参阅图5至图7，其为依据本发明另一实施例所绘示的沟渠绝缘工艺的示意图。首先，如图5所示，同样提供一基底10，如一半导体基底，接着于基底10表面形成一硅氧垫层12以及一硬掩膜层14，如一氮化硅层。硬掩膜层14也可以是一多层结构，如一氮化硅层加上一硅氧层。然后利用光刻工艺于硬掩膜层14上形成开口14a。
如图6所示，接着于开口14a的侧壁上形成侧壁子16，如一氮化硅侧壁子。形成侧壁子16方法，如先沉积一均厚的氮化硅层覆盖住硬屏蔽层16，并顺应地覆盖住开口14a的侧壁及底部，再以各向异性刻蚀工艺回刻蚀所述氮化硅层。接下来再进行一干刻蚀工艺，利用侧壁子16作为刻蚀掩膜来继续经由开口14a刻蚀基底10至一预定深度，如此会在开口14a下方形成一沟渠114，其开口宽度大小可以借由侧壁子16的厚度来控制，例如，侧壁子16的厚度可以小于开口14a宽度的四分之一。
如图7所示，进行一热氧化工艺，例如，在温度介于800-1200℃，以水蒸气、氧气，或内含少量氯化氢或氮气的水蒸汽或氧气，以及工艺压力介于600-760托的条件下，利用侧壁子16作为保护层来氧化基底10，直到沟渠114最后被氧化层18填满，而在氧化层18表面上留下楔形凹陷结构18a，同时产生轻微的鸟嘴状结构18b。此实施例是利用氮化硅侧壁子的厚度来缩减绝缘沟渠的宽度，以提高电路集成度。
请参阅图8至图10，其为依据本发明又一实施例所绘示的沟渠绝缘工艺的示意图。首先，如图8所示，同样提供一基底10，如一半导体基底，接着再于基底10表面形成一硅氧垫层12以及一硬掩膜层14，如一氮化硅层。硬掩膜层14也可以是一多层结构，如一氮化硅层加上一硅氧层。然后利用光刻工艺于硬掩膜层14形成开口14a，继而经由开口14a刻蚀基底10至一第一预定深度(小于0.2微米)，如此以形成一凹陷区域122。
如图9所示，接着于开口14a的侧壁上形成侧壁子16，如氮化硅侧壁子。形成侧壁子16方法为，例如先沉积一均厚的氮化硅层覆盖住硬掩膜层16，并顺应地覆盖住开口14a的侧壁及底部，再以各向异性刻蚀工艺回刻蚀所述氮化硅层。接下来再进行一干刻蚀工艺，以利用侧壁子16作为刻蚀掩膜来继续经由开口14a以及凹陷区域122刻蚀基底10至一第二预定深度，如此以形成一沟渠124，其开口宽度大小可以借由侧壁子16的厚度来控制。
如图10所示，接着进行一热氧化工艺，例如在温度介于800-1200℃，以水蒸气、氧气，或内含少量氯化氢或氮气的水蒸气或氧气，以及工艺压力介于600-760托的条件下，利用侧壁子16作为保护层来氧化基底10，直到沟渠124最后被氧化层18填满，而在氧化层18表面上留下楔形凹陷结构18a，同时产生轻微的鸟嘴状结构18b。相较于图7，由于有凹陷区域122的存在，使得侧壁子16可以保护住有源区域的转角处，故图10中的鸟嘴状结构18b较不明显，也较不易伸入有源区域，因此更能有效的利用有源区域的面积。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (13)

1.一种沟渠绝缘工艺，其特征在于，包含：
提供一基底，其上设有一垫层以及一硬掩膜层；
于所述硬掩膜层形成至少一开口；
经由所述开口刻蚀所述基底，以形成一第一沟渠；
于所述第一沟渠的侧壁上形成一侧壁子；
经所述第一沟渠刻蚀所述基底，以于所述第一沟渠下方形成一第二沟渠；
进行一热氧化工艺，利用所述侧壁子作为一保护层来氧化所述第二沟渠内的所述基底，形成一仅位于所述第二沟渠内的一氧化层，直到所述第二沟渠被所述氧化层填满；
移除所述侧壁子，以裸露出所述第一沟渠的侧壁；
于裸露出來的所述第一沟渠侧壁上形成一衬层；以及
进行一化学气相沉积工艺来沉积一介电层，以填满所述第一沟渠。
2.根据权利要求1所述的沟渠绝缘工艺，其特征在于，所述垫层是一硅氧垫层。
3.根据权利要求1所述的沟渠绝缘工艺，其特征在于，所述侧壁子是一氮化硅层。
4.根据权利要求1所述的沟渠绝缘工艺，其特征在于，所述热氧化工艺是在温度介于800-1200℃，以水蒸气、氧气，或内含氯化氢或氮气的水蒸气或氧气，在工艺压力介于600-760托的条件下进行。
5.根据权利要求1所述的沟渠绝缘工艺，其特征在于，所述第二沟渠的开口宽度大小是通过所述侧壁子的厚度来控制。
6.根据权利要求1所述的沟渠绝缘工艺，其特征在于，所述衬层是一氧化衬层。
7.根据权利要求1所述的沟渠绝缘工艺，其特征在于，所述氧化层表面具有一楔形凹陷结构。
8.一种沟渠绝缘工艺，其特征在于，包含：
提供一基底，其上设有一垫层以及一硬掩膜层；
于所述硬掩膜层形成至少一开口；
于所述开口的侧壁上形成一侧壁子；
经由所述开口刻蚀所述基底，以形成一沟渠；以及
进行一热氧化工艺，以利用所述侧壁子作为一保护层来氧化所述沟渠内的所述基底以形成一氧化层，直到所述沟渠被所述氧化层填满。
9.根据权利要求8所述的沟渠绝缘工艺，其特征在于，所述垫层是一硅氧垫层。
10.根据权利要求8所述的沟渠绝缘工艺，其特征在于，所述侧壁子是一氮化硅层。
11.根据权利要求8所述的沟渠绝缘工艺，其特征在于，所述热氧化工艺是在温度介于800-1200℃，以水蒸气、氧气，或内含氯化氢或氮气的水蒸气或氧气，在工艺压力介于600-760托的条件下进行。
12.根据权利要求8所述的沟渠绝缘工艺，其特征在于，所述侧壁子的厚度小于所述开口的宽度的四分之一。
13.根据权利要求8所述的沟渠绝缘工艺，其特征在于，所述氧化层表面具有一楔形凹陷结构。
CN201210378608.9A 2012-08-28 2012-10-09 沟渠绝缘工艺 Expired - Fee Related CN103681452B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW101131197 2012-08-28
TW101131197A TWI470733B (zh) 2012-08-28 2012-08-28 溝渠絕緣製程

Publications (2)

Publication Number Publication Date
CN103681452A CN103681452A (zh) 2014-03-26
CN103681452B true CN103681452B (zh) 2016-04-20

Family

ID=50188129

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210378608.9A Expired - Fee Related CN103681452B (zh) 2012-08-28 2012-10-09 沟渠绝缘工艺

Country Status (3)

Country Link
US (2) US8846489B2 (zh)
CN (1) CN103681452B (zh)
TW (1) TWI470733B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9711646B2 (en) 2014-03-31 2017-07-18 United Microelectronics Corp. Semiconductor structure and manufacturing method for the same
US9385030B2 (en) 2014-04-30 2016-07-05 Globalfoundries Inc. Spacer to prevent source-drain contact encroachment
CN105448807B (zh) * 2015-11-20 2017-11-10 浙江正邦电子股份有限公司 一种半导体器件芯片对通隔离制造工艺
US9449921B1 (en) * 2015-12-15 2016-09-20 International Business Machines Corporation Voidless contact metal structures
US20210351066A1 (en) * 2017-12-29 2021-11-11 United Microelectronics Corp. Semiconductor device and method for fabricating the same
CN110911342A (zh) * 2018-09-14 2020-03-24 长鑫存储技术有限公司 浅沟槽隔离结构及其制备方法
CN111799329A (zh) * 2019-04-08 2020-10-20 三星电子株式会社 半导体器件
CN113782484A (zh) * 2021-11-11 2021-12-10 广州粤芯半导体技术有限公司 半导体器件的制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6018174A (en) * 1998-04-06 2000-01-25 Siemens Aktiengesellschaft Bottle-shaped trench capacitor with epi buried layer
US6251750B1 (en) * 1999-09-15 2001-06-26 United Microelectronics Corp. Method for manufacturing shallow trench isolation
US7470588B2 (en) * 2005-09-22 2008-12-30 Samsung Electronics Co., Ltd. Transistors including laterally extended active regions and methods of fabricating the same
TW200926353A (en) * 2007-07-13 2009-06-16 Marvell World Trade Ltd Method for shallow trench isolation
US7745904B2 (en) * 2005-03-10 2010-06-29 Taiwan Semiconductor Manufacturing Company Shallow trench isolation structure for semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6146970A (en) * 1998-05-26 2000-11-14 Motorola Inc. Capped shallow trench isolation and method of formation
KR100593673B1 (ko) * 2004-10-27 2006-06-28 삼성전자주식회사 반도체 장치의 제조 방법 및 이를 이용한 반도체 장치의 소자 분리막 제조 방법
US7465642B2 (en) * 2005-10-28 2008-12-16 International Business Machines Corporation Methods for forming semiconductor structures with buried isolation collars
US20080048186A1 (en) * 2006-03-30 2008-02-28 International Business Machines Corporation Design Structures Incorporating Semiconductor Device Structures with Self-Aligned Doped Regions

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6018174A (en) * 1998-04-06 2000-01-25 Siemens Aktiengesellschaft Bottle-shaped trench capacitor with epi buried layer
US6251750B1 (en) * 1999-09-15 2001-06-26 United Microelectronics Corp. Method for manufacturing shallow trench isolation
US7745904B2 (en) * 2005-03-10 2010-06-29 Taiwan Semiconductor Manufacturing Company Shallow trench isolation structure for semiconductor device
US7470588B2 (en) * 2005-09-22 2008-12-30 Samsung Electronics Co., Ltd. Transistors including laterally extended active regions and methods of fabricating the same
TW200926353A (en) * 2007-07-13 2009-06-16 Marvell World Trade Ltd Method for shallow trench isolation

Also Published As

Publication number Publication date
CN103681452A (zh) 2014-03-26
US20140065795A1 (en) 2014-03-06
TW201409611A (zh) 2014-03-01
TWI470733B (zh) 2015-01-21
US20140087540A1 (en) 2014-03-27
US8846489B2 (en) 2014-09-30

Similar Documents

Publication Publication Date Title
CN103681452B (zh) 沟渠绝缘工艺
CN103400794B (zh) 自对准沟槽的形成方法
CN102760736A (zh) 半导体器件及其制造方法
CN109244075A (zh) 3d存储器件的制造方法
KR100590383B1 (ko) 반도체 소자의 소자분리막 형성방법
CN105161450A (zh) 一种双浅沟槽隔离形成方法
CN102339783A (zh) 半导体装置的元件隔离结构及其形成方法
CN104078412B (zh) 浅沟槽隔离工艺
CN104465728B (zh) 分离栅功率器件的栅极结构及工艺方法
CN103227143B (zh) 浅沟槽隔离工艺
CN102130036B (zh) 浅沟槽隔离结构制作方法
US6103581A (en) Method for producing shallow trench isolation structure
CN108470709A (zh) 浅沟槽绝缘结构的制造方法
CN208873722U (zh) 3d存储器件
CN108417527A (zh) 自对准接触孔的形成方法
CN104517886A (zh) 一种浅沟槽隔离结构的形成方法
US8765575B2 (en) Shallow trench forming method
KR20080001269A (ko) 소자 분리막을 포함하는 반도체 소자 및 그것의 형성 방법
JP2009117799A (ja) 半導体メモリ素子の素子分離膜形成方法
KR20010008607A (ko) 반도체장치의 소자분리막 형성방법
KR100550635B1 (ko) 반도체소자 및 그의 제조 방법
TWI322457B (en) Method for manufacturing shallow trench isolation structure and semiconductor structure
CN100520596C (zh) 一种在cob-dram制造中提高sac刻蚀制程容许度的方法
KR100881414B1 (ko) 반도체 소자의 소자분리막 형성방법
KR101161661B1 (ko) 반도체 소자의 소자분리막 형성방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20160420

Termination date: 20181009