1322457 15872twf.doc/006 九、發明說明： 【發明所屬之技術領域】 本發明乃是關於一種積體電路製造技術，特別是關於 一種形成積體電路元件中所採用的改進淺渠溝隔離結構。 【先前技術】 在積體電路製造領域中’在追求更小之積體電路尺寸 的潮流下，已能夠在一般基底上封裝出更高密度、更小的 電子元件。在積體電路的應用領域中，常使用的電子元件 包括有主動元件(active device)如電晶體等，以及被動元件 (passive device)如電阻和電容器等。一般來說，高密度封 裝的電子7G件的可靠性乃是部分地取決於是否能夠爲積體 電路中的相接元件提供足夠的電性隔離。 習知的-種爲相接的元件提供電性隔離的方法是形成 ^^^ft^b(local oxidization of silicon, LOCOS)^# 〇 =LOCOS結構卿成方法是將不可氧化的罩幕(咖⑻如 氮化石夕⑸洲)沉積在空白石夕晶圓（blank仙咖_社。用 ==罩幕形成，然後在被暴露⑽表面部分(利用 开广:氧化矽_2)臈。該氧化膜的作用是將 的元離的方法是在基底上 結構。典型的STI結構形成 區域之間的基—淺渠溝，然後== 5 15872twfdoc/006 絕緣t料，如二氧化矽或其他介電材料。當淺渠溝被注滿 後’採用化學機械研磨(Chemicai mechanical⑽吨CMp) 技術而平坦化晶圓表面，而使絕緣材料保留在淺渠溝中， 其中淺渠溝之頂面與暴露的基底之頂面切齊。被“埋入，， 的絕緣材料爲形成於暴露基底之内或之上的相接元件之間 提供電性隔離。一般用於注滿STI淺渠溝的材料是氧化 物，其可採用高密度電漿之化學氣相沉積(high density plasma chemical vapor deposition，HDP-CVD)技術而沉積 一層該氧化物薄膜。 儘官LOCOS結構在某些應用中能夠提供有效的電性 隔離’但是LOCOS技術仍存在嚴重的局限。例如，L〇c〇s 結構在基底表面上耗費大量的矽之主動面積，而減少了可 用於形成電子元件的面積。此外，由於L〇c〇s結構具有 不平的表面輪廓(topology)，對其製程的產出量 yield)和後續的基底處理製程的複雜度都會産生不利影 響。還有，在習知的LOCOS方法中，氮化矽罩幕下面的 石夕容易發生橫向氧化(lateral oxidation)，而在已經形成的氧 化層邊緣形成“鳥嘴(brid’s beak)，，結構。 同樣地’習知的STI技術也存在一些缺陷。例如，隨 著STI渠溝寬度的減少，填注渠溝的絕緣材料的寬度也相 對地減少。如果填入渠溝之絕緣材料造成過高的埋置應力 (embedded stress)而使矽晶格產生差排(dislocati〇n)，便會有 額外的漏電流產生也使得此絕緣材料能夠提供有效電性隔 離的能力隨之降低。特別是，使用各種習知技術所形成的 1322457 15872twf.doc/006 寬度小於大約1800A的STI渠溝，其提供之相接元件之間 電性隔離的能力將嚴重下降^差排通常是在3Ή渠溝結構 的形成過程中，由施加在基底和/或絕緣材料上之機械或熱 應力所造成的。 如上所述，由於填充渠溝的絕緣材料的埋置應力產生 差排導致STI渠溝所提供之充分電性隔離的能力受到損 害。此差排通常是由於STI渠溝結構所導致的機械和熱應 力造成的。圖1疋習知STI結構的剖面示意圖，從圖中可 • 以看出機械和熱應力所造成的影響。圖1中所示的結構包 括石夕基底100，其具有形成於其上的二氧化^夕層ι〇2和氮 化矽層104。蝕刻出一渠溝108並穿透氧化物和氮化物層 而進入基底100。利用習知的氧化技術，例如乾的或濕的 熱氧化法以在渠溝108表面上形成侧壁氧化層1〇6。當其 後b溝108填注滿絕緣材料時（例如使用高密度電襞·化學 氣相沉積法(HDP-CVD)技術），此時側壁氧化層1〇6將有 助於減少絕緣層内的應力。 • 圖1所不之習知STI渠溝結構的實施例具有許多缺 點。例如’氧化物侵餘(oxide encroachment)結構1〇7，通 常也被稱爲“鳥嘴(bird’s beak)，，結構，其形成於當η2〇與 〇2擴散到矽基底100和二氧化矽層1〇2之間的介面時。侵 钱結構107是使元件活性面積(active area)縮小而致特性損 失的原因之一。此外，STI渠溝底部的尖銳角落11〇也將 導致填注渠溝108的絕緣材料内産生很高的埋置應力，這 是差排所産生的原因之一。在某些製程條件中，渠溝的角 7 1322457 15872twf.doc/006 洛110處的蝕刻略深於渠溝108的中心，使得角落lio更 爲尖銳’尤其是在形成側壁氧化層1〇6之後。如此，將更 進一步地增加了埋置應力。如上所述，這些埋置應力所造 成的差排將導致漏電電流’進而降低了鄰近的被渠溝1〇8 所分隔的主動元件的可靠性。 降低STI渠溝填充絕緣材料的埋置應力的方法之一是 繼續再沉積一層具有張應力（tensile stress)和壓應力 (compressive stress)的另一層絕緣材料。理論上這另一層絕 緣材料會平衡整個絕緣體中的整體結構應力。然而，在實 際製程中，若要採用此一技術而將結構應力降低到能夠使 整個絕緣體中的埋置應力有效地減少是非常因難或者是不 ，由於沉積了多層絕緣材料，對後續的用於 2體電路之平坦表面的化學機械研磨 的精確控制將變得十分困難。 降低STI渠溝填充絕緣材料内埋置應力的另一方法θ 填充渠溝後進行高溫退火(anneal) 疋 ，應力並由此降低沉積在渠溝内的絕： :然而，在隔離渠溝的表面上具有 丄: ，中，此退火步驟將會產生不利地該側=06 = ?力，這種熱應力又是產生絕 匕層=的熱 【發明内容】 徘的另一原因。 由於上述原因，本發明提 通半導體基底上的高密度封裝;二性隔離在普 施例中，STi結構提供 方法》在某些實 已修正的回形輪靡，可降低在 8 1322457 15872twf.doc/006 離的元件類型。例如，在快閃記憶體(flash memory)的應用 設備中，渠溝通常介於大約2500人到大約4500人之間。為 了分隔邏輯裝置（例如為金屬氧化半導體(MOS)之電晶 體）’其渠溝通常介於大約2000A到大約4000A之間。在 一貫施例中’可藉由非等向性钱刻(anisotropic etching)法而 形成渠溝’例如為一反應性離子银刻(reactive ion etching) 法，至於其他蝕刻法則用於其他實施例。 然後’在钱刻渠溝208上均厚地(conformally)沉積一 鲁 層薄的、均厚的氮化石夕層212❶在一實施例中，均厚的氮 化矽層212具有大約25A到大約300A之間的厚度，在另 一實施例中’均厚的氮化矽層212具有大約3〇A到大約 2〇〇A之間的厚度，在又一實施例中，均厚的氮化矽層212 具有大約50人到大約150A之間的厚度，在一實施例中， 均厚的氮化矽層212具有大約75A到大約125A之間的厚 度。在一實施例中，氮化矽層212具有大約均一厚度，順 著渠溝208之形狀蓋於渠溝2〇8的直立、水平部及角落部。' • 在這些實施例中，然後，藉由現場蒸汽産生(in situ steam generation，ISSG)氧化技術而選擇性地將氮化石夕層212氧 化，其中能夠進行ISSG氧化製程的處理工具(pr嶋麵 tool)例如使用應用材料公司（在Santa Qara, CA)於市場上 所推出的Centura® 5_系統。在卫跑波中―，渠溝雇 f部-角農上的氮化石夕與渠溝施中其他部分（直立和水平 部，）的』U窆鮮較_氧化速率。因此， 在氧化渠溝208之底部角落的氮化石夕所使用❾時間中，不 1322457 15872twf.doc/006 分的氮化石夕也會被氧化，而且位於其 = := 200也會部分地氧化。由於 Γ中=生而=^8中不同的表面氧化，因此在渠溝 是，cm度的側壁氧化層，如圖3所示。特別 tf，立和水平部射姆較大的厚度 而在渠溝208的角落部具有相對較小的厚产t2。 和渠溝中之不同部分‘化石夕沉積 考氧化（知:用ISSG法）的相對速率。PRODUCTION OF THE INVENTION The present invention relates to an integrated circuit manufacturing technique, and more particularly to an improved shallow trench isolation structure used in forming an integrated circuit component. [Prior Art] In the field of integrated circuit manufacturing, in the pursuit of a smaller integrated circuit size, it has been possible to package higher density and smaller electronic components on a general substrate. In the field of application of integrated circuits, commonly used electronic components include active devices such as transistors and the like, as well as passive devices such as resistors and capacitors. In general, the reliability of high density packaged electronic 7G components depends in part on the ability to provide adequate electrical isolation for the connected components in the integrated circuit. The conventional method of providing electrical isolation for the connected components is to form ^^^ft^b(local oxidization of silicon, LOCOS)^# 〇=LOCOS structure is a non-oxidizable mask (coffee) (8) If the nitrite shi (5) continent is deposited on the blank Shixi wafer (blank xian _ _. Use the == mask to form, and then exposed (10) surface part (using Kaiguang: yttrium oxide_2) 该. The function of the membrane is to separate the element by the structure on the substrate. The typical STI structure forms the base between the regions - shallow trenches, then == 5 15872twfdoc/006 Insulation material such as cerium oxide or other dielectric Material. When the shallow trench is filled, 'Chemicai mechanical (10) ton CMp) technology is used to planarize the wafer surface, leaving the insulating material in the shallow trench, where the top surface of the shallow trench is exposed The top surface of the substrate is aligned. The "buried" insulating material provides electrical isolation between the contact elements formed in or on the exposed substrate. The material typically used to fill the STI shallow trench is oxidized. High-density plasma chemical vapor deposition (high density plasm) A chemical vapor deposition (HDP-CVD) technique is used to deposit a layer of the oxide film. The LOCOS structure can provide effective electrical isolation in some applications', but the LOCOS technology still has serious limitations. For example, L〇c〇 The s structure consumes a large amount of active area of the crucible on the surface of the substrate, and reduces the area available for forming electronic components. Furthermore, since the L〇c〇s structure has an uneven surface topology, the throughput of the process is increased. The yield and subsequent complexity of the substrate processing process can have an adverse effect. Also, in the conventional LOCOS method, the smectite under the tantalum nitride mask is prone to lateral oxidation, but has been formed. The edge of the oxide layer forms a "brid's beak," structure. Similarly, the conventional STI technology has some drawbacks. For example, as the width of the STI trench is reduced, the width of the insulating material filling the trench is also relatively reduced. If the insulating material filled in the trench causes excessively high embedded stress and the germanium lattice is dislocated, additional leakage current is generated and the insulating material can provide effective electricity. The ability to isolate is reduced. In particular, the use of various conventional techniques to form 1322457 15872twf.doc/006 STI trenches with a width less than approximately 1800A, which provides a significant reduction in the ability to electrically isolate the connected components. The differential row is usually in 3 channels. During the formation of the trench structure, it is caused by mechanical or thermal stresses applied to the substrate and/or insulating material. As described above, the ability of the buried stress of the insulating material filling the trench to cause a poor electrical discharge to the sufficient electrical isolation provided by the STI trench is impaired. This difference is usually due to mechanical and thermal stresses caused by the STI channel structure. Figure 1 is a schematic cross-sectional view of a conventional STI structure from which the effects of mechanical and thermal stresses can be seen. The structure shown in Fig. 1 includes a stone substrate 100 having a oxidized layer ITO 2 and a ruthenium nitride layer 104 formed thereon. A trench 108 is etched and penetrates the oxide and nitride layers to enter the substrate 100. The sidewall oxide layer 1 〇 6 is formed on the surface of the trench 108 by a conventional oxidation technique such as dry or wet thermal oxidation. When the b-channel 108 is filled with an insulating material (for example, using a high-density electro-chemical vapor deposition (HDP-CVD) technique), the sidewall oxide layer 1〇6 will help reduce the thickness of the insulating layer. stress. • The conventional STI trench structure embodiment of Figure 1 has a number of disadvantages. For example, an oxide encroachment structure 1〇7, also commonly referred to as a “bird's beak,” structure, is formed when η2〇 and 〇2 diffuse into the ruthenium substrate 100 and the ruthenium dioxide layer. The interface between 1 and 2 is one of the reasons why the active area is reduced and the characteristic loss is caused. In addition, the sharp corners 11 at the bottom of the STI trench will also cause the filling of the trench. The high embedding stress in the insulating material of 108 is one of the reasons for the difference. In some process conditions, the etching at the corner of the trench is slightly deeper than the etching at the corner of the trench. The center of the trench 108 makes the corner lio sharper 'especially after the sidewall oxide layer 1 〇 6 is formed. Thus, the embedding stress is further increased. As described above, the difference caused by these embedding stresses This will result in a leakage current' which in turn reduces the reliability of the adjacent active components separated by the trenches 1 〇 8. One way to reduce the buried stress of the STI trench filled insulating material is to continue to deposit a layer of tensile stress (tensile) Stress) Another layer of insulating material (compressive stress). In theory, this other layer of insulating material will balance the overall structural stress in the entire insulator. However, in the actual process, the use of this technology to reduce the structural stress to the entire insulator The effective reduction of the buried stress in the process is very difficult or not. Due to the deposition of multiple layers of insulating material, precise control of the subsequent chemical mechanical polishing of the flat surface of the 2-body circuit becomes very difficult. Another method of embedding stress in a trench filled insulating material θ is filled with a high temperature anneal after filling the trench, thereby stressing and thereby reducing the deposition in the trench: however, there is a flaw on the surface of the isolated trench In the middle of the annealing step, the side of the annealing step will be unfavorably generated. This thermal stress is another cause of the heat generated by the 匕 layer = 发明. For the above reasons, the present invention provides High-density packaging on a semiconductor substrate; in the case of a universal isolation, the STi structure provides a method in some modified round rims that can be lowered at 8 1322457 15872twf.doc/006 The type of component to be removed. For example, in flash memory applications, the trench is usually between about 2,500 and about 4,500. In order to separate the logic device (for example, metal oxidation) Semiconductor (MOS) transistors] 'the trenches are typically between about 2000 A and about 4000 A. In a consistent application, 'the trench can be formed by an anisotropic etching method', for example A reactive ion etching method, as well as other etching methods, are used in other embodiments. Then, a thin, thick, nitrided layer of tantalum layer 212 is deposited conformally on the money channel 208. In one embodiment, the blanket layer of tantalum nitride 212 has a thickness of about 25A to about 300A. In another embodiment, the 'thickness tantalum nitride layer 212 has a thickness between about 3 A and about 2 A, and in yet another embodiment, the thick tantalum nitride layer 212. Having a thickness of between about 50 and about 150 A, in one embodiment, the blanket layer of tantalum nitride 212 has a thickness of between about 75 A and about 125 A. In one embodiment, the tantalum nitride layer 212 has a substantially uniform thickness that is applied to the upright, horizontal, and corner portions of the trench 2〇8 along the shape of the trench 208. In these embodiments, the nitride layer 212 is then selectively oxidized by in situ steam generation (ISSG) oxidation techniques, wherein the processing tool capable of performing the ISSG oxidation process (pr嶋 surface) Tool) For example, the Centura® 5_ system introduced by Applied Materials (in Santa Qara, CA). In the Wei Runbo, the gully hired the f-partition of the nitrite on the horns and the other parts of the gully (upright and horizontal), the 氧化 oxidation rate. Therefore, in the cesium time used for the nitriding of the bottom corner of the oxidation trench 208, the nitride nitrite which is not 1322457 15872 twf.doc/006 is also oxidized, and its ===200 is also partially oxidized. Because of the different surface oxidation in Γ中=生=^8, the trench is a 2.5 degree sidewall oxide layer, as shown in Figure 3. In particular, the tf, the vertical and horizontal portions have a larger thickness and have a relatively small thicker t2 at the corners of the trench 208. And the different parts of the ditch ‘the fossil eve deposition test (known: use ISSG method) relative rate.
12 1322457 15872twf.doc/006 化速率要比STI渠溝結構其他部分的氮化矽的氧化速率要 慢四倍。表A中的數據是藉由穿透式電子顯微技術(TEM) 而得。 在一個實施例中，ISSG之氧化技術使用大約1%到大 約50/ί>之間的虱氣百分比(％¾2) ’在一實施例中，ISSG氧 化技術使用大約5%到大約33%之間的氫氣百分比(％h2；)， 在一個實施例中’ISSG氧化技術使用大約10%到大約25〇/〇 之間的氫氣百分比(％¾)。氫氣百分比％h2乃是由以下之 φ 公式所定義： %H2=(H2流速）X (¾流速+ 〇2流速)·1 藉由在STI渠溝内形成可變厚度的氮化矽層，使得在 STI渠溝中提供了一已修正的側壁氧化層206。如圖3所 示，與圖1所示之習知STI渠溝的尖銳角落相比，已修正 的側壁氧化層206具有一圓角落。當絕緣材料沉積於已修 正的側壁氧化層206之後，其結果由於圓角落之緣故以降 低絕緣材料内的機械應力，以降低絕緣材料内的差排密度。 圖4是利用在此所揭露之某些實施例所形成的渠 矚溝308的部分的照片。照片顯示已修正的侧壁氧化層鄕 具有在渠溝壁平坦部的第一厚度tl和渠溝角落部的第二 厚度t2，其中第一厚度tl>第二厚度t2。類似結構亦顯示 於圖5中。圖4和圖5所示的相片分別是使用穿透式電子 顯微鏡及掃描電子顯微鏡(SEM)所得到的。 本發明所揭露的技術的一個實施例繪示於如圖6的流 程圖。在這些實施例中，在一操作方塊400内，渠溝被蝕 13 15872twf.doc/006 "穿α氮化物和氧化物層並進入其下的美底。 作方塊404中，採用τ 八 土 _。，，、、、後在# 氧化。在一杂;^, Γ 技將均厚沉積的氮化石夕層 魏據局部輪摩而以非對稱的氧itT氧t如Γ s 其他部分的氮化錢二 實施例中，、古知溝之角落周圍產生較薄的氧化。在這些 '，沒種非對稱的氧化導致在STI準溝巾 =:壁=具有圓滑的底部角二= 便提供平也面進行化學機械研磨(CMP)技術處理，以 =於各個習知的STI渠溝之形成技術，本發 路的许夕實施例具有許多優點，其能_成更窄的渠溝， 而不會犧牲能夠提供有效電性隔離的能力 竿二 形成具有降低了缺陷密度細結;某;： 貝施例包括圓形㈣氧化層，其可降個 : 緣材料内的結構應力。 m% if定ΪΪΓΓ已以較佳實施例揭露如上，然其並非用以 =Γ丄 習此技藝者’在不脫離本發明之精神 和辄圍内’备可作些許之更動與潤飾，因此本發明 範圍當視後附之巾請專纖目所界定者為準。 … 【圖式簡單說明】 本發明的已修正的STI技術和結構如附圖所示， 附圖僅起制仙。_由町各圖組成，圖中相同的ς 1322457 15872twf.doc/006 圖標記代表相同的部件。 圖1疋習知的STI結構的剖面示意圖。 圖2緣示為本發明較佳實施例之氮化層均厚地沉積於 在STI渠溝上的剖面示意圖。 圖3繪示為執行現場蒸汽產生氧化製程之後的圖2所 示的STI渠溝的下角落部的局部放大圖。 圖4是利用一實施例所形成的S11結構的一部分的 面照片。 ° φ 圖5是利用一實施例所形成的STI結構的剖面照片。 圖6綠示為本發明較佳實施例之形成具有降低差排密 度的絕緣材料的STI渠溝的方法的流裎圖。 【主要元件符號說明】 100 :基底 102 :二氧化矽層 104 : It化石夕層 106 :側壁氧化層 107 :氧化物侵蝕結構 • 108 :渠溝 110 :角落 200 :基底 202 :氧化層 204 :氮化矽層 206、306 :側壁氧化層 208、308 :渠溝 15 1322457 15872twf.doc/006 212 :氮化矽層 tl、t2 :厚度 400、402、404、406、408 :操作方塊12 1322457 15872twf.doc/006 The rate of oxidation is four times slower than that of other parts of the STI trench structure. The data in Table A is obtained by transmission electron microscopy (TEM). In one embodiment, the ISSG oxidation technique uses a percentage of helium (%3⁄42) between about 1% and about 50/ί'. In one embodiment, the ISSG oxidation technique uses between about 5% and about 33%. The percentage of hydrogen (%h2;), in one embodiment, the 'ISSG oxidation technique uses a percentage of hydrogen (%3⁄4) between about 10% and about 25 〇/〇. The percentage of hydrogen %h2 is defined by the following formula φ: %H2=(H2 flow rate)X (3⁄4 flow rate + 〇2 flow rate)·1 By forming a variable thickness layer of tantalum nitride in the STI trench, A modified sidewall oxide layer 206 is provided in the STI trench. As shown in Figure 3, the modified sidewall oxide layer 206 has a rounded corner as compared to the sharp corners of the conventional STI trench shown in Figure 1. After the insulating material is deposited on the modified sidewall oxide layer 206, the result is a reduction in mechanical stress in the insulating material due to the rounded corners to reduce the differential density within the insulating material. 4 is a photograph of a portion of a trench 308 formed using certain embodiments disclosed herein. The photograph shows that the modified sidewall oxide layer 鄕 has a first thickness t1 at the flat portion of the trench wall and a second thickness t2 at the corner portion of the trench, wherein the first thickness tl > the second thickness t2. A similar structure is also shown in Figure 5. The photographs shown in Figures 4 and 5 were obtained using a transmission electron microscope and a scanning electron microscope (SEM), respectively. One embodiment of the disclosed technology is illustrated in the flow chart of FIG. In these embodiments, in an operational block 400, the trench is etched 13 15872 twf.doc/006 " through the alpha nitride and oxide layers and into the underlying aesthetic. In block 404, τ 八土 _ is employed. ,,,, and after oxidation in #. In a heterogeneous; ^, 技 technique will be deposited in a uniform thickness of the nitrite layer according to the local wheel and the asymmetric oxygen itT oxygen t such as 其他 s other parts of the nitriding money two examples, Gu Zhigou Thinner oxidation occurs around the corners. In these ', no kind of asymmetric oxidation leads to the STI quasi-dough == wall=has a smooth bottom angle two = then it provides a flat surface chemical mechanical polishing (CMP) technology treatment to = various conventional STI The formation technique of the trench, the embodiment of the present invention has many advantages, which can be made into a narrower trench without sacrificing the ability to provide effective electrical isolation. ; a; Bayes example includes a circular (four) oxide layer, which can be reduced: structural stress within the edge material. The m% if definition has been disclosed above in the preferred embodiment, but it is not intended to be used by those skilled in the art to make a few changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is subject to the definition of the attached towel. [Simplified Schematic Description] The modified STI technique and structure of the present invention are as shown in the drawings, and the drawings are only for the sake of the drawings. _ consists of various maps of the town, the same ς 1322457 15872twf.doc/006 in the figure. The figure marks represent the same parts. Figure 1 is a schematic cross-sectional view of a conventional STI structure. Figure 2 is a schematic cross-sectional view showing a nitride layer deposited uniformly on a STI trench in accordance with a preferred embodiment of the present invention. Figure 3 is a partial enlarged view of the lower corner portion of the STI trench shown in Figure 2 after performing an in-situ steam generation oxidation process. Figure 4 is a photograph of a portion of the S11 structure formed using an embodiment. ° φ Figure 5 is a cross-sectional photograph of an STI structure formed using an embodiment. Figure 6 is a flow diagram showing a method of forming an STI trench having an insulating material having reduced differential density in accordance with a preferred embodiment of the present invention. [Main component symbol description] 100: Substrate 102: cerium oxide layer 104: It fossil layer 106: sidewall oxide layer 107: oxide etched structure • 108: trench 110: corner 200: substrate 202: oxide layer 204: nitrogen矽 矽 206, 306: sidewall oxide layer 208, 308: trench 15 1322457 15872twf.doc / 006 212: tantalum nitride layer tl, t2: thickness 400, 402, 404, 406, 408: operation block
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