TWI703673B - Method of fabricating semiconductor device and semiconductor device - Google Patents

Abstract

A trench is formed through a plurality of layers that are disposed over a first substrate. A first deposition process is performed to at least partially fill the trench with a first dielectric layer. The first dielectric layer delivers a tensile stress. A second deposition process is performed to form a second dielectric layer over the first dielectric layer. A third deposition process is performed to form a third dielectric layer over the second dielectric layer. The third dielectric layer delivers a first compressive stress.

Description

Manufacturing method of semiconductor device and semiconductor device

The present disclosure relates to methods of filling deep trenches of semiconductor devices.

Semiconductor integrated circuits (IC) have experienced rapid growth. Technological advances in integrated circuit materials and design have produced several generations of integrated circuits, each of which has smaller and more complex circuits than the previous generation. However, as the size of semiconductor manufacturing continues to shrink, various new challenges may arise. For example, semiconductor manufacturing may involve filling trenches with a high aspect ratio (e.g., aspect ratio greater than or equal to 10:1), because the size of semiconductor devices (and the resulting trench size also) becomes smaller and smaller, filling such trenches Trenching can be difficult to implement. Another example is that semiconductor manufacturing may involve the process of bonding different wafers together. However, the warpage of the wafer (which may be partly caused by the tensile stress-relieving film) may cause metal cracks in the bonding. As the bonding area is getting smaller and smaller, the size reduction in semiconductor manufacturing may further add to this problem.

Therefore, although the existing semiconductor manufacturing methods are generally sufficient In order to achieve the desired purpose, but not completely satisfactory in all aspects.

The present disclosure provides a method for manufacturing a semiconductor device, including: forming a trench through a plurality of layers provided on a first substrate; performing a first deposition process to at least partially fill the trench with a first dielectric layer Groove, in which the first dielectric layer releases tensile stress; performing a second deposition process to form a second dielectric layer on the first dielectric layer; and performing a third deposition process to form a second dielectric layer A third dielectric layer is formed thereon, wherein the third dielectric layer releases the first compressive stress.

The present disclosure provides another method of manufacturing a semiconductor device, including: forming a trench through a stack of a plurality of layers provided on a device substrate, wherein the trench has an aspect ratio greater than or equal to about 10:1, and One of the stacked layers includes a bonding pad; a spin-on dielectric deposition process is used to partially fill the trench with a first dielectric material, and the first dielectric material is in a liquid state; and the first dielectric material is baked , To transform the first dielectric material from liquid to solid; after baking, fill the remaining part of the trench with a second dielectric material; use a plasma deposition process to form a third dielectric on the second dielectric material Material, wherein the third dielectric material is formed to have a thickness within about 20% to about 80% of the total thickness of the first dielectric material and the second dielectric material; the chemical vapor deposition process is used in the first A fourth dielectric material is formed on the three dielectric materials; an opening is etched through the fourth dielectric material, the third dielectric material, the second dielectric material, and the first dielectric material, wherein the opening exposes the bonding pad And coupling the carrier substrate to the device substrate, wherein the coupling includes The protruding component of the carrier substrate is inserted through the opening and the protruding component is bonded to the bonding pad.

The present disclosure also provides a semiconductor device including a plurality of layers, trenches, a second dielectric layer, and a third dielectric layer. Multiple layers are stacked vertically. The trench extends vertically through the plurality of layers, wherein the trench is at least partially filled with a first dielectric layer, and the first dielectric layer releases the first tensile stress. The second dielectric layer is disposed on the first dielectric layer, wherein the second dielectric layer releases the second tensile stress or the first compressive stress. The third dielectric layer is disposed on the second dielectric layer, wherein the third dielectric layer releases the second compressive stress.

100: Semiconductor device

110: substrate

120: epitaxial layer

130: layer

140: conductive element

150: layer

160: passivation layer

170: layer

180: passivation layer

200, 201, 202: groove

220, 230: size

250: layer

300: deposition process

310, 311, 312: layer

320: thickness

350: Annealing process

370: Deposition process

380: layer

390: thickness

400: deposition process

410: layer

420: Thickness

450: Flattening process

500: deposition process

510: layer

520: thickness

550: etching process

570: open

600: carrier substrate

600A: Protruding components

650: Grinding process

700: Etching process

720: open

900: method

910, 920, 930, 940, 950: steps

The various aspects of the present disclosure can be best understood by reading the following detailed description together with the accompanying drawings. It should be emphasized that, according to industry standard practices, the various features are not drawn to scale. In fact, for clarity of discussion, the size of each feature may be increased or decreased arbitrarily. And it should be emphasized that the accompanying drawings only illustrate representative implementations of the present disclosure, and therefore should not be regarded as limiting the scope, because the present disclosure can also be applied to other implementations.

1 to 12 are schematic partial cross-sectional views of the semiconductor device at various stages of manufacturing according to various embodiments of the present disclosure.

FIG. 13 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

The subsequent disclosure provides many different implementations or examples to achieve different features of the provided subject matter. Specific embodiments of components and configurations are described below to simplify the present disclosure. These are of course only examples and are not intended to be limiting. For example, in the following description, forming the first feature higher than the second feature or above the second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include additional features that may be formed on Between the first and second features, so the first and second features may not be in direct contact. In addition, the present disclosure may repeat numbers and/or letters in each embodiment. Such repetition is for the sake of simplification and clarity, and does not mean the relationship between the various embodiments and/or configurations discussed.

In addition, relative terms in space may be used here, such as "below", "below", "lower", "above", "higher" and similar terms to make it easy to describe as shown in the diagram The relationship between one element or feature and other elements or features. In addition to the directions shown in the drawings, relative terms in space are intended to cover different directions of the device in use or operation. The device may have other directions (rotation 90 degrees or other directions), and the relative terms used here in space can also be interpreted accordingly.

In addition, when a number or a range of numbers is described in terms of "about", "approximately", etc., the term is intended to cover multiple numbers within a reasonable range including the number described, such as within +/- 10% of the number , Or other values understood by those skilled in the art. For example, the term "about 5 nanometers (nm)" covers the size range from 4.5 nanometers to 5.5 nanometers.

The rapid development of the semiconductor industry has led to advances in manufacturing methods and processes. However, despite these advances, existing semiconductor manufacturing may still have various disadvantages. For example, existing semiconductor manufacturing may involve forming a deep trench with a high aspect ratio (eg, greater than about 10), and filling the deep trench with material. Due to the high aspect ratio and the increasingly smaller device sizes, it is difficult to fill such deep trenches without the gaps or voids trapped therein. These gaps/voids may cause problems in subsequent manufacturing processes and may reduce device performance. Another example is that existing semiconductor manufacturing may involve bonding different wafers together, such as bonding device wafers and carrier wafers. However, any warpage in the device wafer (which may be caused by the tensile stress released by its film) may cause cracks to appear at or near the bonding area. In some cases, the tensile stress-relieving film may be the film used to fill deep trenches in existing manufacturing methods. These cracks in the junction area can reduce device performance or even cause device failure.

In order to overcome the problems of the existing semiconductor manufacturing process, the present disclosure proposes a novel solution involving multiple material layers in order to fill the deep trenches more effectively, with substantially no gaps/voids trapped therein, which improves device performance. This novel solution also introduces compressive stress to compensate for tensile stress. Compressive stress basically offsets tensile stress, thus reducing or eliminating wafer warpage. Therefore, the joint crack problem is basically eliminated, and the device performance is improved. The following discusses various aspects of the present disclosure with reference to FIGS. 1 to 12. According to embodiments of the present disclosure, these figures are schematic partial cross-sectional side views of the semiconductor device 100 at various manufacturing stages. In some embodiments, the semiconductor device 100 may include a two-dimensional transistor or a planar transistor. In other In some embodiments, the semiconductor device 100 may include a three-dimensional FinFET transistor, in which one or more fin structures surround the gate structure.

Referring to FIG. 1, the semiconductor device 100 includes a substrate 110. In some embodiments, the substrate 110 includes a silicon material doped with p-type dopants (such as boron), such as a P-type substrate. Alternatively, the substrate 110 may include another suitable semiconductor material. For example, the substrate 110 may include silicon (N-type substrate) doped with n-type dopants (such as phosphorus or arsenic). The substrate 110 may also include other elemental semiconductors, such as germanium and diamond. The substrate 110 may optionally include a compound semiconductor and/or an alloy semiconductor. In addition, the substrate 110 may be strained to improve performance, and may include a silicon-on-insulator (SOI) structure.

An epitaxial layer 120 is formed on the substrate 110. The formation of the epitaxial layer 120 may use an epitaxial growth process. In some embodiments, the epitaxial layer 120 may include silicon material. In other embodiments, the epitaxial layer 120 may include silicon germanium or other suitable semiconductor materials. It should be understood that a portion of the epitaxial layer 120 may be used as an active area of the semiconductor device 100. Transistor components, such as the source/drain regions or channel regions of a metal oxide semiconductor field effect transistor (MOSFET), may be at least partially formed in the epitaxial layer 120.

An insulating layer 130 is formed on the epitaxial layer 120. The insulating layer 130 includes an electrically insulating material, such as a dielectric material. In various embodiments, the dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, or low-k dielectric materials. A low-k dielectric material is a dielectric material having a dielectric constant (which is approximately 4) smaller than that of silicon dioxide. As a non-restrictive implementation For example, low-k materials may include fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, spin-coated organic polymer dielectrics, spin-coated silicon Base polymer dielectric, or a combination thereof.

The insulating layer 130 may be part of an interconnect structure, and the interconnect structure may include one or more interconnect layers, which provide electrical connections between various doping features, circuits, and/or inputs/outputs in the semiconductor device 100. Sexual interconnection (for example, wiring). For example, the interconnect structure may include conductive elements such as vias and/or metal lines. As an example, FIG. 1 shows the conductive element 140. The insulating layer 130 provides electrical isolation for the conductive element 140 (and also other conductive elements). In some embodiments, the conductive element 140 includes a metal material, such as copper or copper alloy. The conductive element 140 may be used for bonding and may serve as a bonding pad.

A layer 150 is formed on the insulating layer 130 and on the conductive element 140. In some embodiments, the layer 150 may include a dielectric material and may act as an etch stop layer (ESL). In some embodiments, the layer 150 may include silicon nitride or silicon oxynitride.

A passivation layer 160 is provided on the layer 150. The passivation layer 160 protects the components of the semiconductor device 100 from being affected by factors such as dust and moisture. In some embodiments, the passivation layer 160 includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, and the like.

A layer 170 is formed on the passivation layer 160. Similar to layer 150, layer 170 may contain a dielectric material and may act as an etch stop layer. However, layer 170 and layer 150 may be used as etch stop layers for different processes or layers. For example, layer 170 may serve as a layer formed thereon (e.g., as discussed below Layer 180) is a patterned etch stop layer. In contrast, layer 150 may serve as an etch stop layer for a deep trench etching process (discussed below). In some embodiments, the layer 170 may include silicon nitride or silicon oxynitride.

A passivation layer 180 is provided on the layer 170. Similar to the passivation layer 160, the passivation layer 180 protects the components of the semiconductor device 100 from being affected by factors such as dust and moisture. In some embodiments, the passivation layer 180 includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, and the like. As mentioned above, the layer 170 may serve as a patterned etch stop layer for the passivation layer 180, but this is not the focus of this disclosure. The patterning of the passivation layer 180 is also performed at different regions of the semiconductor device 100 (for example, a portion not shown in FIG. 1), and therefore, it is not specifically shown in the subsequent drawings herein. It should also be understood that, in some embodiments, the semiconductor device 100 may be implemented without the layer 170 and the passivation layer 180.

Referring now to FIG. 2, a plurality of trenches are formed in the semiconductor device 100, for example, a relatively shallow trench 200 and a plurality of relatively deep trenches 201 to 202. The trenches 200 to 202 may be formed through one or more etching processes. The trench 200 is vertically aligned with the conductive element 140 and is formed above the conductive element 140. As shown in Figure 2, trench 200 extends vertically through layers 160 to 180 and extends at least partially into layer 150. The trenches 201 to 202 are formed on opposite sides of the conductive element 140. Each of the trenches 201 to 202 extends vertically through the layers 130 to 180 and extends at least partially into the epitaxial layer 120. Each of the trenches 201 to 202 also has a lateral dimension 220 (e.g., width) and a vertical dimension 230 (e.g., depth). In some embodiments, the vertical dimension 230 is greater than or equal to about 6 microns (microns), for example, greater than or equal to about 8 microns.

The aspect ratio of the trench 201 or the trench 202 may be defined as the ratio of the vertical dimension 230 to the lateral dimension 220. Expressed in mathematical terms, the aspect ratio of trench 201 (or trench 202)=(size 230)÷(size 220). The aspect ratio of the trenches 201 and 202 is relatively high, for example, greater than or equal to 10 (or 10:1). This means that the trenches 201 and 202 are long and narrow and therefore may be difficult to fill completely without sinking any air gaps or voids therein. As the size of semiconductors continues to shrink, smaller and smaller device sizes are intensifying this problem. The present disclosure overcomes these problems by using a novel and non-obvious process to fill the trenches 201 to 202, as discussed in more detail below.

Referring now to FIG. 3, an insulating layer 250 is formed on the semiconductor device 100. In some embodiments, the insulating layer 250 is formed via atomic layer deposition (ALD), and may include transition metal oxide/nitride materials, such as TaO, TaN, TiO, TiN, ZrO, ZrN, and the like. In other embodiments, the insulating layer 250 may be formed through a self-assembly monolayer (SAM) coating technology, and may include a functional group that is resistant to NF ₃ etching, such as an -OH group. The insulating layer 250 partially fills the trenches 200 to 202. After the insulating layer 250 is formed, a spin-on dielectric deposition process 300 is performed to form a dielectric layer 310 in the trench 200, a dielectric layer 311 in the trench 201, and a dielectric layer in the trench 202 312. In some embodiments, the dielectric layers 310 to 312 include oxide materials, such as silicon oxide (Si _x O _y ). In some embodiments, y is approximately equal to 2x, such as between about 1.8x and about 2.2x. The silicon content in the layers 310-312 may be related to the refractive index (RI) of the layers 310-312. In some embodiments, the refractive index of layers 310 to 312 is in a range between about 1.4 and about 1.7.

During and immediately after deposition, the dielectric layers 310 to 312 are in a liquid state. Due to the liquid nature of the dielectric layers 310 to 312, even if the trenches 201 to 202 have a high aspect ratio (for example, greater than or equal to 10:1), the dielectric layers 310 to 312 can fill small slits, such as the trenches 201 to 201. 202. There are basically no air gaps or voids. In addition, since the dielectric layers 310 to 312 are in a liquid state, they can be sprayed out as part of the spin-on dielectric deposition process 300 to improve uniformity. In some embodiments, the upper surfaces of the dielectric layers 310 to 312 are substantially coplanar.

As shown in Figure 3, each of the dielectric layers 311 or 312 has a thickness 320 (measured in vertical dimension). The value of thickness 320 may be adjusted by configuring one or more process parameters (such as deposition time) of spin-on dielectric deposition process 300. The thickness 320 is less than or substantially equal to the vertical dimension 230 (depth) of the trench 201/202. The thickness 320 of the dielectric layer 311/312 is within about 40% to about 100% of the vertical dimension 230 (depth) of the trench 201/202. In other words, in some embodiments, the dielectric layers 310 to 312 may only partially fill the trenches 200 to 202, or, in some other embodiments, the dielectric layers 310 to 312 may completely fill the trenches 200. To 202. Since there are dielectric layers 311 to 312 in the trenches 201 to 202, after the deposition process 300 is performed, the trenches that are now at least partially filled have a smaller aspect ratio. In some embodiments, the trenches 201 to 202 may have an aspect ratio less than about 6:1, for example, an aspect ratio ranging from about 6:1 to about 0:1.

The dielectric layers 310 to 312 also release tensile stress to the semiconductor device 100 (for example, a stress state that causes expansion). In some embodiments, the tensile stress released by the dielectric layers 310 to 312 is greater than or substantially equal to about 4.0×10 ⁸ dyne/cm ² . In some embodiments, the tensile stress released by the dielectric layers 310 to 312 is greater than or substantially equal to about 200 megapascals (MPa). Although such tensile stress, if not considered, will cause wafer warpage, the present disclosure overcomes this problem by forming other layers of materials that apply compressive stress to compensate for the tensile stress, which will be discussed in more detail below. .

Referring now to FIG. 4, an annealing process 350 is performed on the semiconductor device 100. In some embodiments, the annealing process 350 is performed at a processing temperature ranging between about 80 degrees Celsius and about 800 degrees Celsius. The annealing process 350 bakes the dielectric layers 310 to 312. As described above, the dielectric layers 310 to 312 are in a liquid state during the execution of the spin-on dielectric deposition process 300 and immediately after the processing, because the liquid is beneficial to filling the trenches 200 to 202, especially the trench 201 with a high aspect ratio. To 202. In addition, the annealing process 350 helps the dielectric layers 310 to 312 change from liquid to solid.

Referring now to FIG. 5, a deposition process 370 is performed to deposit a layer 380. In some embodiments, the deposition process 370 includes a high-aspect-ration (HARP) process, which is used to deposit material in small trenches with a high aspect ratio. In some embodiments, the high aspect ratio process may include a thermal process, which deposits a silicon oxide film with tetraethyl orthosilicate (TEOS) and O ₃ as precursors.

A layer 380 is deposited on the dielectric layers 310 to 312 and on the insulating layer 250, and the layer 380 has a thickness 390. If the groove 200 to 202 If the dielectric layers 310 to 312 have not been completely filled (such as the embodiment shown herein), the layer 380 will completely fill the remaining portions of the trenches 200 to 202. In other words, the part of the layer 380 may be formed higher than the dielectric layers 310 to 312 and in the trenches 200 to 202, and the other part of the layer 380 may be formed higher than the trenches 200 to 202 and in the trenches 200 to 202. 202 outside. In various embodiments, the layer 380 may fill about 0% to about 60% of the trenches 201 to 202 (in terms of trench depth).

Although the gap filling performance of the deposition process 370 may not be as good as the spin-on dielectric deposition process 300, there is still no problem in filling the trenches 200 to 202. This is because the partially filled trenches 200 to 202 (e.g., partially filled with dielectric layers 310 to 312) already have a reduced aspect ratio, because the depth of these trenches is reduced and their width remains substantially the same . Therefore, the deposition process 370 can still fill the remaining portions of the trenches 200 to 202 without creating voids or gaps therein.

In some embodiments, the layer 380 includes an oxide material, such as silicon oxide (Si _x O _y ). In some embodiments, y is approximately equal to 2x, for example from about 1.8x to about 2.2x. The silicon content in the layer 380 may be related to the refractive index (RI) of the layer 380. In some embodiments, the refractive index of layer 380 is in a range between about 1.4 and about 1.7.

The layer 380 may relieve stress, which may be tensile or compressive. In some embodiments, the tensile or compressive stress released by the dielectric layer 380 is in a range between about -100 MPa and about 200 MPa. In the embodiment where the stress released by the layer 380 is tensile stress, the tensile stress is much smaller than the tensile stress released by the dielectric layers 310 to 312, and such tensile stress The force will be compensated via the compressive stress released by the subsequently formed layer, as described below. It should be understood that it may not be only the dielectric layers 310 to 312 and/or the layer 380 that are components that cause tensile stress. Other components of the semiconductor device 100 may also cause tensile stress, and the combined tensile stress needs to be compensated, otherwise it may cause problems such as wafer warpage and joint cracks, as discussed below.

One of the benefits of the present disclosure is that it has good gap filling performance in filling trenches 200 to 202. It can be used for trenches 201 to 202 because trenches 201 to 202 have a high aspect ratio (for example, greater than about 10:1). Conventional manufacturing processes usually use atomic layer deposition (ALD) to fill trenches with a high aspect ratio, such as trenches 201 to 202. Unfortunately, as the device size shrinks and/or the aspect ratio increases, in the trench filling process, even the atomic layer deposition process may trap air gaps or voids in the formed material. These air gaps or voids may cause manufacturing problems and may reduce device performance. In contrast, a two-step process (for example, processes 300 and 370) allows the trenches 201 to 202 to be filled without trapping air gaps or voids therein. This eliminates problems that may be caused by air gaps or voids in subsequent manufacturing processes.

In some embodiments, two different processes (for example, process 300 and 370) are performed to fill the lower and upper portions of trenches 201 to 202 with high aspect ratios with dielectric layers 311 to 312 and layer 380, respectively, to obtain benefit. In more detail, although the spin-on dielectric deposition process 300 may have excellent gap filling performance, the resulting dielectrics 311 to 312 may have relatively high tensile stress, which may cause wafer warpage. When the entire trenches 201 to 202 are completely filled with the dielectric layers 311 to 312, the resulting tensile stress The force may be relatively high, and to compensate for the tensile stress, it may cause a great burden on the subsequent manufacturing process. However, when the trenches 201 to 202 are partially filled (as in the case of the illustrated embodiment), the resulting tensile stress is not very high, which can be easily compensated by the subsequent manufacturing process. And as mentioned above, only partially filling trenches 201 to 202 through the deposition process 300 is not a problem, because the subsequent trench filling only needs to fill trenches with a significantly reduced aspect ratio (for example, 6:1 or less) . This can be easily achieved through the deposition process 370 without trapping voids therein, even if the gap filling performance of the deposition process 370 is not as good as the deposition process 300. Therefore, there is almost no performance loss (if any) in terms of trench filling, and no gaps or voids inset. Advantageously, since the layer 380 formed by the deposition process 370 has low tensile stress or no tensile stress at all, the total tensile stress is reduced, which means that it may be easier to compensate for the tensile stress of the dielectric layers 311 to 312 Tensile stress.

In some embodiments, after the layer 380 is formed, the warpage of the wafer of the semiconductor device 100 manufactured thereon is measured. Since the wafer warpage is due to the tensile stress caused by the various components of the semiconductor device (for example, the tensile stress released by the dielectric layers 310 to 312 and the tensile stress possibly released by the layer 380), the wafer warps The measurement provides an indication of how much compressive stress may be needed to compensate for tensile stress. However, it should be understood that this wafer warpage measurement step is optional and may be omitted in some embodiments.

Referring now to FIG. 6, a high density plasma (HDP) deposition process 400 is performed to deposit a dielectric layer 410 on the layer 380. In some embodiments, the dielectric layer 410 includes an oxide material, such as silicon oxide (Si _x O _y ). In some embodiments, y is approximately equal to 2x, for example between about 1.8x and about 2.2x. The silicon content in layer 410 may be related to the refractive index (RI) of layer 410. In some embodiments, the refractive index of layer 380 is in a range between about 1.4 and about 1.7. In some embodiments, performing the high-density plasma deposition process 400 may use precursors including silane (SiH ₄ ) and oxygen (O ₂ ).

The dielectric layer 410 also relieves compressive stress. In some embodiments, the compressive stress released by the dielectric layer 410 is less than or substantially equal to about -1.0×10 ⁹ dyne/cm ² . In some embodiments, the tensile stress released by the dielectric layer 410 is less than or substantially equal to about -100 MPa. The compressive stress counteracts the tensile stress released by the dielectric layers 310 to 312 (and possibly by layer 380). Therefore, the dielectric layer 410 can reduce potential wafer warpage caused by tensile stress. The dielectric layer 410 has a thickness 420. The thickness 420 is adjusted to be within a certain percentage of the total combined thickness of layers 380 and 311/312 (which may be the sum of thickness 320 and thickness 390). In some embodiments, the thickness 420 is adjusted to about 20% to about 80% of the sum of the thicknesses 320 and 390. This range is optimized because it allows the dielectric layer 410 to release a sufficient amount of compressive stress to offset the tensile stress released by the components of the semiconductor device (for example, via layers 310 to 312 and/or 380), but not too much This causes the wafer to warp due to excessive compressive stress. In some embodiments, the compressive stress may be memorable, for example due to a stress memorization technique (SMT). In other words, even after the dielectric layer 410 is removed, the compressive stress released by the dielectric layer 410 remains at least partially.

Referring now to FIG. 7, a planarization process 450 is optionally performed on the dielectric layer 410. For example, the planarization process 450 may include chemical mechanical polishing (CMP) process, which flattens the upper surface of the dielectric layer 410. If the trenches 200 to 202 are not filled according to the process of the present disclosure discussed above, voids or air gaps may be formed in the material for filling the trenches. Sometimes, the void may have a shape similar to a vertically extending line or seam. When a chemical mechanical polishing process such as process 450 is performed, the used chemicals (for example, slurry) may enter the voids. Such chemical residues in the voids may be difficult to remove in a subsequent process, which may contaminate the semiconductor device 100 and reduce performance. However, since the present disclosure fills the trenches with high aspect ratio without indenting voids therein, the planarization process 450 will not produce such undesirable chemical residues.

Referring to FIG. 8, a deposition process 500 is performed to form a layer 510 on the dielectric layer 410. In some embodiments, the deposition process 500 includes plasma enhanced chemical vapor deposition (PECVD). In some embodiments, the layer 510 is formed to include silicon oxide (Si _x O _y ), or in some other embodiments, to include silicon nitride (Si _x N _y ). In embodiments where the layer 510 includes silicon oxide, the deposition process 500 may use SiH ₄ /TEOS and O ₂ as precursors. In embodiments where the layer 510 includes silicon nitride, the deposition process 500 may use SiH ₄ and N ₂ O/NH ₃ as precursors.

In embodiments where the layer 510 includes silicon oxide, y is approximately equal to 2x, for example between about 1.8x and about 2.2x. In embodiments where the layer 510 includes silicon nitride, y is approximately equal to (4/3)x, for example, y is between approximately 1.1x and approximately 1.5x. The silicon content in layer 510 may be related to the refractive index (RI) of layer 510. In some embodiments, when the layer 510 includes silicon oxide, the refractive index of the layer 510 is in the range of about 1.4 to about 1.7. When the layer 510 includes silicon nitride, the refractive index of the layer 510 is in the range of about 1.7 to about 2.2. In range.

Layer 510 also relieves compressive stress. In some embodiments, the compressive stress released by the layer 510 is in the range of about -5.0×10 ⁹ dyne/cm ² to about -2.0×10 ⁸ dyne/cm ² . In some embodiments, the compressive stress released by the layer 510 is in the range of about -300 MPa to about -50 MPa. Compressive stress also helps to offset tensile stress caused by various components of the semiconductor device (eg, via layers 310-312 and/or 380), which helps reduce wafer warpage. The amount of compressive stress released by the layer 510 may be configured by adjusting the material composition of the layer 510 (for example, by changing the x and y values discussed above), or by adjusting the thickness 520 of the layer 510. In some embodiments, the thickness range of layer 510 is configured such that the combined compressive stress released by layer 410 and layer 510 will substantially offset the tensile stress released by layer 310 to 312 and/or layer 380. In some embodiments, the thickness 520 ranges from about 50 nanometers (nm) to about 200 nanometers. In some embodiments, compressive stress may have memory properties. In other words, even after the dielectric layer 510 is removed, the compressive stress released by the dielectric layer 510 may at least partially remain. In addition to relieving compressive stress, another function of layer 510 is that it helps to adhere to the carrier wafer during the bonding process discussed below.

Now referring to FIG. 9, an etching process 550 is performed on the semiconductor device 100 to form an opening or recess 570. The opening 570 extends vertically through the layers 510, 410, 380, 310, 250, and 150 and exposes a portion of the conductive element 140.

Referring now to FIG. 10, the semiconductor device 100 is vertically turned upside down. The carrier substrate 600 is then bonded to the semiconductor device 100. The carrier substrate 600 includes a protruding component 600A (for example, containing a metal material), which is inserted Inside the opening 570. Via the protruding member 600A, the carrier substrate 600 is bonded to the semiconductor device 100 (for example, to the conductive element 140).

As described above, wafer warpage has been substantially reduced or eliminated, for example, through the implementation of layers 410 and 510 (both of which relieve compressive stress) to compensate for the tensile stress released by layers 310 to 312 and/or 380. If the wafer warpage is not reduced, this warpage may cause the portion of the semiconductor device 100 corresponding to the conductive element 140 to bend upward, while the remaining portion of the semiconductor device 100 may bend downward. Therefore, the bonding of the carrier substrate 600 and the semiconductor device 100 may cause bonding cracks, for example, at or near the interface between the protruding component 600A and the conductive element 140. The small bonding area associated with the bonding interface (for example, due to the reduced size of the device) may contribute to this problem. Joint cracks can reduce device performance and even cause failure. The present disclosure eliminates or at least reduces the possibility of joint cracks by applying compressive stress to offset tensile stress. This helps to make the wafer substantially flatter, and avoids the joint crack problem that often plagues traditional semiconductor devices.

Referring now to FIG. 11, the polishing process 650 is performed on the semiconductor device 100 from the "back side" (for example, the side not facing the carrier substrate 600) of the semiconductor device. The polishing process 650 removes the substrate 110 and possibly portions of the layer 250 and/or portions of the epitaxial layer 120. In some embodiments, the polishing process 650 may include a mechanical polishing process and/or a chemical thinning process. For example, the mechanical polishing process may remove a large amount of material, such as the substrate 110, and then the chemical thinning process may apply etching chemicals to further thin the semiconductor device 100.

Now referring to FIG. 12, etching is performed on the semiconductor device 100 Process 700. In some embodiments, the etching process 700 uses NF3 as an etchant. The etching process 700 removes the layers 310 to 312, 380, 410, and 510. The removal of layers 310 to 312, 380, 410, and 510 forms an opening 720. Therefore, the etching process 700 may divide the semiconductor device 100 into multiple components, for example, each component is separated from other components by an opening 720. In some embodiments, each component may be packaged into an integrated circuit chip.

Note that if the slurry residue from the planarization process 450 remains in the trenches 200 to 202 (for example, due to the existence of voids or gaps), the etching process 700 may not be able to completely etch the slurry residue. This is because of the material composition between the paste residue (which may contain one or more organic compounds) and the layers 310 to 312, 380, 410, and 510 (these layers contain dielectric materials such as silicon oxide or silicon nitride) The difference. In other words, the etching process 700 may have etching selectivity, allowing the dielectric material of the layers 310 to 312, 380, 410, and 510 to be etched and removed at a much faster etch rate than the organic compound of the etch-removed paste. However, since the present disclosure fills the trenches without voids or gaps, there is no indented slurry residue in the layers 310 to 312, 380, 410, and 510. Therefore, it is possible to completely remove the layers 310 to 312, 380, 410, and 510, and no contamination will be left.

FIG. 13 is a flowchart of a method 900 for executing a method of manufacturing a semiconductor device according to various aspects of the present disclosure. The method includes step 910, forming trenches that pass through a plurality of layers provided on the first substrate. In some embodiments, the formed trench has an aspect ratio greater than or equal to about 10:1.

The method includes step 920, performing a first deposition process to The trench is at least partially filled with the first dielectric layer. The first dielectric layer relieves tensile stress. In some embodiments, the first deposition process includes a spin-on dielectric deposition process to at least partially fill the trench with the first dielectric layer. During the spin-on dielectric deposition process, the first dielectric layer is in a liquid state. The annealing process may be performed after the first deposition process but before the second deposition process. The annealing process bakes the second dielectric layer to transform the first dielectric layer from a liquid state to a solid state.

The method includes step 930, performing a second deposition process to form a second dielectric layer on the first dielectric layer. In some embodiments, the second deposition process includes a high aspect ratio deposition process (HARP). In some embodiments, the first deposition process partially fills the trench with the first dielectric layer, and the second deposition process completely fills the remaining portion of the trench with the second dielectric layer.

The method includes step 940, performing a third deposition process to form a third dielectric layer on the second dielectric layer. The third dielectric layer releases the first compressive stress. In some embodiments, the third deposition process includes a plasma process, such as a high density plasma (HDP) deposition process. In some embodiments, the third deposition process is performed so that the thickness of the third dielectric layer is in a range between about 20% and about 80% of the combined thickness of the first dielectric layer and the second dielectric layer.

The method includes step 950, performing a fourth deposition process to form a fourth dielectric layer on the third dielectric layer. The fourth dielectric layer releases the second compressive stress. In some embodiments, the fourth deposition process includes a plasma enhanced chemical vapor deposition (PECVD) process.

In some embodiments, the first dielectric layer, the second dielectric layer are formed The electrical layer and the third dielectric layer include silicon oxide material in each of these layers, and the fourth dielectric layer is formed to include silicon nitride material.

It should be understood that another process may be performed before, during, or after steps 910 to 950. For example, the method 900 may further include these steps: forming a recess that extends through the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer, wherein the recess exposes the plurality of Performing a bonding process with the second substrate, wherein the second substrate includes a protruding component inserted into the conductive component and bonded with the conductive component; and performing one or more etching processes to remove the second substrate A dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer. For simplification reasons, other manufacturing processes are not discussed in detail here.

In summary, the present disclosure realizes one or more processes (such as spin-on dielectric deposition processes and high aspect ratio processes) with good gap filling performance to form materials in high aspect ratio trenches without Indented voids or gaps in the material. The present disclosure also forms a compressive stress relief layer to offset the tensile stress experienced by the wafer.

Based on the above discussion, it can be seen that the present disclosure provides advantages over traditional image sensor devices. However, it should be understood that other embodiments may provide additional benefits, and not all benefits must be disclosed herein, and not all embodiments require specific benefits. One benefit relates to improvements in gap filling performance. Since the semiconductor devices here include high aspect ratio trenches (for example, the aspect ratio is greater than or equal to about 10:1), it is difficult for the conventional semiconductor manufacturing process to fill these trenches without leaving indented gaps or voids therein. Often, according to the traditional semiconductor manufacturing process, the "line" shape The voids may be trapped in the material filling the high aspect ratio trenches. Such voids or gaps may cause problems in later manufacturing. For example, polishing processes such as chemical mechanical planarization may be performed in a later manufacturing step. The polishing process may use chemical slurries, which may enter voids or gaps. The slurry residue may be difficult to remove through subsequent processes, which may leave contamination to the semiconductor device.

The present disclosure eliminates this problem by using a spin-on deposition process to form a liquid dielectric material in a high aspect ratio trench. This process has good gap filling performance. In embodiments where the dielectric material does not completely fill the trench, the depth of the trench is still reduced, which means that the aspect ratio is reduced. The reduced aspect ratio of the trench (which has been partially filled with the dielectric material) makes it easier to fill with the subsequent high aspect ratio process. Therefore, through a spin-coating deposition process alone, or a combination of a spin-coating deposition process and a high aspect ratio process, the high aspect ratio trenches of the present disclosure may be completely filled without voids or gaps sinking therein. This eliminates the possibility of contaminating materials such as slurry residues of chemical mechanical planarization being trapped in the voids or gaps, and thus may improve device performance.

Another benefit of the present disclosure relates to eliminating joint cracks by reducing wafer warpage. In more detail, some layers formed in a semiconductor device (such as a layer filling a high aspect ratio trench) may apply tensile stress. Tensile stress may cause the wafer to bend or warp. If correction is not made (as is the case in conventional manufacturing), the warpage of the wafer may cause joint cracks at or near the interface between the semiconductor device and the carrier substrate. Joint cracks may reduce device performance or even cause device failure. In order to overcome this problem, the present disclosure The content forms one or more layers that apply compressive stress, even after the layer is removed, the compressive stress may remain (due to stress memory technology). Compressive stress compensates for tensile stress, so wafer warpage or bending is basically reduced or completely eliminated. As a result, joint cracks are also basically eliminated, and device performance is improved.

Other benefits include taking advantage of the calculability of existing manufacturing processes and the ease and low cost of implementation.

One aspect of the present disclosure relates to a method of manufacturing a semiconductor device. The method includes: forming a trench through a plurality of layers disposed on a first substrate; performing a first deposition process to at least partially fill the trench with a first dielectric layer, wherein the first dielectric layer releases Tensile stress; performing a second deposition process to form a second dielectric layer on the first dielectric layer; and performing a third deposition process to form a third dielectric layer on the second dielectric layer, wherein The third dielectric layer releases the first compressive stress.

Another aspect of the present disclosure relates to a method of manufacturing a semiconductor device. This method includes forming a trench through a stack of layers disposed on a device substrate, where the trench has an aspect ratio greater than or equal to about 10:1, and where one layer of the stack includes a bonding pad; using spin coating In the dielectric deposition process, the trench is partially filled with a first dielectric material in a liquid state; the first dielectric material is baked to transform the first dielectric material from a liquid state to a solid state; after the baking, a second dielectric material is used A second dielectric material fills the remaining part of the trench; a plasma deposition process is used to form a third dielectric material on the second dielectric material, wherein the third dielectric material is formed to have a thickness that is in the first Within about 20% and about 80% of the total thickness of a dielectric material and the first dielectric material; use a chemical phase gas deposition process to form a fourth dielectric material on the third dielectric material; An opening through the fourth dielectric material, the third dielectric material, the second dielectric material, and the first dielectric material, wherein the opening exposes at least a part of the bonding pad; and coupling the carrier substrate to the device substrate, Among them, the coupling includes a protruding component of the carrier substrate, which is inserted through the opening and joins the protruding component to the bonding pad.

Another aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes: a plurality of layers stacked vertically on each other; a trench extending vertically through the plurality of layers, wherein the trench is at least partially filled with a first dielectric layer, the first dielectric layer Filling to release the first tensile stress; a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer releases the second tensile stress or the first compressive stress; and the third dielectric layer is disposed On the second dielectric layer, the third dielectric layer releases the second compressive stress.

The features of several embodiments have been summarized above, so that those skilled in the art can better understand the accompanying detailed description. Those skilled in the art should understand that they may easily use this disclosure as a basis for the design and modification of other manufacturing processes and structures to achieve the same purpose or achieve the same benefits as the embodiments described herein. Those skilled in the art should also understand that these equal constructions do not depart from the spirit and scope of the present disclosure, and they may make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure. For example, by implementing different thicknesses for the bit line conductor and the word line conductor, it is possible to realize that each conductor has a different resistance. However, it is also possible to use other techniques for changing the resistance of the metal conductor.

900: method

910, 920, 930, 940, 950: steps

Claims (9)

A method for manufacturing a semiconductor device includes: forming a trench through a plurality of layers provided on a first substrate; and performing a first deposition process to at least partially fill the trench with a first dielectric layer A trench, wherein the first dielectric layer releases a tensile stress, wherein the first deposition process includes a spin-on dielectric deposition process to at least partially fill the trench with the first dielectric layer, and During the spin-on dielectric process, the first dielectric layer is in a liquid state; a second deposition process is performed to form a second dielectric layer on the first dielectric layer; and a third The deposition process is used to form a third dielectric layer on the second dielectric layer, wherein the third dielectric layer releases a first compressive stress. The method of manufacturing a semiconductor device according to claim 1, wherein the forming the trench includes forming the trench having an aspect ratio greater than or equal to about 10:1. The method for manufacturing a semiconductor device according to claim 1, further comprising: performing an annealing process after the first deposition process but before the second deposition process, wherein the annealing process bakes the first dielectric layer to The first dielectric layer changes from the liquid state to a solid state. The method of manufacturing a semiconductor device according to claim 1, wherein: the first deposition process partially fills the trench with the first dielectric layer; and the second deposition process completely fills the second dielectric layer Of the groove The remaining part. A method of manufacturing a semiconductor device includes: forming a trench through a stack of a plurality of layers provided on a device substrate, wherein the trench has an aspect ratio greater than or equal to about 10:1, and wherein One of the plurality of layers of the stack includes a bonding pad; a spin-on dielectric deposition process is used to partially fill the trench with a first dielectric material, the first dielectric material is in a liquid state; Bake the first dielectric material to transform the first dielectric material from the liquid state to a solid state; after the baking, fill a remaining part of the trench with a second dielectric material; use a dielectric The slurry deposition process forms a third dielectric material on the second dielectric material, wherein the third dielectric material is formed to have a thickness that is greater than the difference between the first dielectric material and the second dielectric material Within about 20% to about 80% of the total thickness; using a chemical vapor deposition process to form a fourth dielectric material on the third dielectric material; etching an opening through the fourth dielectric Material, the third dielectric material, the second dielectric material, and the first dielectric material, wherein the opening exposes at least a portion of the bonding pad; and coupling a carrier substrate to the device substrate, wherein the coupling It includes a protruding component inserted into the carrier substrate through the opening and bonding the protruding component to the bonding pad. The method of manufacturing a semiconductor device described in claim 5, Wherein: the first dielectric material applies a first tensile stress; the second dielectric material applies a second tensile stress, which is smaller than the first tensile stress or a first compressive stress; the third dielectric material The material applies a second compressive stress; and the fourth dielectric material applies a third compressive stress. A semiconductor device comprising: a plurality of layers vertically stacked together; a trench extending vertically through the plurality of layers, wherein the trench is at least partially filled with a first dielectric layer, the first The dielectric layer releases a first tensile stress; a second dielectric layer is disposed on the first dielectric layer, wherein the second dielectric layer releases a second tensile stress or a first compressive stress; The third dielectric layer is disposed on the second dielectric layer, wherein the third dielectric layer releases a second compressive stress; a first substrate; an epitaxial layer, which is disposed on the first substrate, Wherein the plurality of layers are disposed on the epitaxial layer, and wherein the trench at least partially extends into the epitaxial layer; a conductive element is disposed in one of the plurality of layers; and a The second substrate is bonded to the conductive element. The semiconductor device according to claim 7, further comprising: a fourth dielectric layer disposed on the third dielectric layer, wherein the fourth dielectric layer releases a third compressive stress. The semiconductor device according to claim 8, wherein: the fourth dielectric layer includes Si _x N _y , y is in the range of about 1.2x to about 1.5x; and the fourth dielectric layer has a refractive index which is In the range between about 1.7 and about 2.2.

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