CN103647912A - Device and method for multi-window image data high speed scanning and acquisition for grating ruler - Google Patents
Device and method for multi-window image data high speed scanning and acquisition for grating ruler Download PDFInfo
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- CN103647912A CN103647912A CN201310691827.7A CN201310691827A CN103647912A CN 103647912 A CN103647912 A CN 103647912A CN 201310691827 A CN201310691827 A CN 201310691827A CN 103647912 A CN103647912 A CN 103647912A
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Abstract
The invention relates to a device and a method for multi-window image data high speed scanning and acquisition for a grating ruler. The device for multi-window image data high speed scanning and acquisition for the grating ruler comprises a CMOS image sensor, a field programmable gate array FPGA and a static random access memory SRAM, wherein a signal input end of the field programmable gate array FPGA is connected with a signal output end of the CMOS image sensor, a signal output end of the field programmable gate array FPGA is connected with a signal input end of the static random access memory SRAM, and a signal output end of the static random access memory SRAM is connected with an SRAM interface of a DSP. According to the device, the field programmable gate array FPGA is utilized to realize high speed image data acquisition, when a moving speed of the image sensor is quite fast, grating coding can be intelligibly shot, so later image processing difficulty is greatly reduced. According to multi-window driving of an absolute grating ruler for the image sensor, a method for improving a shooting speed is realized through reducing effective-less pixel points; longer effective length is acquired through arrangement of window positions with fewer pixel points.
Description
Technical field
The present invention relates to the optical grating ruler measurement field of processing based on image, relate in particular to the view data high-velocity scanning of many windows of imageing sensor and harvester and method, belong to the innovative technology of the view data high-velocity scanning of many windows of imageing sensor and harvester and method.
Background technology
At present, the principle of grating scale is substantially all that Moire fringe based on grating scale is interfered or diffraction produces is measured.This method for designing is developed so far, although quite ripe, but still there are many deficiencies, such as principle is more numerous and diverse, the design comparison of circuit is complicated, requires also higher.
Under this background, the grating scale of processing based on image arises at the historic moment.And the grating scale of processing based on image in the market can not be accomplished in the situation that translational speed is very fast, guarantee the real-time of measuring.Reason is that the grasp speed of image is fast not, and the crawl of whole spoke picture causes a large amount of pixel exposures and the waste in transmission time.
Summary of the invention
The object of the present invention is to provide a kind of many windows of imageing sensor view data high-velocity scanning and harvester.The present invention, in the very fast situation of imageing sensor translational speed, can photograph grating encoding clearly, and the difficulty of the image processing in later stage is reduced greatly.
Another object of the present invention is to provide a kind of many windows of image-position sensor view data high-velocity scanning and acquisition method.Method of the present invention is convenient and practical.
Technical scheme of the present invention is: the present invention is the high-velocity scanning of many windows view data and the harvester of grating scale, include cmos image sensor, on-site programmable gate array FPGA and static RAM SRAM, wherein the signal input part of on-site programmable gate array FPGA and the signal output part of cmos image sensor are connected, the signal output part of on-site programmable gate array FPGA is connected with the signal input part of static RAM SRAM, and the signal output part of static RAM SRAM is connected to the SRAM interface of DSP.
Above-mentioned on-site programmable gate array FPGA includes image data acquiring module, imageing sensor register configuration module, static RAM SRAM control module, and wherein the relation of image data acquiring module, imageing sensor register configuration module, these three modules of static RAM SRAM control module is relations of time order and function.First use imageing sensor register configuration block configuration imageing sensor, make it to carry out work according to our requirement, then use image data acquiring module to gather the picture signal that imageing sensor is captured, finally use static RAM SRAM control module that the picture signal collecting is deposited in SRAM, so that post-processed.
Many windows view data high-velocity scanning of grating scale of the present invention and the method for collection, include following steps:
1) use SCCB agreement that imageing sensor is configured to the operating state that many windows and window are lined up oblique line.
2) according to the view data output protocol of imageing sensor, gather the view data of imageing sensor output.
3) according to the input and output agreement of SRAM, the view data collecting is write in SRAM and stored, then read and be transferred to DSP to make post-processed from it.
Compared with prior art, tool has the following advantages in the present invention:
1) high-velocity scanning of the present invention and acquisition method comprise the many windows drivings to imageing sensor for absolute grating scale; By reducing the method that improves shooting speed without effect pixel; Placement by the window's position obtains longer effective length with pixel still less; By using the method for on-site programmable gate array FPGA high speed acquisition view data.
2) the present invention to many windows of imageing sensor drive be by on-site programmable gate array FPGA drives imageing sensor and to the configuration of register, make it to open a plurality of windows shooting grating encodings.
3) the present invention is by reducing the method that improves shooting speed without effect pixel, to drive and realize by described many windows, by reducing, in image is processed, act on little pixel to reach higher frame speed, accomplish that real-time is higher in the measuring process of grating scale.
4) placement of the present invention by the window's position obtains longer effective length with pixel still less, to drive based on described multiwindow, method by the scanning of oblique scanning or parabola replaces linear scanning, accomplishes to obtain better image processing effect with pixel still less.
5) the present invention is by using the method for on-site programmable gate array FPGA high speed acquisition view data, be by using on-site programmable gate array FPGA to build an Acquisition Circuit according to the data output timing of imageing sensor, can accomplish not leak the data that data and reliability better collect the grating encoding that imageing sensor spreads out of.
The present invention can rise to very fast by the speed of the speed of exposure one frame picture and collection one frame picture.The present invention is not only applicable to grating scale, and architectural configurations of the present invention is flexible, is applicable to modularized design, thereby reduces the construction cycle of product.In addition, the construction cycle of the present invention is short, is particularly suitable for high speed real time image processing system.
Accompanying drawing explanation
Fig. 1 is many windows view data high-velocity scanning of grating scale and the schematic diagram of harvester;
Fig. 2 is FPGA internal module schematic diagram;
Fig. 3 is many windows view data high-velocity scanning of grating scale and the flow chart of acquisition method;
Fig. 4 is the many windows schematic diagram in grating encoding;
Fig. 5 tiltedly scans schematic diagram.
Embodiment
The present invention is the high-velocity scanning of many windows view data and the harvester of grating scale, include cmos image sensor, on-site programmable gate array FPGA and static RAM SRAM, wherein the signal input part of on-site programmable gate array FPGA and the signal output part of cmos image sensor are connected, the signal output part of on-site programmable gate array FPGA is connected with the signal input part of static RAM SRAM, and the signal output part of static RAM SRAM is connected to the SRAM interface of DSP.
Above-mentioned on-site programmable gate array FPGA includes image data acquiring module, imageing sensor register configuration module, static RAM SRAM control module, and wherein the relation of image data acquiring module, imageing sensor register configuration module, these three modules of static RAM SRAM control module is relations of time order and function.First use imageing sensor register configuration block configuration imageing sensor, make it to carry out work according to our requirement, then use image data acquiring module to gather the picture signal that imageing sensor is captured, finally use static RAM SRAM control module that the picture signal collecting is deposited in SRAM, so that post-processed.
Many windows view data high-velocity scanning of grating scale of the present invention and the method for collection, include following steps:
1) use SCCB agreement that imageing sensor is configured to the operating state that many windows and window are lined up oblique line.
2) according to the view data output protocol of imageing sensor, gather the view data of imageing sensor output.
3) according to the input and output agreement of SRAM, the view data collecting is write in SRAM and stored, then read and be transferred to DSP to make post-processed from it.
The high speed acquisition of grating encoding and the specific implementation method of high-speed transfer are as follows:
First need the register of imageing sensor to be configured, just must be first according to the communication protocol of imageing sensor manufacturers design and configure its register.Use on-site programmable gate array FPGA to build the circuit that can communicate by letter with imageing sensor, its register is configured.
To the speed of its configuration and do not require that very fast, common MCU can accomplish, but because the collection of high speed image data will be gathered by on-site programmable gate array FPGA, so its configuration is also completed by on-site programmable gate array FPGA.
Use on-site programmable gate array FPGA to set up as follows with communicating by letter of the SCCB agreement of imageing sensor:
Two delivery outlets are set, and SIO_C and SIO_D, be respectively clock line and the data wire of SCCB communication protocol.
By system clock frequency division, make SIO_C clock line carry out redirect with the frequency of 100K-400K, the frequency of 100K is used in official's suggestion.
Send initial signal: at SIO_C, between high period, SIO_D line is dragged down, communication starts.
First write device address, the i.e. address of imageing sensor.
At SIO_C, between low period, change the level of SIO_D, data can be write into.Agreement regulation starts to pass from a high position.
After eight bit address are write, SIO_D is set to input port, a rear clock, and imageing sensor can return to a response bits, automatically SIO_D is dragged down, and confirms to have received that eight arrange address bit.
Harvest response bits and start and send out eight bit register address, then receive a response bits.
Send the value that sixteen bit will write register, response bits of every transmission eight bit image transducer auto-returneds.
Send an end signal: at SIO_C, be between high period, SIO_D line is drawn high by low, finish once communication.
Register that just can stable configuration imageing sensor by above sequential.
Address and the value timesharing that will write are assigned to a register variable, with a state machine, with above agreement timesharing, these register addresss and value are write in imageing sensor.
Imageing sensor is set to the pattern of windowing, rather than the crawl of picture in its entirety.And open a plurality of windows, could realize oblique scanner uni parabola scanning,
Configuration image transducer x0_start[m:0], x0_end[m:0], y0_start[n:0] and, y0_end[n:0] value of four registers region that can make first window.X1_start[m:0 is set again], x1_end[m:0], y1_start[n:0] and, y1_end[n:0] make second window, by that analogy.
These windows are lined up to an oblique line, can realize the effect of oblique scanning.Speed be risen to the requirement of real-time that meets grating scale, the area of these windows enough decodes grating encoding, and the pixel of exposure is fewer, and the time that captures each pictures is fewer, and the time of transmission is fewer.
Imageing sensor is set to white-black pattern.
Dividing of more than configuration nothing priority.After correct configuration image transducer, imageing sensor is by the output image data outward of the speed with very fast.
With on-site programmable gate array FPGA, gather this high-speed data more applicable.Here use on-site programmable gate array FPGA collection not need to use FIFO to carry out buffer memory, direct image data, in image data, accomplish the not delay to the time, to later image, process and leave time enough allowance, guarantee that the complete frame picture of every collection just can handle a frame picture, this real-time to grating scale plays very important effect.
With the newly-built acquisition module of on-site programmable gate array FPGA, according to LVDS serial output or CMOS parallel output sequential, data acquisition is entered to on-site programmable gate array FPGA storage inside.
Here the CMOS parallel output of take describes as example:
CMOS parallel output has frame synchronization line, row line synchro, and 10 of output clock and data wires, when frame synchronization line is low level, after a period of time, saltus step is high level, represents the beginning of a frame picture.When row line synchro is high level, data are effective, and during for low level, data are invalid, and row line synchro rising edge is that a line picture starts.When effective in the synchronous while of frame synchronization and row, each rising edge of output clock line represents valid data.
Programmable gate array FPGA inside is by a clock of frame synchronizing signal line storage at the scene, non-with the frame synchronization level of the previous clock of the frame synchronization level of a rear clock ' with ', if result is 1, frame synchronization trailing edge arrives, and is the beginning of a frame picture in the data that after this receive.
Programmable gate array FPGA inside is a clock of line synchronizing signal line storage at the scene, non-by the row sync level of the rear clock of the row sync level of previous clock ' with ', if result is 1,
The synchronous rising edge of going arrives, and is the beginning of picture a line in the data that after this receive.
Detection frame synchronizing signal is high level, and line synchronizing signal is while being high level, and the rising edge of each imageing sensor output clock reads in data in on-site programmable gate array FPGA.
In programmable gate array FPGA, write at the scene a static RAM SRAM controller, memory address and storage data are outputed in the address pin and data pin of static RAM SRAM, will write after enable signal WE drags down a period of time and draw high again and data can be write in static RAM SRAM.
When often collecting a view data, start static RAM SRAM write signal by the data that collect write with static RAM SRAM in store so that on-site programmable gate array FPGA is done the preliminary treatment of image and the transfer of data in later stage and image is processed.
The present invention compares with other prior aries, and its advantage is:
The present invention can rise to very fast by the speed of the speed of exposure one frame picture and collection one frame picture.The present invention is directed to grating scale, but be not only applicable to grating scale.Architectural configurations of the present invention is flexible, is applicable to modularized design, thereby reduces the construction cycle of product.And the construction cycle of itself is short, be particularly suitable for high speed real time image processing system.
The schematic diagram of the grating scale that after Fig. 4 tiltedly windows, camera photographs, has opened altogether 7 windows in figure, the area of each window is identical, and the grating length that can detect is like this starting to the end of the 7th window of the 1st window.In figure, black part is divided into imageing sensor except the part of window with external shield, and imageing sensor does not gather the part of image.Collection capacity and the transmission quantity of data have been reduced thus.
Fig. 5 tiltedly scans schematic diagram, the right-angle side that in figure, a and b are right-angled triangle, c is the hypotenuse of this right-angled triangle, c>a, c>b, by a, b is considered as two length of sides of the rectangle that imageing sensor can take, while window being arranged in to oblique line as figure tetra-, the effective length that can be used as image processing will be greater than direct use horizontal line scanning.
For above explanation, principal character and advantage of the present invention; the personnel of relevant every trade will be appreciated that; the present invention is not restricted to the described embodiments; the description of specification and enforcement just illustrates principle of the present invention; do not departing under the prerequisite of invention spirit and scope; the present invention also has various variations and upgrading, and these variations and upgrading all fall in the claimed scope of the invention.The claimed scope of the present invention is defined by appending claims and equivalent thereof.
Claims (3)
1. the high-velocity scanning of many windows view data and the harvester of a grating scale, it is characterized in that including cmos image sensor, on-site programmable gate array FPGA and static RAM SRAM, wherein the signal input part of on-site programmable gate array FPGA and the signal output part of cmos image sensor are connected, the signal output part of on-site programmable gate array FPGA is connected with the signal input part of static RAM SRAM, and the signal output part of static RAM SRAM is connected to the SRAM interface of DSP.
2. the high-velocity scanning of many windows of grating scale according to claim 1 view data and harvester, it is characterized in that above-mentioned on-site programmable gate array FPGA includes image data acquiring module, imageing sensor register configuration module, static RAM SRAM control module, wherein the relation of image data acquiring module, imageing sensor register configuration module, these three modules of static RAM SRAM control module is relations of time order and function; First use imageing sensor register configuration block configuration imageing sensor, make it to carry out work according to our requirement, then use image data acquiring module to gather the picture signal that imageing sensor is captured, finally use static RAM SRAM control module that the picture signal collecting is deposited in SRAM, so that post-processed.
3. a method for the high-velocity scanning of many windows of grating scale view data and collection, is characterized in that including following steps:
1) use SCCB agreement that imageing sensor is configured to the operating state that many windows and window are lined up oblique line;
2) according to the view data output protocol of imageing sensor, gather the view data of imageing sensor output;
3) according to the input and output agreement of SRAM, the view data collecting is write in SRAM and stored, then read and be transferred to DSP to make post-processed from it.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106841093A (en) * | 2017-03-31 | 2017-06-13 | 山东省科学院自动化研究所 | A kind of THz continuous wave fast accurate scanning system and method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN202013177U (en) * | 2011-04-15 | 2011-10-19 | 贵州英特利智能控制工程研究有限责任公司 | Grating ruler measurement device based on advanced reduced instruction set computer (RISC) machine (ARM) processor and field programmable gata array (FPGA) |
| CN202329560U (en) * | 2011-11-28 | 2012-07-11 | 贵州英特利智能控制工程研究有限责任公司 | Grating data acquisition card based on PCI (Peripheral Component Interconnect) interface |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202013177U (en) * | 2011-04-15 | 2011-10-19 | 贵州英特利智能控制工程研究有限责任公司 | Grating ruler measurement device based on advanced reduced instruction set computer (RISC) machine (ARM) processor and field programmable gata array (FPGA) |
| CN202329560U (en) * | 2011-11-28 | 2012-07-11 | 贵州英特利智能控制工程研究有限责任公司 | Grating data acquisition card based on PCI (Peripheral Component Interconnect) interface |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106841093A (en) * | 2017-03-31 | 2017-06-13 | 山东省科学院自动化研究所 | A kind of THz continuous wave fast accurate scanning system and method |
| CN106841093B (en) * | 2017-03-31 | 2023-09-08 | 山东省科学院自动化研究所 | Terahertz continuous wave rapid and accurate scanning system and method |
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