CN103647912B - Many windows view data high-velocity scanning of a kind of grating scale and the data high-speed scanner uni acquisition method of harvester - Google Patents
Many windows view data high-velocity scanning of a kind of grating scale and the data high-speed scanner uni acquisition method of harvester Download PDFInfo
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- CN103647912B CN103647912B CN201310691827.7A CN201310691827A CN103647912B CN 103647912 B CN103647912 B CN 103647912B CN 201310691827 A CN201310691827 A CN 201310691827A CN 103647912 B CN103647912 B CN 103647912B
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Abstract
The present invention is a kind of imageing sensor many windows view data high-velocity scanning and harvester and method, many windows view data high-velocity scanning of grating scale and harvester include cmos image sensor, on-site programmable gate array FPGA and static RAM SRAM, wherein the signal input part of on-site programmable gate array FPGA is connected with the signal output part of cmos image sensor, the signal output part of on-site programmable gate array FPGA is connected with the signal input part of static RAM SRAM, the signal output part of static RAM SRAM is connected to the SRAM interface of DSP.By the present invention in that by on-site programmable gate array FPGA high speed acquisition view data, in the case of imageing sensor translational speed is very fast, it is possible to photograph grating encoding clearly, make the difficulty of the image procossing in later stage be substantially reduced.The present invention is directed to absolute grating scale many windows of imageing sensor are driven；By reducing without acting as the method that vegetarian refreshments improves shooting speed；Longer effective length is obtained with less pixel by placing of the window's position.
Description
Technical field
The present invention relates to optical grating ruler measurement field based on image procossing, particularly relate to imageing sensor many windows view data
High-velocity scanning and harvester and method, belong to imageing sensor many windows view data high-velocity scanning and harvester and method
Innovative technology.
Background technology
At present, the principle of grating scale be substantially based on grating scale interfere or diffraction produce Moire fringe measure.
This method for designing is developed so far, although the most ripe, but still suffer from many not enough, such as principle is more numerous and diverse, circuit
Design comparison is complicated, it is desirable to the highest.
In this context, grating scale based on image procossing arises at the historic moment.And it is based on image procossing in the market
Grating scale can not be accomplished in the case of translational speed is very fast, it is ensured that the real-time of measurement.Reason is the crawl speed of image
Degree is fast not, and the crawl of whole spoke picture causes the exposure of a large amount of pixel and transmission waste of time.
Summary of the invention
It is an object of the invention to provide a kind of imageing sensor many windows view data high-velocity scanning and harvester.This
Bright in the case of imageing sensor translational speed is very fast, it is possible to photograph grating encoding clearly, make at the image in later stage
The difficulty of reason is substantially reduced.
Another object of the present invention is to provide a kind of as sensor many windows view data high-velocity scanning and acquisition method.This
The method of invention is convenient and practical.
The technical scheme is that the present invention is the view data high-velocity scanning of many windows and the harvester of grating scale, bag
Having included cmos image sensor, on-site programmable gate array FPGA and static RAM SRAM, wherein scene can be compiled
The signal input part of journey gate array FPGA is connected with the signal output part of cmos image sensor, on-site programmable gate array FPGA
Signal output part be connected with the signal input part of static RAM SRAM, static RAM SRAM's
Signal output part is connected to the SRAM interface of DSP.
Above-mentioned on-site programmable gate array FPGA includes image data acquiring module, imageing sensor register configuration mould
Block, static RAM SRAM control unit, wherein image data acquiring module, imageing sensor register configuration mould
Block, the relation of static RAM SRAM control unit these three module are the relations of time order and function.First by figure
As sensors register configuration modular configuration diagram is as sensor, it is allowed to be operated according to our requirement, then uses image
The picture signal that data collecting module collected imageing sensor is captured, finally uses static RAM SRAM to control
The picture signal collected is stored in SRAM by module, in order to the later stage processes.
Many windows view data high-velocity scanning of grating scale of the present invention and the method for collection, comprise the following steps that
1) use SCCB agreement that imageing sensor is configured to many windows and the duty of oblique line lined up by window.
2) the view data output protocol according to imageing sensor gathers the view data of imageing sensor output.
3) view data that will collect according to the input and output agreement of SRAM writes in SRAM and stores, then is read out from passing
It is defeated by DSP and processes to make the later stage.
The present invention compared with prior art, has the advantage that
1) high-velocity scanning of the present invention and acquisition method include driving many windows of imageing sensor for absolute grating scale；
By reducing without acting as the method that vegetarian refreshments improves shooting speed；Obtained more with less pixel by the placement of the window's position
Long effective length；By the method using on-site programmable gate array FPGA high speed acquisition view data.
2) many windows of imageing sensor are driven by the present invention is to drive image sensing by on-site programmable gate array FPGA
Device and to the configuration of depositor, make it possible to out the shooting grating encoding of multiple window.
3) present invention is by reducing without acting as the method that vegetarian refreshments improves shooting speed, is to be driven in fact by described many windows
Existing, in image procossing, act on little pixel by minimizing fast to reach higher frame, accomplish the measurement at grating scale
In journey, real-time is higher.
4) present invention obtains longer effective length by placing of the window's position with less pixel, is based on described many
Window drives, and replaces linear scanning by the method for tiltedly scanning or parabola scanning, accomplishes to obtain with less pixel
Better image treatment effect.
5) by the present invention in that by the method for on-site programmable gate array FPGA high speed acquisition view data, be by using
On-site programmable gate array FPGA builds an Acquisition Circuit according to the data output timing of imageing sensor, can accomplish not leak
Data and reliability preferably collect the data of the grating encoding that imageing sensor spreads out of.
The speed of the speed and collection one frame picture that expose a frame picture can be risen to the fastest by the present invention.The present invention
It is applicable not only to grating scale, and architectural configurations of the present invention is flexible, it is adaptable to modularized design, thus reduce the exploitation week of product
Phase.It addition, the present invention construction cycle is short, it is particularly suitable for high speed real time image processing system.
Accompanying drawing explanation
Fig. 1 is the view data high-velocity scanning of many windows and the schematic diagram of harvester of grating scale；
Fig. 2 is FPGA internal module schematic diagram；
Fig. 3 is the view data high-velocity scanning of many windows and the flow chart of acquisition method of grating scale；
Fig. 4 is the many windows schematic diagram in grating encoding；
Fig. 5 is for tiltedly scanning schematic diagram.
Detailed description of the invention
The present invention is the view data high-velocity scanning of many windows and the harvester of grating scale, include cmos image sensor,
On-site programmable gate array FPGA and static RAM SRAM, wherein the signal of on-site programmable gate array FPGA is defeated
Enter end is connected with the signal output part of cmos image sensor, the signal output part of on-site programmable gate array FPGA and static state with
The signal input part of machine access memorizer SRAM connects, and the signal output part of static RAM SRAM is connected to DSP
SRAM interface.
Above-mentioned on-site programmable gate array FPGA includes image data acquiring module, imageing sensor register configuration mould
Block, static RAM SRAM control unit, wherein image data acquiring module, imageing sensor register configuration mould
Block, the relation of static RAM SRAM control unit these three module are the relations of time order and function.First by figure
As sensors register configuration modular configuration diagram is as sensor, it is allowed to be operated according to our requirement, then uses image
The picture signal that data collecting module collected imageing sensor is captured, finally uses static RAM SRAM to control
The picture signal collected is stored in SRAM by module, in order to the later stage processes.
Many windows view data high-velocity scanning of grating scale of the present invention and the method for collection, comprise the following steps that
1) use SCCB agreement that imageing sensor is configured to many windows and the duty of oblique line lined up by window.
2) the view data output protocol according to imageing sensor gathers the view data of imageing sensor output.
3) view data that will collect according to the input and output agreement of SRAM writes in SRAM and stores, then is read out from passing
It is defeated by DSP and processes to make the later stage.
The high speed acquisition of grating encoding is as follows with the specific implementation method of high-speed transfer:
Configure firstly the need of to the depositor of imageing sensor, and configure its depositor and be necessary for first passing according to image
The communication protocol of sensor manufacturer design.On-site programmable gate array FPGA is used to build the electricity that can communicate with imageing sensor
Road, configures its depositor.
Being not required for quickly to its speed configured, common MCU can accomplish, but adopting due to high speed image data
Collection to be acquired by on-site programmable gate array FPGA, so also being completed its configuration by on-site programmable gate array FPGA.
On-site programmable gate array FPGA is used to set up as follows with the communication of the SCCB agreement of imageing sensor:
Two delivery outlets, the clock line of SIO_C and SIO_D, respectively SCCB communication protocol and data wire are set.
Being divided by system clock, make SIO_C clock line redirect with the frequency of 100K-400K, official's suggestion uses
The frequency of 100K.
Send initial signal: being between high period at SIO_C, dragged down by SIO_D line, communication starts.
First the address of write device address, i.e. imageing sensor.
It is between low period at SIO_C, changes the level of SIO_D, data can be write into.Agreement specifies from a high position
Start to pass.
After eight bit address being write, SIO_D being set to input port, later clock, imageing sensor can return one
Response bits, drags down SIO_D automatically, confirms that having been received by eight arranges address bit.
Harvest response bits and start to send out eight bit register address, then receiving a response bits.
Send the value of sixteen bit depositor to be write, often send eight one response bits of bit image sensor auto-returned.
Send an end signal: be between high period at SIO_C, SIO_D line is drawn high by low, terminates once to communicate.
Just can the depositor of stable configuration imageing sensor by above sequential.
Address is assigned to a register variable with value timesharing to be write, will with above agreement timesharing with a state machine
These register address write in imageing sensor with value.
Imageing sensor is set to the crawl of the pattern of windowing rather than picture in its entirety.And open multiple window and could realize tiltedly
Scanner uni parabola scans,
Configuration imageing sensor x0_start [m:0], x0_end [m:0], y0_start [n:0], y0_end [n:0] four
The value of individual depositor can make the region of first window.X1_start [m:0], x1_end [m:0], y1_start are set again
[n:0], y1_end [n:0] makes second window, by that analogy.
These windows are lined up an oblique line, the effect tiltedly scanned can be realized.Speed is risen to the reality meeting grating scale
The requirement of time property, the area of these windows enough decodes grating encoding, and the pixel of exposure is the fewest, captures each pictures
Time is the fewest, and the time of transmission is the fewest.
Imageing sensor is set to white-black pattern.
Configuration as above without priority point.After correct configuration imageing sensor, imageing sensor will be the most past
Outer output view data.
This high-speed data is gathered more applicable with on-site programmable gate array FPGA.Used here as field-programmable gate array
Row FPGA gathers and need not use FIFO to cache, and directly gathers data, accomplishes not drag the time gathering in data
Prolong, process to later image and leave time enough allowance, it is ensured that often gathered a frame picture and just can process a frame picture,
The real-time of grating scale is played very important effect by this.
With the newly-built acquisition module of on-site programmable gate array FPGA, according to LVDS Serial output or CMOS parallel output
Sequential, enters on-site programmable gate array FPGA storage inside by data acquisition.
Here illustrate as a example by CMOS parallel output:
CMOS parallel output has frame synchronization line, row line synchro, and output clock and data wire 10, when frame synchronization line is low electricity
Flat, after a period of time, saltus step is high level, represents the beginning of a frame picture.When row line synchro is high level, data are effective, for low
Data invalid during level, row line synchro rising edge is that a line picture starts.When frame synchronization and row synchronize the most effectively, during output
Each rising edge of clock line represents valid data.
Inside programmable gate array FPGA, frame synchronizing signal line is stored a clock at the scene, with the frame of later clock
The frame synchronization level of sync level ' with ' previous clock non-, if result is 1, then frame synchronization trailing edge arrives, and connects thereafter
The data received are the beginning of a frame picture.
Inside programmable gate array FPGA, line synchronising signal line is stored a clock at the scene, with the row of previous clock
The row sync level of sync level ' with ' later clock non-, if result is 1,
Then row synchronizes rising edge arrival, and the data received thereafter are the beginning of picture a line.
Detection frame synchronizing signal is high level, and when line synchronising signal is high level, during the output of each imageing sensor
Data are read in on-site programmable gate array FPGA by the rising edge of clock.
Write a static RAM SRAM controller at the scene in programmable gate array FPGA, address will be stored
And storage data export in address pin and the data pin of static RAM SRAM, write enable signal WE is drawn
Draw high again after low a period of time and can write data in static RAM SRAM.
Start static RAM SRAM write signal while often collecting a view data will collect
Data write and static RAM SRAM in store, in order to on-site programmable gate array FPGA do image pretreatment and
The data transmission in later stage and image procossing.
The present invention, compared with other prior aries, has an advantage in that:
The speed of the speed and collection one frame picture that expose a frame picture can be risen to the fastest by the present invention.The present invention
For grating scale, but it is applicable not only to grating scale.Architectural configurations of the present invention is flexible, it is adaptable to modularized design, thus reduces product
The construction cycle of product.And the construction cycle of itself is short, it is particularly suitable for high speed real time image processing system.
Fig. 4 tiltedly window after the schematic diagram of grating scale that photographs of photographic head, figure has been opened altogether 7 windows, the face of each window
The end started to the 7th window that grating length is the 1st window that is long-pending identical, that be so able to detect that.Black part in figure
It is divided into imageing sensor to remove the window part with external shield, i.e. imageing sensor and does not gather the part of image.Thereby reduce number
According to collection capacity and transmission quantity.
Fig. 5 tiltedly scans schematic diagram, and in figure, a and b is the right-angle side of right angled triangle, and c is the hypotenuse of this right angled triangle, then
C > a, c > b, a, b are considered as two length of sides of the rectangle that imageing sensor can shoot, when window arrangement being become oblique line such as figure four,
Can will be greater than directly using horizontal line to scan as the effective length of image procossing.
For above explanation, principal character and advantages of the present invention, the personnel of relevant every trade it should be understood that the present invention is not
Be restricted to the described embodiments, description and enforcement the principle that the present invention is simply described is described, without departing from spirit and
On the premise of scope, the present invention also has various change and upgrading, and these changes and upgrading both fall within claimed model of the present invention
In enclosing.Claimed scope is defined by appending claims and equivalent thereof.
Claims (2)
1. many windows view data high-velocity scanning of grating scale and a data high-speed scanner uni acquisition method for harvester, described
Many windows view data high-velocity scanning of grating scale and harvester include cmos image sensor, field programmable gate array
FPGA and static RAM SRAM, wherein the signal input part of on-site programmable gate array FPGA passes with cmos image
The signal output part of sensor connects, the signal output part of on-site programmable gate array FPGA and static RAM SRAM
Signal input part connect, the signal output part of static RAM SRAM is connected to the SRAM interface of DSP；Its feature
It is that data high-speed scanner uni acquisition method comprises the following steps that
1) use SCCB agreement that imageing sensor is configured to many windows and the duty of oblique line lined up by window；
2) the view data output protocol according to imageing sensor gathers the view data of imageing sensor output；
3) view data that will collect according to the input and output agreement of SRAM writes in SRAM and stores, then is read out from being transferred to
DSP processes to make the later stage.
Many windows view data high-velocity scanning of grating scale the most according to claim 1 and the data high-speed scanning of harvester
And acquisition method, it is characterised in that above-mentioned on-site programmable gate array FPGA includes image data acquiring module, image sensing
Device register configuration module, static RAM SRAM control unit, wherein image data acquiring module, image sensing
Device register configuration module, the relation of static RAM SRAM control unit these three module are the passes of time order and function
System；First by imageing sensor register configuration modular configuration diagram as sensor, image data acquiring module is then used to adopt
The collection picture signal captured of imageing sensor, finally uses static RAM SRAM control unit to collect
Picture signal is stored in SRAM, in order to the later stage processes.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202013177U (en) * | 2011-04-15 | 2011-10-19 | 贵州英特利智能控制工程研究有限责任公司 | Grating ruler measurement device based on advanced reduced instruction set computer (RISC) machine (ARM) processor and field programmable gata array (FPGA) |
| CN202329560U (en) * | 2011-11-28 | 2012-07-11 | 贵州英特利智能控制工程研究有限责任公司 | Grating data acquisition card based on PCI (Peripheral Component Interconnect) interface |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202013177U (en) * | 2011-04-15 | 2011-10-19 | 贵州英特利智能控制工程研究有限责任公司 | Grating ruler measurement device based on advanced reduced instruction set computer (RISC) machine (ARM) processor and field programmable gata array (FPGA) |
| CN202329560U (en) * | 2011-11-28 | 2012-07-11 | 贵州英特利智能控制工程研究有限责任公司 | Grating data acquisition card based on PCI (Peripheral Component Interconnect) interface |
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