CN104935885B - A kind of expansible multiplex image acquisition device based on AXI buses - Google Patents
A kind of expansible multiplex image acquisition device based on AXI buses Download PDFInfo
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Abstract
A kind of expansible multiplex image acquisition device based on AXI buses of the disclosure of the invention, a kind of image collecting device, the multiplex image acquisition technical field more particularly to based on Zynq.Two RAM are stored in respectively by carrying out ping-pong operation to the view data collected, then therefrom place to go is spliced respectively, it is stored in FIFO, data stream transmitting is ultimately produced to image processing module, complete the processing of image, so as to can Multi-channel high-efficient simultaneously gathered data, the advantages of processing speed is fast.
Description
Technical field
The invention belongs to a kind of image collecting device, the multiplex image acquisition technical field more particularly to based on Zynq.
Technical background
In wire rod, tubing visual defects detecting system, single camera can not complete the apparent panorama sketch to wire rod, tubing
As collection, pass through multiple cameras, multi-angled shooting, it is possible to achieve the apparent panoramic picture of wire rod, tubing is gathered.Conventional images
For harvester when setting multiple cameras, it is necessary to give each one image pick-up card of camera configuration, such cost is very high, and
Extra computing resource is needed in follow-up image procossing, significantly increases the time of calculating.
This method can dynamically be matched somebody with somebody according to information such as the wire rod of required detection, the diameter of tubing and accuracy of detection requirements
Connection camera number and camera mode of operation are put, it is convenient and practical.Zynq chips are SOC technical products of new generation, are answered based on IP
Developed with technology, IP interconnections are carried out by AXI buses.AXI stream are one kind in AXI buses, are mainly used in data
Streaming, speed is fast, and agreement is simple.
The content of the invention
The technical problems to be solved by the invention are that design is a kind of fast based on AXI bus processing speeds, and simple in construction can
Extend multiplex image acquisition device.
A kind of expansible multiplex image acquisition device based on AXI buses of the present invention, the device include:Multiple images gather
Branch road, concatenation module, fifo module, data flow generation module, image processing module, drive module, ARM；Wherein IMAQ
Branch road includes：Camera, camera link chips, data capture module, RAM1, RAM2, camera collection image information pass through
Cameralink chips are transferred to data capture module, and data capture module stores the data received progress ping-pong operation in turn
To RAM1 or RAM2, concatenation module reads data and spliced from RAM1 and RAM2, then writes FIFO；Data flow generates
Module reads view data from each IMAQ branch road FIFO, carries out integrating generation data flow, is then transferred to image procossing
Module；ARM control drive modules send driving data to other each modules.
Wherein ARM is configured by AXI lite buses to drive module；Data flow generation module passes through AXI
Stream buses are by data stream transmitting to image processing module.
A kind of expansible multiplex image acquisition device based on AXI buses of the present invention, passes through the view data to collecting
Carry out ping-pong operation and be stored in two RAM respectively, then therefrom place to go is spliced respectively, be stored in FIFO, ultimately produce data
Be streaming to image processing module, complete the processing of image, so as to can simultaneously Multi-channel high-efficient gathered data, processing speed
Spend the advantages of fast.
Brief description of the drawings
Fig. 1 is a kind of structural representation of the expansible multiplex image acquisition device based on AXI buses of the present invention.
Embodiment
1. present apparatus total system framework is as shown in Figure 1.
2.ARM configures to camera number and mode of operation, by AXI lite buses to camera drive module
Corresponding registers are configured.Configuration-direct is parsed, gives configuration information to view data trapping module and AXI stream numbers
According to stream generation module.Corresponding module defines relevant variable, entered according to the camera number of practical application and the mode of operation of camera
Row work.
3.ARM produces camera drive signal, and the corresponding registers of camera drive module are carried out by AXI lite buses
Configuration, by parsing ARM configuration-directs, camera driver' s timing is produced using Zynq logical resources, drive signal is sent to
The LVTTL signals that Zynq is sent are changed into LVDS signals by camera link chips, camera link chips, and LVDS signals lead to
Cross camera link cables and be sent to camera, driving camera work.
After 4. camera obtains activation bit, start working, by the view data of collection by camera link cables with
LVDS signal modes are sent to camera link chips, and the LVDS signals that camera is sent are changed into by camera link chips
LVTTL signals, it is then passed to Zynq chip internals.
5. view data trapping module produces image data acquiring sequential by internal logic resource, to camera image data
It is acquired.
6. view data trapping module first passes through logic and produces corresponding time sequence, first to each camera clock signal rising edge
Captured respectively, phase adjusted is carried out according to camera link view data and the phase relation of clock, to ensure to collect
View data it is reliable and stable.The signals such as FVAL, LVAL, DVAL according to camera link and the rising edge clock of capture
Signal, the effective view data of each camera is respectively cached write-in ram in slice.The view data of each camera
Cached using two RAM, by ping-pong operation, just change another RAM after caching a line view data every time and carry out down
The caching of a line view data.
7. concatenation module, a line view data in the current RAM for not carrying out write operation is read respectively, is write in FIFO,
Complete the splicing of view data, caching.
8.AXI stream data flow generation modules, after having data in monitoring to cache FIFO, the image that will splice
Data read-out, data flow is generated according to AXI stream bus standards, data flow length is multiplied by equal to camera single row of pixels number
Camera number, and give view data to processing system with data-stream form and carry out image procossing.
Claims (1)
1. a kind of expansible multiplex image acquisition device based on AXI buses, the device include:Multiple images collection branch road, spell
Connection module, fifo module, data flow generation module, image processing module, drive module, ARM；Wherein IMAQ branch road bag
Include：Camera, camera link chips, data capture module, RAM1, RAM2, camera collection image information pass through camera
Link chips are transferred to data capture module, and data capture module stores the data received progress ping-pong operation to RAM1 in turn
Or RAM2, concatenation module read data and spliced from RAM1 and RAM2, then write FIFO；Data flow generation module from
View data is read in each IMAQ branch road FIFO, carries out integrating generation data flow, is then transferred to image processing module；
ARM control drive modules send driving data to other each modules；
It is characterized in that the ARM is configured by AXI lite buses to drive module；Data flow generation module passes through AXI
Stream buses are by data stream transmitting to image processing module；
The ARM configures to camera number and mode of operation, the phase by AXI lite buses to camera drive module
Register is answered to be configured.Configuration-direct is parsed, gives configuration information to view data trapping module and AXI stream data
Flow generation module.Corresponding module defines relevant variable, carried out according to the camera number of practical application and the mode of operation of camera
Work；
The ARM produces camera drive signal, and the corresponding registers of camera drive module are matched somebody with somebody by AXI lite buses
Put, by parsing ARM configuration-directs, produce camera driver' s timing using Zynq logical resources, drive signal is sent to camera
The LVTTL signals that Zynq is sent are changed into LVDS signals by link chips, camera link chips, and LVDS signals pass through
Camera link cables are sent to camera, driving camera work；
After the camera obtains activation bit, start working, by the view data of collection by camera link cables with
LVDS signal modes are sent to camera link chips, and the LVDS signals that camera is sent are changed into by camera link chips
LVTTL signals, it is then passed to Zynq chip internals；
Described image data capture module produces image data acquiring sequential by internal logic resource, and camera image data is entered
Row collection；
Described image data capture module first passes through logic and produces corresponding time sequence, first to each camera clock signal rising edge point
Do not captured, phase adjusted is carried out according to camera link view data and the phase relation of clock, to ensure what is collected
View data is reliable and stable；According to camera link FVAL, LVAL, DVAL signal and the rising edge clock signal of capture,
The effective view data of each camera is respectively cached write-in ram in slice；The view data of each camera uses
Two RAM are cached, and by ping-pong operation, are cached a line view data every time and are just changed another RAM progress next lines afterwards
The caching of view data；
The concatenation module, a line view data in the current RAM for not carrying out write operation is read respectively, is write in FIFO, it is complete
Into the splicing of view data, caching；
The AXI stream data flow generation modules, after having data in monitoring to cache FIFO, the picture number that will splice
According to reading, data flow is generated according to AXI stream bus standards, data flow length is multiplied by phase equal to camera single row of pixels number
Machine number, and give view data to processing system with data-stream form and carry out image procossing.
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| CN105208355A (en) * | 2015-10-21 | 2015-12-30 | 合肥华凌股份有限公司 | Refrigerator data acquisition method and system as well as refrigerator |
| CN107608654B (en) * | 2017-09-14 | 2021-02-12 | 中国科学院半导体研究所 | Transmission control device and method for multi-path asynchronous information |
| CN109410804B (en) * | 2018-09-14 | 2021-09-28 | 武汉帆茂电子科技有限公司 | V-by-one signal generation device and method based on FPGA |
| CN111711745B (en) * | 2020-05-06 | 2021-06-22 | 中国科学院西安光学精密机械研究所 | Portable camera link data acquisition system and acquisition method |
| CN114449131A (en) * | 2021-11-29 | 2022-05-06 | 王乐群 | Moving target detection system based on ZYNQ acceleration |
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| CN102176737A (en) * | 2011-03-20 | 2011-09-07 | 北京艾科瑞德科技有限公司 | System for collecting and processing 10K*10K ultrahigh resolution images |
| CN202393715U (en) * | 2012-01-04 | 2012-08-22 | 西安工程大学 | Automatic detecting device for grey cloth defect spot |
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| CN102004709B (en) * | 2009-08-31 | 2013-09-25 | 国际商业机器公司 | Bus bridge between processor local bus (PLB) and advanced extensible interface (AXI) and mapping method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102176737A (en) * | 2011-03-20 | 2011-09-07 | 北京艾科瑞德科技有限公司 | System for collecting and processing 10K*10K ultrahigh resolution images |
| CN202393715U (en) * | 2012-01-04 | 2012-08-22 | 西安工程大学 | Automatic detecting device for grey cloth defect spot |
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