CN108012053A - A kind of high speed image Transmission system based on CoaXPress interfaces - Google Patents
A kind of high speed image Transmission system based on CoaXPress interfaces Download PDFInfo
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- CN108012053A CN108012053A CN201711134148.4A CN201711134148A CN108012053A CN 108012053 A CN108012053 A CN 108012053A CN 201711134148 A CN201711134148 A CN 201711134148A CN 108012053 A CN108012053 A CN 108012053A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/50—Constructional details
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/50—Constructional details
- H04N23/54—Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
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Abstract
The invention discloses a kind of high speed image Transmission system based on CoaXPress interfaces, includes the use of high-speed cmos sensor and is used to gather visible images, the image capture module being AD converted to the analog image of collection；By master element FPGA, receive the view data that image capture module collects and carry out data processing, including data training, data point reuse, image rectification and the image processing module that data processing is carried out according to data format as defined in CoaXPress agreements；Receive the view data after image processing module processing, using CoaXPress interfaces and its respective drive chip, the data transmission module being transmitted to processed view data；The power module being powered respectively to image capture module, image processing module and data transmission module.The present invention solve the problems, such as existing high speed camera video data can not real-time Transmission, realize 1000 frames/second speed, image resolution ratio is 1280 × 1024 pixels, and the high speed image that data locating depth is 8Bits transmits.
Description
Technical field
The invention belongs to high speed image data transmission field, and in particular to a kind of high speed based on CoaXPress interfaces
Image delivering system.
Background technology
The reach of science promotes exploration of the mankind to finer, the more delicate world.In modern industrial production, control and section
Learn in research, various high speed motions are observed, data collection and analysis becomes more and more significant.In military field engineering
Aspect, by recording and analyzing each transient state in high speed change procedure, such as arm discharge, shell track, gunpowder explosion, fire
Flight etc., significantly more efficient approach is provided for experimental study, weaponry design and improvement；In terms of industrial production, pass through reality
When monitor production line on part defect, improve production efficiency, turn avoid artificial missing inspection and false retrieval；In automobile making side
Face, by studying the change at car crass moment each position and the force-bearing situation of manikin, produces safety coefficient higher
Automobile.
Under the light stimulus of intermediate light, it is only 12 ~ 16 frames/second that the human eye vision limit, which differentiates frequency, can not observe tens,
Hundreds of even the high-speed motion phenomenon of thousands of frames.Further, since " freezing " ability of common camera technology is limited, have in observation
When having the motion process that certain speed changes, the ambiguous phenomenon such as image slanting or even hangover often occurs, speed is higher,
Picture quality is poorer.Therefore, Fast Phenomena can be shot by developing one kind, and is slowed down to human eye vision and can differentiated
The video camera of degree, it appears it is particularly important that.
The high-speed photography equipment of early stage is mainly ray machine formula high speed camera, and such camera coordinates high quick-action with optical principle
The mechanical structure of work completes the observation and record to quick change procedure.According to the difference of working method, ray machine formula high speed camera
Three kinds of intermittent high-speed camera, optical compensation formula high speed camera and High-speed Rotating-mirror Camera can be divided into.Although with regard to shooting speed
Speech, ray machine formula high speed camera can reach the needs of observation and record, but due to the use of film as storage medium, unavoidably
Introduce the cumbersome Film processing work such as development, fixing, be then just able to carry out the analysis of data, this results in ray machine formula
High speed camera back-end processing speed is slow, can not the image that was photographed of Real Time Observation；And parallax error is big, in test easily by
To interference；The film quantity to be expended during high-speed capture is also excessive, and use cost further increases, and the above is difficult to overcome
The drawbacks of constrain the development of film type high speed camera.With the development of electronic technology, there is height in the 90's of last century
Speed digital formula camera.
Currently, it can realize that the detector of " taking the photograph slow play soon " technology is broadly divided into CCD and CMOS two types.In recent years,
Ccd image sensor occupies certain position with the features such as noise is small, high sensitivity in field of photography, but its resolution ratio with frame frequency not
It can get both, image quality, increase device cost and device power consumption will certainly be lost when pursuing high-speed photography.However, cmos sensor
And there is no the trade-off problem of frame frequency and resolution ratio, under mega pixel resolution ratio shooting speed up to 1000fps even more highs,
Compared with CCD, more accurate transient information can be provided for transient study, becomes the useful tool of transient study.
The mass data storage of high speed imaging system and the counting bottleneck that collection is always design.More than 1000 frames
High speed imaging system, it requires to handle the view data of a whole frame within 1ms, is more than 1000*1000, data bit in resolution ratio
When number is 10bit, its data volume is very big, it is necessary to using other methods more than 10Gbps, real-time intractability.Currently on the market
The image data acquiring of high-speed camera usually first stores image using high speed mass data storage units, then again
Carry out processing to send to the method completion of Computer display, this Method And Principle is simple, right although high speed image cannot be handled in real time
In high speed high definition imaging system be the method for unique feasible.
Chinese patent 200910021207.6, discloses a kind of high frame frequency and high resolution CMOS imaging system, using CPLD as
Control unit, using SDRAM as storage unit in high speed, realizes 500 frames, the high frame frequency and high resolution of 1280*1024 resolution ratio
Imaging, but SDRAM storage speeds are slower, and data bandwidth is smaller, is not suitable for the number of high-resolution imaging systems more than 1000 frames
According to caching, and the power supply of detector and other units is not separated, noise is larger, and image effect is general, in addition, using general
Data-interface transmits view data, can only realize caching display.
The content of the invention
The object of the present invention is to provide a kind of high speed image Transmission system based on CoaXPress interfaces, solve existing
High speed camera video data can not real-time Transmission the problem of, realize 1000 frames/second speed, image resolution ratio for 1280 ×
1024 pixels, the high speed image that data locating depth is 8Bits transmit.
The technical solution for realizing the object of the invention is：A kind of high speed image transmission system based on CoaXPress interfaces
System, including
It is used to gather visible images using high-speed cmos sensor, the Image Acquisition for being AD converted the analog image of collection
Module；
By master element FPGA, receive the view data that image capture module collects and carry out data processing, including data instruction
White silk, data point reuse, image rectification and the image procossing that data processing is carried out according to data format as defined in CoaXPress agreements
Module；
The view data after image processing module processing is received, using CoaXPress interfaces and its respective drive chip, to processing
The data transmission module that the view data crossed is transmitted；
The power module being powered respectively to image capture module, image processing module and data transmission module.
Described image acquisition module is acquired exterior visible images after being powered, the pixel data quilt after opto-electronic conversion
On piece ADC digital, then digital signal, which is serialized, send to lvds driver, finally with 16 road LVDS difference forms to outside piece
Output, and with two-way LVDS differential clock signals, i.e. pixel clock PCLKP/N and data clock DCLKP/N.
The FPGA of described image processing module employs the EP4S100G5H40I2 of Altera Stratix IV GT series,
Turned by the string in FPGA and high speed LVDS data receiver IP kernel LVDS_RX are to the serioparallel exchange of sensor output data, to string
And transformed data carry out data training and data point reuse, and Nonuniformity Correction is carried out, the data after correction pass through at a high speed
Serial transceiver IP kernel ALTGX carries out high speed serialization processing.
Described image transport module includes 4 CoaXPress interface driver chips, and driving chip uses
The EQCO31T20 of Microchip companies, by the processed view data of image processing module, sends to the number of driving chip
According to input terminal, each chip exports a pair of of high-speed differential serial data, the high-speed differential serial data by bnc interface and
Coaxial cable is transmitted to image pick-up card.
The power module is powered by the way of DC-DC and LDO are combined, using DC-DC chips that the 12V of input is electric
Press and be converted into 5V, 3.6V, 3.3V, 2.5V, 1.8V, 1.2V, 1.5V, 1.4V, 1.1V, 0.95V, 0.9V, wherein 3.0V, 2.5V,
1.8V, 1.5V, 1.1V, 0.95V and 0.9V are used to power to image processing module；1.2V is used to power to image transmission module；
5V voltage conversions are powered into 3.3V, 3.0V, 2.5V, 1.8V to image capture module using LDO chips.
Compared with prior art, the present invention significantly the advantages of, has：
（1）The CoaXPress interfaces used are a kind of point-to-point serial communication interface standards of high speed, can pass through a coaxial electrical
Cable connects camera with host, and single cable transmission rate highest can reach 6.25Gbps, can be come using more cables
Increase bandwidth, so as to meet the requirement of high frame frequency camera real-time Transmission.
（2）The driving of CoaXPress interfaces is controlled by FPGA, compared with other high-speed interfaces, it is only necessary to seldom
FPGA resource.
（3）Driving chip only needs EQCO62T20 a kind of, and peripheral circuit is simpler, and can carry out two-way communication.
Brief description of the drawings
Fig. 1 is the high speed image Transmission system entire block diagram of the invention based on CoaXPress interfaces.
Fig. 2 is that system data flows to schematic diagram.
Fig. 3 is CoaXPress interface protocol transmission rule schematic diagrames.
Fig. 4 is EQCO31T20 peripheral circuit diagrams.
Embodiment
The present invention is described in further detail below in conjunction with the accompanying drawings：
A kind of high speed image Transmission system based on CoaXPress interfaces, image capture module using high-speed cmos chip into
Row Image Acquisition and digital-to-analogue conversion, using FPGA as control element, are driven sensor, and the image collected is carried out
Processing；On-chip memory need not be reused cached and exported again；By the way of DC-DC power source and LDO power supplys are combined
It is powered, power consumption is lower, and noise is smaller；High speed image transmission is carried out using CoaXPress interfaces, utilizes four coaxial electricals
Cable, data transmission bauds can reach 3.125Gbps on every cable, and the total speed of data reaches 12.5Gbps, can complete in real time
Transmit the high speed image data transmission of 1000 frame 1280*1024 resolution ratio.
With reference to Fig. 1, a kind of high speed transmission system based on CoaXPress interfaces includes image capture module, image procossing
Module, image transmission module and power module.Image capture module gathers visible images using high-speed cmos sensor, and right
The analog image of collection is AD converted；Image processing module is carried out the view data collected by master element FPGA
Data processing, including data training, data point reuse, image rectification and according to data format as defined in CoaXPress agreements into
Row data processing etc..Data transmission module uses CoaXPress interfaces and its respective drive chip, to processed view data
It is transmitted.
During using high speed image Transmission system of the present invention based on CoaXPress interfaces, by camera lens, Image Acquisition
Module, image processing module, power module, data transmission module and computer are sequentially connected, and wherein camera lens passes through external frame
It is fixed on immediately ahead of the cmos detector of image capture module, bnc interface and the computer of data transmission module pass through coaxial electrical
Cable is connected, and remainder is attached by piece connector.
The core of image capture module is to use high-speed cmos sensor, and what is used in the present invention is with high-speed cmos sensor
The high-speed cmos sensor LUX1310 of luxima companies of the U.S. is a for high speed machines vision, industry and biomedical city
The high speed global shutter CMOS digital image sensor of the 1280*1024 pixels 1000fps of field.This cmos digital image sensing
Device is easily integrated, and has been internally integrated low noise 12bit pipeline ADCs, is programmed on supporting pieces, the parallel LVDS outputs in 16 tunnels.Modulus
Converter ADC converts analog signals into 12bit digital signals.Then gone here and there by the ADC digital signals changed and turn to 1bit numbers
According to flowing and be sent into lvds driver.In order to reduce the bit rate of lvds driver, using 16 road lvds drivers.User can be with
By X, Y opens a window to obtain the frame frequency of higher.
Image data processing unit core is FPGA, and the FPGA that the present invention uses is the stratix IV of altera companies
GT series EP4S100G5H40I2, have abundant clock sources and high-speed differential interface, the high speed that can be transmitted with receiving front-end
Differential data, while high-speed data is handled；Comprising abundant SERDES blocks, i.e. high-speed transceiver module, can meet
The parallel-serial conversion of high-speed data.In the present invention, it is necessary to carry out high speed serialization processing to the processed parallel signals of FPGA, in order to
Realize the function, calling is IP kernel ALTGX in model FPGA, and each transceiver passage in device can be with one solely
Vertical data rate or an independent protocol mode operation.In each transceiver people having a common goal, transmitters and receivers passage is not with
Same data rate operation, what is be used in the present invention is configured to Transmitter only, i.e., has only used in transceiver
Serializer module.Partial data flow direction is as shown in Figure 2.The 16 road LVDS view data that front end is transmitted, every one group of 4 tunnel are transmitted to
Se pializer section, serializer are arranged to BASIC（PMA Direct）PMA is used only in functional mode, in this mode, all passages
Module is configured；Number of channels selection 4；The single width of wide data path selection（Single-width）, this pattern exists
Run between 600Mbps and 3.75Gbps, meet the bandwidth requirement of the present invention；Interface width is selected between FPGA architecture and transceiver
Select 8；Input clock frequency selects 90M.
Power supply module provides burning voltage for the chip of whole system, in order to reduce power consumption, reduces noise, power supply unit is adopted
Powered with DC-DC with the LDO modes being combined, 12V voltages reach power supply unit by connector, and power supply unit mainly uses
The TPS6213X series DC-DC chips of DC-DC chip LT3693, TI companies and the DC-DC cores of TOREX companies of LINER companies
Piece XC9272.12V voltages are classified as simulation 12V and numeral 12V, digital 12V by magnetic bead first and are converted into through power supply chip
For the chips such as FPGA, Flash, RS485 use, simulation 12V and numeral 12V be also converted into respectively 5V, 3.6V, 3.3V, 2.5V,
1.8V, 1.2V, 1.5V, 1.4V, 1.1V, 0.95V, 0.9V, wherein, voltage needed for image acquisition units is provided by LDO chips,
Since LDO input and output electric currents are identical, in order to reduce power consumption, pressure drop cannot be excessive, thus by power supply unit output 3.6V and
2.5V reaches the input voltage for the power supply chip that image acquisition units are used as on the unit by connector.
Data transmission module is the core of the present invention, in the design of the module, is divided into two parts：First, CoaXPress
Interface protocol；Second, the design of CoaXPress driving chips part.
CoaXPress interface protocols define trigger, general purpose I/O, control data and high-speed data-flow on the link
Transmission rule, as shown in Figure 3.Wherein, trigger has limit priority, and any relatively low in the appropriate convenient insertion of transmission
The transmission packet of priority；For high-speed data, agreement regulation, view data is sent in the form of data packet by link,
Packet transport layer is responsible for cutting view data blocking, and adds head and afterbody so as to form packet；Controlling data is then
For providing register access, equipment is transferred to from host, and slave device is sent to the result confirmation message of host.
The driving chip of CoaXPress interfaces employs the EQCO31T20 of Microchip companies, which sends
Speed is 3.125Gbps, receiving velocity 20Mbps, there is corresponding EQCO31R20 chips on corresponding capture card,
EQCO31T/R20 single coaxial cables chipset design be used on single 75 Ω coaxial cables at the same time send and receive signal with
And power supply.In one direction, down link signal is sent.In the opposite direction, there is provided a uplink compared with low speed
Road.EQCO31T20 fundamental diagrams are as shown in Figure 4.By calculating the bandwidth of front-end image data acquisition unit output data, it is
11.25Gbps, according to CoaXPress interface bandwidths, base patterns, i.e. every cable speed 3.125Gbps can be selected, it is necessary to
Use four cables；Or selection full patterns, i.e. every cable speed is 6.25Gbps, it is necessary to use two cables.Full
Pattern is to the more demanding of SERDES, it is necessary to FPGA costly, and power consumption can be excessive, therefore selection makes in the present invention
With the base patterns of CoaXPress, by four cable transmissions, every cable speed is 2.8125Gbps, is meeting conveyor
While wide, surplus has been left for the transmission of every cable.
Claims (5)
- A kind of 1. high speed image Transmission system based on CoaXPress interfaces, it is characterised in that：IncludingIt is used to gather visible images using high-speed cmos sensor, the Image Acquisition for being AD converted the analog image of collection Module；By master element FPGA, receive the view data that image capture module collects and carry out data processing, including data instruction White silk, data point reuse, image rectification and the image procossing that data processing is carried out according to data format as defined in CoaXPress agreements Module；The view data after image processing module processing is received, using CoaXPress interfaces and its respective drive chip, to processing The data transmission module that the view data crossed is transmitted；The power module being powered respectively to image capture module, image processing module and data transmission module.
- 2. the high speed image Transmission system according to claim 1 based on CoaXPress interfaces, it is characterised in that：It is described Image capture module is acquired exterior visible images after being powered, and the pixel data after opto-electronic conversion is by piece ADC digital Change, then digital signal, which is serialized, send to lvds driver, is finally exported with 16 road LVDS difference forms to outside piece, and adjoint Two-way LVDS differential clock signals, i.e. pixel clock PCLKP/N and data clock DCLKP/N.
- 3. the high speed image Transmission system according to claim 1 based on CoaXPress interfaces, it is characterised in that：It is described The FPGA of image processing module employs the EP4S100G5H40I2 of Altera Stratix IV GT series, by FPGA String turns and high speed LVDS data receiver IP kernel LVDS_RX are to the serioparallel exchange of sensor output data, to the number after serioparallel exchange According to the training of progress data and data point reuse, and Nonuniformity Correction is carried out, the data after correction pass through high speed serialization transceiver IP Core ALTGX carries out high speed serialization processing.
- 4. the high speed image Transmission system according to claim 1 based on CoaXPress interfaces, it is characterised in that：It is described Image transmission module includes 4 CoaXPress interface driver chips, and driving chip uses Microchip companies EQCO31T20, by the processed view data of image processing module, sends to the data input pin of driving chip, Mei Gexin Piece exports a pair of of high-speed differential serial data, and the high-speed differential serial data are transmitted to by bnc interface and coaxial cable Image pick-up card.
- 5. the high speed image Transmission system according to claim 1 based on CoaXPress interfaces, it is characterised in that：It is described Power module is powered by the way of DC-DC and LDO are combined, using DC-DC chips by the 12V voltage conversions of input into 5V, 3.6V, 3.3V, 2.5V, 1.8V, 1.2V, 1.5V, 1.4V, 1.1V, 0.95V, 0.9V, wherein 3.0V, 2.5V, 1.8V, 1.5V, 1.1V, 0.95V and 0.9V are used to power to image processing module；1.2V is used to power to image transmission module；Using LDO cores Piece powers 5V voltage conversions into 3.3V, 3.0V, 2.5V, 1.8V to image capture module.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109947376A (en) * | 2019-04-04 | 2019-06-28 | 上海威固信息技术股份有限公司 | A kind of multi-protocol interface solid-state memory system realized based on FPGA |
| CN110740257A (en) * | 2019-10-12 | 2020-01-31 | 南京理工大学 | high-speed high-definition CMOS imaging system and imaging method thereof |
| CN111131738A (en) * | 2019-12-20 | 2020-05-08 | 合肥埃科光电科技有限公司 | Image acquisition system based on CoaXPress interface and acquisition method thereof |
| CN111314641A (en) * | 2020-02-18 | 2020-06-19 | 东南大学 | System and method for acquiring, storing and displaying high-frame-frequency image |
| CN111427829A (en) * | 2020-03-13 | 2020-07-17 | 浙江华睿科技有限公司 | Low-speed uplink signal demodulation circuit of CoaXPres protocol and driving circuit of CoaXPres protocol |
| CN113206957A (en) * | 2021-04-30 | 2021-08-03 | 重庆西山科技股份有限公司 | Image processing method and system for endoscope and storage medium |
| CN113301286A (en) * | 2021-05-13 | 2021-08-24 | 合肥开拓导航控制技术有限责任公司 | FPGA-based uplink and downlink data processing and analog video image acquisition system |
| CN114726927A (en) * | 2021-11-30 | 2022-07-08 | 武汉卓目科技有限公司 | Conversion system and method for Coaxpress high-speed image interface and optical fiber transmission interface |
| CN117835073A (en) * | 2024-03-04 | 2024-04-05 | 深圳市度申科技有限公司 | Image acquisition system based on FPGA |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109947376A (en) * | 2019-04-04 | 2019-06-28 | 上海威固信息技术股份有限公司 | A kind of multi-protocol interface solid-state memory system realized based on FPGA |
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| CN111131738A (en) * | 2019-12-20 | 2020-05-08 | 合肥埃科光电科技有限公司 | Image acquisition system based on CoaXPress interface and acquisition method thereof |
| CN111314641A (en) * | 2020-02-18 | 2020-06-19 | 东南大学 | System and method for acquiring, storing and displaying high-frame-frequency image |
| CN111314641B (en) * | 2020-02-18 | 2022-05-10 | 东南大学 | System and method for acquiring, storing and displaying high-frame-frequency image |
| CN111427829A (en) * | 2020-03-13 | 2020-07-17 | 浙江华睿科技有限公司 | Low-speed uplink signal demodulation circuit of CoaXPres protocol and driving circuit of CoaXPres protocol |
| CN111427829B (en) * | 2020-03-13 | 2022-03-01 | 浙江华睿科技股份有限公司 | Low-speed uplink signal demodulation circuit of CoaXPres protocol and driving circuit of CoaXPres protocol |
| CN113206957A (en) * | 2021-04-30 | 2021-08-03 | 重庆西山科技股份有限公司 | Image processing method and system for endoscope and storage medium |
| CN113301286A (en) * | 2021-05-13 | 2021-08-24 | 合肥开拓导航控制技术有限责任公司 | FPGA-based uplink and downlink data processing and analog video image acquisition system |
| CN114726927A (en) * | 2021-11-30 | 2022-07-08 | 武汉卓目科技有限公司 | Conversion system and method for Coaxpress high-speed image interface and optical fiber transmission interface |
| CN117835073A (en) * | 2024-03-04 | 2024-04-05 | 深圳市度申科技有限公司 | Image acquisition system based on FPGA |
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Application publication date: 20180508 |