CN116539160A - Uncooled infrared detector imaging and thermal time constant testing system and method - Google Patents
Uncooled infrared detector imaging and thermal time constant testing system and method Download PDFInfo
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- 238000012360 testing method Methods 0.000 title claims abstract description 41
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
- G01J2005/0077—Imaging
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides an imaging and thermal time constant testing system and method of an uncooled infrared detector, wherein the system comprises the following components: the device comprises a case, an FPGA board card, a power board card module, a non-refrigeration infrared detector, a chopper and a surface source radiation blackbody; the FPGA board card and the power supply module are arranged in the case; the chopper is arranged between the detector and the surface source radiation blackbody, the centers of the surface source radiation blackbody, the chopper and the detector are positioned on the same horizontal line, the chopper is used for generating signals under different frequencies, and the surface source radiation blackbody is used for providing a light source for the detector; the FPGA board is connected with the non-refrigeration infrared detector and is used for generating a detector driving signal and receiving image data acquired by the detector; and the upper computer processes the acquired image data to obtain a thermal time constant. When the invention collects images, two independent fifo are used for caching odd-numbered lines and even-numbered lines and directly output according to the lines, so that additional on-board caching is not needed, and resources are saved.
Description
Technical Field
The invention belongs to a detector imaging test technology, and particularly relates to a non-refrigeration type infrared detector imaging and thermal time constant test system and method.
Background
With the recent development of technology, particularly in microelectronics and optoelectronics, a wide variety of infrared devices are in the field of view of people and are widely used in civil and military fields. Because the infrared radiation wave bands emitted by different objects are specific, by utilizing the characteristic of the substance, the technology that people distinguish and detect the objects by judging the specific infrared radiation wave bands and detect invisible infrared radiation and convert the invisible infrared radiation into a measurable signal is the infrared detection technology.
In recent years, the demand of the rapid development of the semiconductor process manufacturing technology is continuously increased, and meanwhile, the development of the technology in the future is promoted, and meanwhile, the technology of the uncooled infrared focal plane detector is low in cost and relatively low in price, compared with the uncooled infrared detector, the uncooled infrared focal plane detector has the advantages of lower cost, smaller power consumption, lighter weight, smaller volume and high starting and stabilizing speed compared with the uncooled infrared detector, so that the infrared detector has wider application and development space, and is easy to promote in the future because of better development prospect and space, and meanwhile, the uncooled infrared focal plane detector is low in cost and relatively low in price, so that the urgent demands of civil infrared systems and infrared systems of partial large-scale equipment can be met.
The uncooled infrared focal plane detector technology has raised a new revolution of infrared technology, and has very wide application and development prospects in the military and civil fields. For one technology, an important component which is often indispensable in the design and manufacturing process is a test verification technology, so that the corresponding test verification technology of the uncooled infrared focal plane detector has important promotion significance and practical value for design improvement and application development research of a future focal plane.
The infrared detector testing method provided by the infrared detector testing system developer in foreign well known places is widely applied to military and civil fields and is widely accepted by users, but most manufacturers implement export blocking on the middle part due to the sensitivity of infrared detection technology and the important significance of the testing system to the development of the infrared detector, and a small part of infrared detector testing systems or equipment which can be exported to China also have the problems of high price, inconvenient later maintenance and the like.
Research work of infrared detector testing systems has also been carried out successively by a plurality of infrared detector manufacturers and related scientific research institutions in China. The practical testing system adapting to the self-product is designed and formulated, and certain popularization and application are performed. However, there are still some differences in terms of the degree of automation of the test system, the stability of the test system, and the test accuracy, as compared with foreign products.
Disclosure of Invention
In order to solve the technical defects in the prior art, the invention provides an imaging and testing system of an uncooled infrared detector.
The technical scheme for realizing the purpose of the invention is as follows: an uncooled infrared detector imaging and thermal time constant testing system, comprising: the device comprises a case, an FPGA board card, a power board card module, a non-refrigeration infrared detector, a chopper and a surface source radiation blackbody;
the FPGA board card and the power supply module are arranged in the case;
the chopper is arranged between the detector and the surface source radiation blackbody, the centers of the surface source radiation blackbody, the chopper and the detector are positioned on the same horizontal line, the chopper is used for generating signals under different frequencies, and the surface source radiation blackbody is used for providing a light source for the detector;
the FPGA board is connected with the non-refrigeration infrared detector and is used for generating a detector driving signal and receiving image data acquired by the detector;
and the upper computer processes the acquired image data to obtain a thermal time constant.
Preferably, the uncooled infrared detector is arranged on the detector interface board, and is connected with a connector on the FPGA board through a differential signal connector arranged on the detector interface board, so that the connection between the FPGA board and the uncooled infrared detector is realized.
Preferably, a detector clamp is arranged in the middle of the detector interface board and used for fixing the detector and connecting the detector with the interface board, two differential signal interfaces with 68 pins are arranged on the left side and the right side and used for connecting with a connector, further carrying out data transmission with an FPGA board card, and the upper end and the lower end of the interface board are provided with power connectors.
Preferably, the uncooled infrared detector works in a working state that the frame frequency is 25Hz and the resolution is 1280 x 1024, the main clock of the uncooled infrared detector is 162MHz, pixel data is converted into a digital signal through an A/D conversion module on a chip and is output in a four-way LVDS differential mode in a serial mode, and one-way differential clock signal is associated.
Preferably, the FPGA board is internally provided with a Kintex-7FPGA chip.
Preferably, the power supply board is a programmable power supply board, and provides 3.6V analog power supply, 1.8V digital power supply and 3.6V-10V bias power supply for the detector.
Preferably, image data is acquired at different chopping frequencies, the chopping frequencies of the chopper being 0Hz, 2Hz, 4Hz, 6Hz, 8Hz, 10Hz, 12Hz, respectively.
The invention also provides an imaging and thermal time constant testing method of the uncooled infrared detector, which comprises the following specific steps:
step 1, starting a blackbody radiation source, and adjusting a chopper to a specific frequency;
step 2, writing I by using Verilog code 2 C, configuring a driver program by the aid of the detector, generating an edf netlist file, calling the edf netlist file by the aid of the Labview platform by the aid of the upper computer of the case, generating a detector configuration driving IP core, writing the function program into the FPGA board, driving the detector by the aid of the FPGA board by using the detector configuration driving IP core, and transmitting driving signals to the detector through the detector interface board;
step 3, the infrared detector receives the driving signal, acquires an infrared image, generates digital image data and sends the digital image data to the FPGA board through the interface board;
step 4, the FPGA board restores the acquired data according to the even number of the odd number rows;
step 5, the FPGA board caches the image data of the odd lines and the even lines in two FIFOs respectively, and outputs the image data according to the odd-even sequence;
step 6, the upper computer collects and stores the image data of continuous 100 frames output by the FPGA board card;
step 7, the upper computer reads the stored pictures through a thermal time constant test program, takes pixel values of 100 frames of images at a certain point, stores the pixel values into an array, and carries out Fourier transform on 100 groups of data to restore response values under corresponding chopping frequencies;
step 8, changing the modulation frequency of the chopper to 0Hz, 2Hz, 4Hz, 6Hz, 8Hz, 10Hz and 12Hz, repeating the above steps to obtain 7 groups of response values corresponding to different response frequencies, fitting the obtained 7 groups of data to obtain a frequency response curve, and taking outThe corresponding cut-off frequency is calculated according to the formula, and the thermal time constant is displayed on the front panel of the upper computer.
Compared with the prior art, the invention has the remarkable advantages that: (1) According to the invention, the FPGA board is used for realizing the driving and data acquisition of the detector, the NI system upper computer is used for storing image data and testing, the integration of the imaging and testing of the detector is realized, the thermal time constant can be measured in real time after the image is acquired by the detector, and the Labview written operation interface is used, so that the operation is simple and the automation is strong. (2) When the invention collects images, two independent fifo are used for caching odd-numbered lines and even-numbered lines and directly output according to the lines, so that additional on-board caching is not needed, and resources are saved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, like reference numerals being used to refer to like parts throughout the several views.
FIG. 1 is a block diagram of an uncooled infrared detector imaging and testing system of the present invention.
FIG. 2 is a diagram of the imaging test system equipment connections of the uncooled line infrared detector imaging and test system of the present invention.
FIG. 3 is a flow chart of image acquisition for the uncooled line infrared detector imaging and testing system of the present invention.
Fig. 4 is a diagram of image data restoration analysis of the uncooled line infrared detector imaging and testing system of the present invention.
FIG. 5 is a block diagram of a detector interface board of the uncooled line infrared detector imaging and testing system of the present invention.
FIG. 6 is a block diagram of a detector clamp of the uncooled infrared detector imaging and testing system of the present invention.
Fig. 7 is a front panel of the upper computer testing software of the uncooled infrared detector camera testing system of the present invention.
Detailed Description
It is easy to understand that various embodiments of the present invention can be envisioned by those of ordinary skill in the art without altering the true spirit of the present invention in light of the present teachings. Accordingly, the following detailed description and drawings are merely illustrative of the invention and are not intended to be exhaustive or to limit or restrict the invention. Rather, these embodiments are provided so that this disclosure will be thorough and complete by those skilled in the art. Preferred embodiments of the present invention are described in detail below with reference to the attached drawing figures, which form a part of the present application and are used in conjunction with embodiments of the present invention to illustrate the innovative concepts of the present invention.
The invention is conceived of a non-refrigeration type infrared detector imaging and thermal time constant testing system, comprising: the device comprises a case, an FPGA board card, a power board card module, a non-refrigeration infrared detector, a chopper and a surface source radiation blackbody;
the FPGA board card and the power supply module are arranged in the case;
the chopper is arranged between the detector and the surface source radiation blackbody, the centers of the surface source radiation blackbody, the chopper and the detector are positioned on the same horizontal line, the chopper is used for generating signals under different frequencies, and the surface source radiation blackbody is used for providing a light source for the detector;
the FPGA board is connected with the non-refrigeration infrared detector and is used for generating a detector driving signal and receiving image data acquired by the detector;
and the upper computer processes the acquired image data to obtain a thermal time constant.
Referring to fig. 2 and 3, a method for imaging an uncooled infrared detector and testing a thermal time constant includes the following specific steps:
step 1, providing 3.6V analog power supply, 1.8V digital power supply and 3.6V-10V bias power supply for a detector interface board through an upper computer control power supply module;
starting a blackbody radiation source, and adjusting a chopper to a specific frequency;
step 2, writing I by using Verilog code 2 C detector configuration driver, I is realized through a state machine 2 C, writing a starting signal, an equipment address, a register address and data, writing configuration information into a self-built lookup table, sequentially writing, forming an edf netlist file by using a function RTL code, calling the edf netlist file by using a host computer of a case, generating a detector configuration driving IP core, writing the function program into an FPGA board, performing detector driving by using the detector configuration driving IP core by using the FPGA board, and transmitting a driving signal to a detector through a detector interface board: the FPGA board card used in the invention is a built-in Kintex-7FPGA chip, and a differential signal connector is required to be inserted into the interface of the FPGA board card to realize the input and output of data. Through written I 2 C, configuring an IP core by a register, outputting corresponding initialization configuration information to a detector, and finishing driving of a detection container;
and 3, receiving a driving signal by the infrared detector, collecting an infrared image and generating digital image data, wherein differential data connectors at two ends of the interface board are connected with the connectors through differential data lines, and further, the four-channel image data, clock data of one channel and frame synchronization data of one channel are sent to the FPGA board card. The uncooled infrared detector used in the invention works in a working state that the frame frequency is 25Hz, the resolution is 1280 x 1024, the main clock of the sensor is 162MHz, pixel data is converted into a digital signal through an A/D conversion module on a chip, and the digital signal is output in a serial mode in a four-way LVDS differential mode, and is accompanied by one-way differential clock signal and one-way differential frame synchronizing signal. The detector outputs a pixel value of 16bit wide and the output clock is 50MHz.
After receiving the driving signal, the infrared detector generates a 16-bit random number a and puts the 16-bit random number a into a register, reads data in the address of the register through an FPGA board card, and calculates to obtain a key value, wherein the calculation formula is as follows:
b＝a×2 16 +a×2 10 +a×2 4 +1
key＝b/4
and writing the 32-bit configuration key obtained through calculation into a register address corresponding to the detector through the FPGA board card, waiting for 100ms, reading data in the register address of the decryption result, and if the data bit 1 is read, indicating that the verification key is finished, and starting to acquire image data and frame synchronization signals.
And 4, restoring the received image data of the four channels by the FPGA board card according to the mode of fig. 3, wherein the first eight bits of data of every sixteen bits of channel A and channel B are alternately arranged to obtain first 16-bit data of odd lines, the second eight bits of data of odd lines are alternately arranged to obtain second 16-bit data of odd lines, the first eight bits of data of every sixteen bits of data of channel C and channel D are alternately arranged to obtain first 16-bit data of even lines, the second eight bits of data of even lines are alternately arranged to obtain second 16-bit data of even lines, and the like, so that the image data of even lines and even lines are restored. The data transmission channel outputs a specific identifier 1010_0000 at the beginning of each row, and the hexadecimal mark displayed after the intersecting arrangement is 0xcc00;
and 5, the FPGA board caches the odd-numbered lines and the even-numbered lines of the restored image data respectively by using two FIFOs, and sets a counter for calculating the line number, judging the effective reading and writing time of the FIFOs according to the line synchronizing signal and the frame synchronizing signal, judging whether the lines are the odd-numbered lines or the even-numbered lines according to the last bit of the binary number value of the counter, writing one line of data into the FIFO of the odd-numbered lines when the frame synchronizing limiting signal is high and the last bit of the counter is 0, and writing one line of data into the FIFO of the even-numbered lines when the frame synchronizing limiting signal is high and the line synchronizing signal is effective and the last bit of the counter is 0. And sequentially pulling up the read enabling of the odd line FIFO and the even line FIFO according to the odd line mark, and when the data buffered in the FIFO is larger than one line, starting to transmit the data to the upper computer, and respectively storing the acquired continuous 100 frames of images by the upper computer.
Step 6, the upper computer collects and stores the image data of continuous 100 frames output by the FPGA board card;
step 7, the upper computer reads the stored pictures through a thermal time constant test program, takes pixel values of 100 frames of images at a certain point, stores the pixel values into an array, and carries out Fourier transform on 100 groups of data to restore response values under corresponding chopping frequencies;
and 8, changing the modulation frequencies of the choppers to 0Hz, 2Hz, 4Hz, 6Hz, 8Hz, 10Hz and 12Hz, repeating the contents in the steps 1-5, and respectively storing 100 frames of image data obtained under 7 groups of chopper modulation frequencies.
And (3) circularly processing 100 frames of images by using an upper computer test program written by Labview, setting an extraction range, extracting a pixel region with the central position of 3 multiplied by 3, and sequentially storing the pixel region into an array. Carrying out average value solving on the extracted array with the pixel values, and solving in a mode of circularly accumulating and dividing the array with the pixel values by the total number; and the pixel mean value of each frame of picture is stored into an array through a shift register, so that a pixel mean value sampling array storing 100 pixel mean values is obtained. And carrying out FFT conversion on 100 pixel data in the array, restoring the detector response value under the chopping frequency, repeating the steps, sequentially processing 7 groups of image information under different frequency modulation, restoring the response values under different chopping frequencies, and storing the response values and the corresponding frequency values into two arrays respectively. Performing curve fitting on the obtained response frequency and response value of the detector to obtain a frequency response curve, and taking the maximum value of the response curveThe frequency corresponding to this is referred to as the cut-off frequency f.
From the determined cut-off frequency f, a thermal time constant can be determined, as follows:
τ＝1/2πf
and calculating the thermal time constant according to a formula at the upper computer, displaying the thermal time constant on the front panel, and completing the test.
The present invention is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present invention are intended to be included in the scope of the present invention.
It should be appreciated that in the above description of exemplary embodiments of the invention, various features of the invention are sometimes described in the context of a single embodiment or with reference to a single figure in order to streamline the invention and aid those skilled in the art in understanding the various aspects of the invention. The present invention should not, however, be construed as including features that are essential to the patent claims in the exemplary embodiments.
It should be understood that modules, units, components, etc. included in the apparatus of one embodiment of the present invention may be adaptively changed to arrange them in an apparatus different from the embodiment. The different modules, units or components comprised by the apparatus of the embodiments may be combined into one module, unit or component or they may be divided into a plurality of sub-modules, sub-units or sub-components.
Claims (10)
1. An uncooled infrared detector imaging and thermal time constant testing system, comprising: the device comprises a case, an FPGA board card, a power board card module, a non-refrigeration infrared detector, a chopper and a surface source radiation blackbody;
the FPGA board card and the power supply module are arranged in the case;
the chopper is arranged between the detector and the surface source radiation blackbody, the centers of the surface source radiation blackbody, the chopper and the detector are positioned on the same horizontal line, the chopper is used for generating signals under different frequencies, and the surface source radiation blackbody is used for providing a light source for the detector;
the FPGA board is connected with the non-refrigeration infrared detector and is used for generating a detector driving signal and receiving image data acquired by the detector;
and the upper computer processes the acquired image data to obtain a thermal time constant.
2. The uncooled infrared detector imaging and thermal time constant testing system according to claim 1, wherein the uncooled infrared detector is arranged on a detector interface board and is connected with a connector on an FPGA board through a differential signal connector arranged on the detector interface board, so as to realize connection of the FPGA board and the uncooled infrared detector.
3. The uncooled infrared detector imaging and thermal time constant testing system according to claim 2, wherein a detector clamp is arranged in the middle of the detector interface board and is used for fixing the detector and connecting the detector with the interface board, two differential signal interfaces with 68 pins are arranged on the left side and the right side and are used for connecting with connectors so as to carry out data transmission with an FPGA board, and power connectors are arranged on the upper end and the lower end of the interface board.
4. The system for testing the imaging and thermal time constants of the uncooled infrared detector according to claim 1, wherein the uncooled infrared detector works in a working state that the frame frequency is 25Hz and the resolution is 1280 x 1024, the main clock of the uncooled infrared detector is 162MHz, pixel data is converted into a digital signal through an on-chip A/D conversion module, and the digital signal is output in a four-way LVDS differential mode in a serial mode and is accompanied by one-way differential clock signal.
5. The uncooled infrared detector imaging and thermal time constant testing system of claim 1, wherein the FPGA board is embedded with a kenex-7 FPGA chip.
6. The uncooled infrared detector imaging and thermal time constant testing system of claim 1, wherein the power board is a programmable power board providing 3.6V analog power, 1.8V digital power and 3.6V-10V bias power for the detector.
7. The uncooled infrared detector imaging and thermal time constant testing system of claim 1, wherein image data is collected at different chopping frequencies, the chopper chopping frequencies being 0Hz, 2Hz, 4Hz, 6Hz, 8Hz, 10Hz, 12Hz, respectively.
8. The imaging and thermal time constant testing method of the uncooled infrared detector is characterized by comprising the following steps of:
step 1, starting a blackbody radiation source, and adjusting a chopper to a specific frequency;
step 2, writing I by using Verilog code 2 C, configuring a driver program by the aid of the detector, generating an edf netlist file, calling the edf netlist file by the aid of the Labview platform by the aid of the upper computer of the case, generating a detector configuration driving IP core, writing the function program into the FPGA board, driving the detector by the aid of the FPGA board by using the detector configuration driving IP core, and transmitting driving signals to the detector through the detector interface board;
step 3, the infrared detector receives the driving signal, acquires an infrared image, generates digital image data and sends the digital image data to the FPGA board through the interface board;
step 4, the FPGA board restores the acquired data according to the even number of the odd number rows;
step 5, the FPGA board caches the image data of the odd lines and the even lines in two FIFOs respectively, and outputs the image data according to the odd-even sequence;
step 6, the upper computer collects and stores the image data of continuous 100 frames output by the FPGA board card;
step 7, the upper computer reads the stored pictures through a thermal time constant test program, takes pixel values of 100 frames of images at a certain point, stores the pixel values into an array, and carries out Fourier transform on 100 groups of data to restore response values under corresponding chopping frequencies;
step 8, changing the modulation frequency of the chopper to 0Hz, 2Hz, 4Hz, 6Hz, 8Hz, 10Hz and 12Hz, repeating the above steps to obtain 7 groups of response values corresponding to different response frequencies, fitting the obtained 7 groups of data to obtain a frequency response curve, and taking out 1/2 The corresponding cut-off frequency is calculated according to the formula, and the thermal time constant is displayed on the front panel of the upper computer.
9. The uncooled line infrared detector imaging and thermal time constant test method of claim 8, wherein the image data recovery format in step 4 is as follows: the detector outputs four channels of data, the first eight bits of every sixteen bits of data of the channel 1 and the channel 2 are alternately arranged to obtain first 16bit data of odd lines, the second eight bits of data are alternately arranged to obtain second 16bit data of odd lines, the first eight bits of every sixteen bits of data of the channel 3 and the channel 4 are alternately arranged to obtain first 16bit data of even lines, the second eight bits of data are alternately arranged to obtain second 16bit data of even lines and the like, image data of even lines and even lines are restored, a specific identifier 1010_0000 is output by the data transmission channel at the beginning of each line, and a hexadecimal mark displayed after the cross arrangement is 0xcc00 _00 and marks the beginning of one line of data.
10. The method for imaging and testing the thermal time constant of the uncooled infrared detector according to claim 8, wherein the specific process of obtaining the thermal time constant is as follows:
image reading: 100 times of circulation are carried out through a Labview circulation structure, 100 frames of images collected under each frequency are sequentially read and stored, an extraction range is set through adding an image revolution group function module, and pixel values of pixel points in a 3*3 area in the middle of the images are extracted and stored in an array;
solving a pixel mean value: carrying out average value solving on the pixel value arrays of the extracted pixel points, defining an initial empty array, adding a circulating structure, adding a register in the circulating structure, sequentially entering elements in the array into a circulating body, sequentially accumulating, accumulating the output accumulation and the output accumulation of the end of the circulation, obtaining the pixel average value, solving the pixel average value of each frame of picture, storing the pixel average value into the empty array, and obtaining a sampling array with 100 frames of image pixel average values after 100 times of circulation;
fourier transform: setting the acquisition frequency as 25Hz and the data length as 100, carrying out fast Fourier transform on the pixel mean sampling array obtained in the last step through an FFT conversion function, carrying out maximum value extraction on the restored function to obtain a maximum value max_data, and then using a cyclic scanning abscissa, wherein when the corresponding ordinate value is equal to max_data, the abscissa corresponds to the response frequency, the ordinate corresponds to the response value, respectively storing the abscissa and the ordinate into two empty arrays, changing the chopper frequency to obtain the response frequency and the response value under different modulation frequencies, and sequentially storing the response frequency and the response value into the arrays to obtain two groups of data;
thermal time constant test solution: fitting the obtained response frequency and response value to obtain a frequency response curve of the detector, and comparing the values through the loop body to obtain the maximum value of the curveThe abscissa corresponding to the position is the cut-off frequency f, and the relation between the cut-off frequency f and the time constant is calculated: τ=1/(2ρf), and the obtained time constant is displayed on the front panel. .
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| CN117146990A (en) * | 2023-08-30 | 2023-12-01 | 北京波谱华光科技有限公司 | Low-frame-frequency external triggering method and system based on uncooled infrared detector |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117146990A (en) * | 2023-08-30 | 2023-12-01 | 北京波谱华光科技有限公司 | Low-frame-frequency external triggering method and system based on uncooled infrared detector |
| CN117146990B (en) * | 2023-08-30 | 2024-03-08 | 北京波谱华光科技有限公司 | Low-frame-frequency external triggering method and system based on uncooled infrared detector |
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