CN112689072A - Camera system - Google Patents
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- CN112689072A CN112689072A CN202011531986.7A CN202011531986A CN112689072A CN 112689072 A CN112689072 A CN 112689072A CN 202011531986 A CN202011531986 A CN 202011531986A CN 112689072 A CN112689072 A CN 112689072A
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Abstract
The invention discloses a camera system, which comprises a high-speed multi-view camera main system used for sensor configuration, and receiving, analyzing and transmitting sensor pixel data; the high-speed multi-view camera subsystem is used for receiving, caching and transmitting multi-sensor image data; the high-speed multi-view camera main system comprises a sensor module, a processing and control unit and a main system Cameralink sending module; the high-speed multi-view camera subsystem comprises a subsystem Cameralink receiving module, an image storage module, a data transmission module and a storage control and transmission unit. The invention has the advantages of high system integration level, small size, flexible image acquisition control, high image acquisition speed and the like.
Description
Technical Field
The invention relates to the technical field of industrial image acquisition of machine vision, in particular to a high-speed multi-view camera system.
Background
With the continuous development of technology, machine vision is widely applied in the industrial field. The multi-view camera is a camera system with a plurality of imaging units, can control different imaging units to shoot different objects simultaneously, and is widely applied to the field of industrial detection and the field of SMT (surface mount technology).
Most of the existing industrial multi-view camera systems adopt a mode of independent control and separate acquisition of a plurality of camera modules; and the image data are respectively transmitted to an upper computer acquisition terminal through a data bus, and the synthesis and processing of each image data are completed by an upper computer terminal. Most of the existing multi-view camera systems have the following disadvantages: (1) a plurality of camera modules exist in the multi-camera module system and are respectively in direct connection with the acquisition terminal, so that the camera acquisition terminal has various interfaces, the system is complex, the integration level is low, and the size is large. (2) The multiple camera modules in the system are independently controlled, and most of the multiple camera modules are only provided with one acquisition terminal and one control terminal, so that the camera control is not flexible enough, and the interconnection work among the camera modules cannot be met. (3) The data bus adopts network port transmission or other low-speed bus transmission, the bandwidth is limited, the acquisition time is long, and the acquisition speed is generally not high; can not be applied to the field of high-speed SMT surface mounting.
The current market is lack of a multi-view camera system with integrated sensor modules and capable of realizing high-speed acquisition.
Disclosure of Invention
In order to solve the above problems, the present invention provides a camera system, so as to solve the problems of single multi-sensor control and slow image acquisition speed, and improve the image acquisition speed, so that the image acquisition control is more flexible.
In order to achieve the purpose, the invention adopts the following technical scheme:
the camera system of the present invention is characterized by comprising: a high-speed multi-view camera main system and a high-speed multi-view camera subsystem;
the high-speed multi-view camera main system includes: the system comprises a sensor module, a processing and control unit and a Cameralink sending module;
the processing and control unit comprises: the device comprises a sensor configuration module, a trigger control module, an image analysis module and a transmission control module;
the image parsing module includes: the system comprises an MIPI deserializing module, a data analyzing module and an FIFO cache module;
the transmission control module includes: the device comprises a frame header packaging module, an image frame counter, an image line counter, an image caching module, an error monitoring module and a caching reading control module;
the sensor module generates an original serial data stream and sends the original serial data stream to the MIPI deserializing module for serial-parallel conversion processing, and original merged parallel data are obtained and then sent to the data analyzing module; the data analysis module carries out image data extraction processing on the original merged parallel data to obtain image pixel data and then stores the image pixel data into the FIFO cache module;
the frame header packaging module reads the image pixel data from the FIFO cache module, and performs frame header packaging processing on the image pixel data according to the image frame sequence number and the line sequence number information provided by the image frame counter and the image line counter and the monitoring state information provided by the error monitoring module to obtain packaged processing pixel data and store the packaged processing pixel data in the image cache module;
the cache reading control module reads the packaged processing pixel data from the multiple image cache modules by using a cyclic competition reading control method and sends the processing pixel data to the Cameralink sending module, so that the processing pixel data is sent to the high-speed multi-view camera subsystem through the Cameralink sending module;
the high-speed multi-view camera subsystem includes: the system comprises a Cameralink receiving module, a storage control and transmission unit, an image storage module and an image transmission module;
and the Camera link receiving module of the high-speed multi-view camera subsystem receives the processed pixel data and sends the processed pixel data to the storage control and transmission unit for unpacking and controlling storage processing, after unpacking pixel data is obtained, the unpacking pixel data is stored into different cache regions of the image storage module according to frame header information, and the image transmission module sequentially reads the unpacking pixel data from the image storage module and transmits the unpacking pixel data to the terminal equipment.
The camera system of the invention is characterized in that: the sensor configuration module receives the control command from the Cameralink sending module and communicates with the sensor module through an I2C interface.
The trigger control module is connected with the sensor module through an IO interface and controls the sensor module to shoot.
The MIPI deserializing module comprises: a bit alignment module and a Lane alignment module;
the bit alignment module carries out deserializing and bit synchronization processing on the received original serial data stream to obtain original parallel data; and the Lane alignment module performs data alignment and merging processing on the original parallel data in each channel to obtain the original merged parallel data.
The data analysis module comprises: the frame header extraction module, the pixel extraction module and the pixel data synthesis module;
the frame header extraction module extracts frame header information of the original combined parallel data to obtain frame header information;
the pixel extraction module extracts effective pixel information of the parallel data from which the frame header information is removed to obtain a pixel data stream of each channel;
and the pixel data synthesis module is used for merging the pixel data streams of the multiple channels to finally obtain the image pixel data.
The frame header extraction module judges the starting position of the data frame and the starting position of the line pixels by judging the frame starting and line starting mark characters.
The cyclic competition reading control method is carried out according to the following steps:
(1) entering a sending waiting state after the initialization configuration of the main system is completed;
(2) circularly judging the image cache modules, and selecting the image cache module with a high priority level to start a corresponding reading function according to the priority level transmitted by the sensor in the register configuration information after monitoring that the data access amount of the image cache modules reaches a preset threshold value;
(3) and after the image cache module with the high priority finishes reading, finishing reading the image cache modules with the low priority in sequence, immediately entering a sending waiting state after all the image cache modules meeting the threshold condition finish reading, and returning to the step 2 to start the next cycle judgment.
The high-speed multi-view camera subsystem Cameralink receiving module is connected with the high-speed multi-view camera main system Cameralink sending module; the Cameralink receiving module and the Cameralink transmitting module both include: a signal IO interface, a serial port signal interface and an image signal LVDS interface;
the trigger control module receives a trigger level signal from the high-speed multi-view camera subsystem through the IO interface and controls the sensor module to take a picture;
the sensor configuration module receives an instruction from the high-speed multi-view camera subsystem through the serial port signal interface and communicates with the sensor module through an I2C interface;
the image signal LVDS interface is a physical channel for image transmission between the high-speed multi-view camera main system and the subsystem.
Compared with the traditional multi-view camera system, the invention has the following beneficial effects:
the system is realized based on a Cameralink interface, and has the advantages of high integration level, small size and simple system; a plurality of sensor modules are integrated in one board card, so that the control is flexible; compared with other multi-view camera systems, the multi-view camera system has only one set of Cameralink interfaces and the number of interfaces is small.
2, the invention has fast image acquisition speed, and each sensor module carries out exposure and image acquisition simultaneously, and transmits a plurality of image data through pixel combination processing, thereby realizing the simultaneous image acquisition of all sensors.
3, the invention has flexible control of image acquisition, and the sensor modules are uniformly controlled by one control and processing unit; the instruction sent by the upper computer can be received, and the map is drawn by controlling 1 sensor module or a plurality of sensor modules; and there is no requirement for the control sequence.
Drawings
Fig. 1 is a diagram of the camera system of the present invention.
FIG. 2 is a block diagram of the high-speed multi-view camera main system processing and control unit system architecture according to the present invention.
Fig. 3 is a system architecture diagram of the image analysis module of the high-speed multi-view camera main system according to the present invention.
Fig. 4 is a system architecture diagram of the transmission control module of the high-speed multi-view camera main system according to the present invention.
Fig. 5 is a schematic diagram of the multi-view camera host system according to the present invention performing merging processing on image data of a plurality of sensors.
FIG. 6 is a flow chart of a buffer read operation in the transmission control module according to the present invention.
Reference numbers in the figures: 100-a sensor module; 101-a first sensor module; 102-a second sensor module; 103-a third sensor module; 104-a fourth sensor module; 105-a fifth sensor module; 106-a sixth sensor module; 107-a seventh sensor module; 108-an eighth sensor module; 200-a high-speed multi-view camera main system processing and control unit; 210-a sensor configuration module; 220-trigger interface module; 230-MIPI parsing module; 231-MIPI deserializing module; 232-data analysis module; 233-FIFO buffer; 240-transmission control module; 241-frame header encapsulation module; 242-image frame counter; 243-image line counter; 244-image caching module; 245-a cache read control module; 246-error monitoring module; 300-a high-speed multi-view camera main system Cameralink sending module; 400-a high-speed multi-view camera subsystem Cameralink receiving module; 500-high speed multi-view camera subsystem storage control and transmission unit; 600-an image storage module; 700-an image transmission module; 800-terminal equipment.
Detailed Description
A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings.
As shown in fig. 1, a camera system includes: the system comprises a high-speed multi-view camera main system for carrying out sensor configuration, receiving, analyzing and transmitting sensor pixel data and a high-speed multi-view camera subsystem for carrying out multi-sensor image data receiving, caching and transmitting;
as shown in fig. 1, the high-speed multi-view camera main system includes: a sensor module 100, a processing and control unit 200, a Cameralink transmission module 300; the sensor module 100 is connected to the processing and control unit 200, and the processing and control unit 200 is connected to the Cameralink transmission module 300.
As shown in fig. 1, the high-speed multi-view camera subsystem includes: a Cameralink receiving module 400, a storage control and transmission unit 500, an image storage module 600, and an image transmission module 700; the Cameralink receiving module 400 of the high-speed multi-view camera subsystem is connected with the Cameralink sending module 300 of the high-speed multi-view camera subsystem, the Cameralink receiving module 400 is connected with the storage control and transmission unit 500, the image storage module 600 is connected with the storage control and transmission unit 500, the image transmission module 700 is connected with the storage control and transmission unit 500, and the image transmission module 700 is connected with the terminal device 800.
As shown in fig. 1, the Cameralink receiving module 400 of the high-speed multi-view camera subsystem receives and processes pixel data and sends the pixel data to the storage control and transmission unit 500 for unpacking and storage control processing, so as to obtain unpacked pixel data, store the unpacked pixel data into different buffer areas of the image storage module 600 according to frame header information, and the image transmission module sequentially reads the unpacked pixel data from the image storage module 600 and transmits the unpacked pixel data to the terminal device.
The sensor module and the processing and control unit 200 should include the following interfaces:
(1) an image data LVDS output MIPI interface;
(2) an I2C interface for configuring the register of the sensor module;
(3) and triggering the IO interface of the sensor module for collecting the image.
As shown in fig. 1, both the Cameralink receiving module 400 and the Cameralink transmitting module 300 include: the system comprises a signal IO interface, a serial port signal interface and an image signal LVDS interface.
The trigger control module receives a trigger level signal from the high-speed multi-view camera subsystem through an IO interface and controls the sensor module to take a picture;
the sensor configuration module receives an instruction from the high-speed multi-view camera subsystem through a serial port signal interface and communicates with the sensor module through an I2C interface.
The image signal LVDS interface is a physical channel for image transmission between the main system and the subsystem of the high-speed multi-view camera.
As shown in fig. 2, the processing and control unit 200 includes: a sensor configuration module 210, a trigger control module 220, an image parsing module 230, and a transmission control module 240.
As shown in fig. 2, the MIPI image data sent by the sensor modules 101-108 sequentially passes through the MIPI deserializing module 231 and the data analyzing module 232 and is stored in the FIFO buffer module 233. The FIFO buffer module transmits the parsed image data stream to the transmission control module 240.
As shown in fig. 2, sensor configuration module 210 receives control commands from Cameralink transmission module 300 and communicates with the sensor module via an I2C interface.
As shown in fig. 2, the trigger control module 220 is connected to the sensor module through the IO interface, and controls the sensor module to take a picture.
As shown in fig. 2 and 3, the image analysis module 230 includes: an MIPI deserializing module 231, a data parsing module 232, and an FIFO buffer module 233;
the sensor module 100 generates an original serial data stream and sends the original serial data stream to the MIPI deserializing module 231 for serial-parallel conversion processing, and sends the original merged parallel data to the data analyzing module 232; the data analysis module 232 performs image data extraction processing on the original merged parallel data to obtain image pixel data, and then stores the image pixel data into the FIFO buffer module 233;
as shown in fig. 4, the transmission control module includes: a frame header encapsulation module 241, an image frame counter 242, an image line counter 242, an image buffer module 243, an error monitoring module 246, and a buffer reading control module 245.
As shown in fig. 4, the frame header encapsulating module 241 reads image pixel data from the FIFO buffer module 233, and the image frame counter 242 receives configuration information from the sensor configuration module 210 and calculates a frame sequence of the received image data stream according to the configuration information; the image line counter 242 calculates a line sequence of the current image frame; the error monitoring module 246 monitors the image data stream, so as to perform frame header encapsulation processing on the image pixel data according to the image frame sequence number and the line sequence number information provided by the image frame counter 242 and the image line counter 242, and the monitoring state information provided by the error monitoring module 246, and obtain the encapsulated processed pixel data, and store the encapsulated processed pixel data in the image caching module 243;
as shown in FIG. 4, a flush instruction is provided to the image cache module 246 when an error occurs.
As shown in fig. 4, the image buffer module 246 buffers the processed pixel data after the frame header is encapsulated; the buffered read control block 246 performs read control of the buffered processing pixel data.
As shown in fig. 4, the buffer reading control module 246 reads the packaged processed pixel data from the multiple image buffer modules 246 by using a cyclic competition reading control method and sends the processed pixel data to the Cameralink sending module 300, so that the processed pixel data is sent to the high-speed multi-view camera subsystem through the Cameralink sending module 300;
as shown in fig. 6, the round robin contention read control method is performed as follows:
(1) and entering a sending waiting state after the initialization configuration of the main system is completed.
(2) Circularly judging the image cache modules, and selecting the image cache module with a high priority level to start a corresponding reading function according to the priority level transmitted by the sensor in the register configuration information after monitoring that the data access amount of the image cache modules reaches a preset threshold value;
(3) and after the image cache module with the high priority finishes reading, finishing reading the image cache modules with the low priority in sequence, immediately entering a sending waiting state after all the image cache modules meeting the threshold condition finish reading, and returning to the step 2 to start the next cycle judgment.
As shown in fig. 3, the MIPI deserializing module 231 includes: a bit alignment module and a Lane alignment module;
the bit alignment module carries out deserializing and bit synchronization processing on the received original serial data stream to obtain original parallel data; and the Lane alignment module performs data alignment and merging processing on the original parallel data in each channel to obtain original merged parallel data.
As shown in fig. 3, the data parsing module 232 includes: the frame header extraction module, the pixel extraction module and the pixel data synthesis module;
and the original combined parallel data generated by the Lane alignment module sequentially passes through the frame header extraction module to extract frame header information, the pixel extraction module extracts effective pixel information, and the pixel data synthesis module combines multi-channel pixel information to finally obtain image pixel data.
As shown in fig. 3, the frame header extraction module determines the start position of the data frame and the start position of the line pixels by determining the frame start and the line start flag characters; the pixel extraction module extracts effective image pixel data from the front-end data to obtain a pixel data stream of each channel; and the pixel data synthesis module carries out synthesis processing of multi-channel pixel data on the front-end data to finally obtain image pixel data.
As shown in fig. 5, the format of the merged pixel frame is described, and the 1 st line of the merged pixel frame is the complete 1 st line of pixels (including frame header information, image pixels, and no further description is given); merge pixel frame row 2 to the complete row 1 pixel of camera 2; the merged pixel frame row 3 is the complete row 1 pixel of camera 3; similarly, the nth row of the merged pixel frame is the complete 1 st row of pixels of camera n.
As shown in fig. 5, the n +1 th row of the merged pixel frame is the complete 2 nd row of pixels of camera 1; merging the row n +2 of the pixel frame into a complete row 2 of pixels of the camera 2; similarly, the merged pixel frame 2n row is the complete 2 nd row of pixels for camera n; merging the 3 nth row of pixels of the pixel frame into the complete 3 rd row of pixels of the camera n; the LVDS sending module 320 sends the plurality of image data to the high-speed multi-view camera subsystem according to the merged pixel frame format.
Claims (8)
1. A camera system, comprising: a high-speed multi-view camera main system and a high-speed multi-view camera subsystem;
the high-speed multi-view camera main system includes: the system comprises a sensor module, a processing and control unit and a Cameralink sending module;
the processing and control unit comprises: the device comprises a sensor configuration module, a trigger control module, an image analysis module and a transmission control module;
the image parsing module includes: the system comprises an MIPI deserializing module, a data analyzing module and an FIFO cache module;
the transmission control module includes: the device comprises a frame header packaging module, an image frame counter, an image line counter, an image caching module, an error monitoring module and a caching reading control module;
the sensor module generates an original serial data stream and sends the original serial data stream to the MIPI deserializing module for serial-parallel conversion processing, and original merged parallel data are obtained and then sent to the data analyzing module; the data analysis module carries out image data extraction processing on the original merged parallel data to obtain image pixel data and then stores the image pixel data into the FIFO cache module;
the frame header packaging module reads the image pixel data from the FIFO cache module, and performs frame header packaging processing on the image pixel data according to the image frame sequence number and the line sequence number information provided by the image frame counter and the image line counter and the monitoring state information provided by the error monitoring module to obtain packaged processing pixel data and store the packaged processing pixel data in the image cache module;
the cache reading control module reads the packaged processing pixel data from the multiple image cache modules by using a cyclic competition reading control method and sends the processing pixel data to the Cameralink sending module, so that the processing pixel data is sent to the high-speed multi-view camera subsystem through the Cameralink sending module;
the high-speed multi-view camera subsystem includes: the system comprises a Cameralink receiving module, a storage control and transmission unit, an image storage module and an image transmission module;
and the Camera link receiving module of the high-speed multi-view camera subsystem receives the processed pixel data and sends the processed pixel data to the storage control and transmission unit for unpacking and controlling storage processing, after unpacking pixel data is obtained, the unpacking pixel data is stored into different cache regions of the image storage module according to frame header information, and the image transmission module sequentially reads the unpacking pixel data from the image storage module and transmits the unpacking pixel data to the terminal equipment.
2. A camera system as claimed in claim 1, wherein: the sensor configuration module receives the control command from the Cameralink sending module and communicates with the sensor module through an I2C interface.
3. A camera system as claimed in claim 1, wherein: the trigger control module is connected with the sensor module through an IO interface and controls the sensor module to shoot.
4. A camera system as claimed in claim 1, wherein: the MIPI deserializing module comprises: a bit alignment module and a Lane alignment module;
the bit alignment module carries out deserializing and bit synchronization processing on the received original serial data stream to obtain original parallel data; and the Lane alignment module performs data alignment and merging processing on the original parallel data in each channel to obtain the original merged parallel data.
5. A camera system as claimed in claim 1, wherein: the data analysis module comprises: the frame header extraction module, the pixel extraction module and the pixel data synthesis module;
the frame header extraction module extracts frame header information of the original combined parallel data to obtain frame header information;
the pixel extraction module extracts effective pixel information of the parallel data from which the frame header information is removed to obtain a pixel data stream of each channel;
and the pixel data synthesis module is used for merging the pixel data streams of the multiple channels to finally obtain the image pixel data.
6. The camera system of claim 1, wherein the frame header extraction module determines a start position of the data frame and a start position of the line pixels by determining a frame start and a line start flag character.
7. The machine system of claim 1, wherein the round robin contention read control method is performed by:
(1) entering a sending waiting state after the initialization configuration of the main system is completed;
(2) circularly judging the image cache modules, and selecting the image cache module with a high priority level to start a corresponding reading function according to the priority level transmitted by the sensor in the register configuration information after monitoring that the data access amount of the image cache modules reaches a preset threshold value;
(3) and after the image cache module with the high priority finishes reading, finishing reading the image cache modules with the low priority in sequence, immediately entering a sending waiting state after all the image cache modules meeting the threshold condition finish reading, and returning to the step 2 to start the next cycle judgment.
8. A camera system as claimed in claim 1, wherein: the high-speed multi-view camera subsystem Cameralink receiving module is connected with the high-speed multi-view camera main system Cameralink sending module; the Cameralink receiving module and the Cameralink transmitting module both include: a signal IO interface, a serial port signal interface and an image signal LVDS interface;
the trigger control module receives a trigger level signal from the high-speed multi-view camera subsystem through the IO interface and controls the sensor module to take a picture;
the sensor configuration module receives an instruction from the high-speed multi-view camera subsystem through the serial port signal interface and communicates with the sensor module through an I2C interface;
the image signal LVDS interface is a physical channel for image transmission between the high-speed multi-view camera main system and the subsystem.
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| CN202011531986.7A CN112689072A (en) | 2020-12-23 | 2020-12-23 | Camera system |
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| CN202011531986.7A CN112689072A (en) | 2020-12-23 | 2020-12-23 | Camera system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113315935A (en) * | 2021-05-20 | 2021-08-27 | 中国科学院光电技术研究所 | CMOS image sensor data acquisition device and method based on FPGA |
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| CN102859987A (en) * | 2010-04-05 | 2013-01-02 | 高通股份有限公司 | Combining data from multiple image sensors |
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