CN203722715U - Multi-window image data high-speed scanning and acquisition device of grating scale - Google Patents

Abstract

The utility model provides a multi-window image data high-speed scanning and acquisition device of an image sensor. The device comprises a CMOS image sensor, a field-programmable gate array (FPGA), and a static random access memory (SRAM), wherein a signal input terminal of the FPGA is connected to a signal output terminal of the CMOS image sensor, a signal output terminal of the FPGA is connected to a signal input terminal of the SRAM, and a signal output terminal of the SRAM is connected to an SRAM interface of a DSP. The device uses the FPGA for high-speed image data acquisition, so that when the image sensor moves at a very high speed, grating codes can still be captured clearly, and thus the difficulty of later image processing is substantially lowered. The device is aimed at multi-window image sensor driving of an absolute grating scale. Through reduction of useless pixels, capturing speed is raised. Through placement of windows, pixels are reduced so as to obtain a greater effective length.

Description

A kind of high-velocity scanning of many windows view data and harvester of grating scale

Technical field

The utility model relates to the optical grating ruler measurement field of processing based on image, relates in particular to the view data high-velocity scanning of many windows of imageing sensor and harvester, belongs to the innovative technology of the view data high-velocity scanning of many windows of imageing sensor and harvester.

Background technology

At present, the principle of grating scale is substantially all that Moire fringe based on grating scale is interfered or diffraction produces is measured.This method for designing is developed so far, although quite ripe, but still there are many deficiencies, such as principle is more numerous and diverse, the design comparison of circuit is complicated, requires also higher.

Under this background, the grating scale of processing based on image arises at the historic moment.And the grating scale of processing based on image in the market can not be accomplished in the situation that translational speed is very fast, guarantee the real-time of measuring.Reason is that the grasp speed of image is fast not, and the crawl of whole spoke picture causes a large amount of pixel exposures and the waste in transmission time.

Summary of the invention

The purpose of this utility model is to provide a kind of many windows of imageing sensor view data high-velocity scanning and harvester.The utility model, in the very fast situation of imageing sensor translational speed, can photograph grating encoding clearly, and the difficulty of the image processing in later stage is reduced greatly.

The technical solution of the utility model is: the utility model is the high-velocity scanning of many windows view data and the harvester of grating scale, include cmos image sensor, on-site programmable gate array FPGA and static RAM SRAM, wherein the signal input part of on-site programmable gate array FPGA and the signal output part of cmos image sensor are connected, the signal output part of on-site programmable gate array FPGA is connected with the signal input part of static RAM SRAM, and the signal output part of static RAM SRAM is connected to the SRAM interface of DSP.

Above-mentioned on-site programmable gate array FPGA includes image data acquiring module, imageing sensor register configuration module, static RAM SRAM control module.

Compared with prior art, tool has the following advantages the utility model:

1) the utility model high-velocity scanning and acquisition method comprise the many windows drivings to imageing sensor for absolute grating scale; By reducing the method that improves shooting speed without effect pixel; Placement by the window's position obtains longer effective length with pixel still less; By using the method for on-site programmable gate array FPGA high speed acquisition view data.

2) the utility model to many windows of imageing sensor drive be by on-site programmable gate array FPGA drives imageing sensor and to the configuration of register, make it to open a plurality of windows shooting grating encodings.

3) the utility model is by reducing the method that improves shooting speed without effect pixel, to drive and realize by described many windows, by reducing, in image is processed, act on little pixel to reach higher frame speed, accomplish that real-time is higher in the measuring process of grating scale.

4) placement of the utility model by the window's position obtains longer effective length with pixel still less, to drive based on described multiwindow, method by the scanning of oblique scanning or parabola replaces linear scanning, accomplishes to obtain better image processing effect with pixel still less.

5) the utility model is by being used the method for on-site programmable gate array FPGA high speed acquisition view data, be by using on-site programmable gate array FPGA to build an Acquisition Circuit according to the data output timing of imageing sensor, can accomplish not leak the data that data and reliability better collect the grating encoding that imageing sensor spreads out of.

The utility model can rise to very fast by the speed of the speed of exposure one frame picture and collection one frame picture.The utility model is not only applicable to grating scale, and the utility model architectural configurations is flexible, is applicable to modularized design, thereby reduces the construction cycle of product.In addition, the utility model construction cycle is short, is particularly suitable for high speed real time image processing system.

Accompanying drawing explanation

Fig. 1 is many windows view data high-velocity scanning of grating scale and the schematic diagram of harvester;

Fig. 2 is FPGA internal module schematic diagram;

Fig. 3 is many windows view data high-velocity scanning of grating scale and the flow chart of acquisition method;

Fig. 4 is the many windows schematic diagram in grating encoding;

Fig. 5 tiltedly scans schematic diagram.

Embodiment

The utility model is the high-velocity scanning of many windows view data and the harvester of grating scale, include cmos image sensor, on-site programmable gate array FPGA and static RAM SRAM, wherein the signal input part of on-site programmable gate array FPGA and the signal output part of cmos image sensor are connected, the signal output part of on-site programmable gate array FPGA is connected with the signal input part of static RAM SRAM, and the signal output part of static RAM SRAM is connected to the SRAM interface of DSP.

Above-mentioned on-site programmable gate array FPGA includes image data acquiring module, imageing sensor register configuration module, static RAM SRAM control module, and wherein the relation of image data acquiring module, imageing sensor register configuration module, these three modules of static RAM SRAM control module is relations of time order and function.First use imageing sensor register configuration block configuration imageing sensor, make it to carry out work according to our requirement, then use image data acquiring module to gather the picture signal that imageing sensor is captured, finally use static RAM SRAM control module that the picture signal collecting is deposited in SRAM, so that post-processed.

Many windows view data high-velocity scanning of the utility model grating scale and the method for collection, include following steps:

1) use SCCB agreement that imageing sensor is configured to the operating state that many windows and window are lined up oblique line.

2) according to the view data output protocol of imageing sensor, gather the view data of imageing sensor output.

3) according to the input and output agreement of SRAM, the view data collecting is write in SRAM and stored, then read and be transferred to DSP to make post-processed from it.

The high speed acquisition of grating encoding and the specific implementation method of high-speed transfer are as follows:

First need the register of imageing sensor to be configured, just must be first according to the communication protocol of imageing sensor manufacturers design and configure its register.Use on-site programmable gate array FPGA to build the circuit that can communicate by letter with imageing sensor, its register is configured.

To the speed of its configuration and do not require that very fast, common MCU can accomplish, but because the collection of high speed image data will be gathered by on-site programmable gate array FPGA, so its configuration is also completed by on-site programmable gate array FPGA.

?in programmable gate array FPGA, write at the scene a static RAM SRAM controller, memory address and storage data are outputed in the address pin and data pin of static RAM SRAM, will write after enable signal WE drags down a period of time and draw high again and data can be write in static RAM SRAM.

When often collecting a view data, start static RAM SRAM write signal by the data that collect write with static RAM SRAM in store so that on-site programmable gate array FPGA is done the preliminary treatment of image and the transfer of data in later stage and image is processed.

The schematic diagram of the grating scale that after Fig. 4 tiltedly windows, camera photographs, has opened altogether 7 windows in figure, the area of each window is identical, and the grating length that can detect is like this starting to the end of the 7th window of the 1st window.In figure, black part is divided into imageing sensor except the part of window with external shield, and imageing sensor does not gather the part of image.Collection capacity and the transmission quantity of data have been reduced thus.

Fig. 5 tiltedly scans schematic diagram, the right-angle side that in figure, a and b are right-angled triangle, c is the hypotenuse of this right-angled triangle, c>a, c>b, by a, b is considered as two length of sides of the rectangle that imageing sensor can take, while window being arranged in to oblique line as figure tetra-, the effective length that can be used as image processing will be greater than direct use horizontal line scanning.

The utility model is compared with other prior aries, and its advantage is:

The utility model can rise to very fast by the speed of the speed of exposure one frame picture and collection one frame picture.The utility model is for grating scale, but is not only applicable to grating scale.The utility model architectural configurations is flexible, is applicable to modularized design, thereby reduces the construction cycle of product.And the construction cycle of itself is short, be particularly suitable for high speed real time image processing system.

For above explanation, principal character and advantage of the present utility model; the personnel of relevant every trade will be appreciated that; the utility model is not restricted to the described embodiments; the description of specification and enforcement just illustrates principle of the present utility model; do not departing under the prerequisite of utility model spirit and scope; the utility model also has various variations and upgrading, and these variations and upgrading all fall within the scope of claimed the utility model.The claimed scope of the utility model is defined by appending claims and equivalent thereof.

Claims (2)

1. the high-velocity scanning of many windows view data and the harvester of a grating scale, it is characterized in that including cmos image sensor, on-site programmable gate array FPGA and static RAM SRAM, wherein the signal input part of on-site programmable gate array FPGA and the signal output part of cmos image sensor are connected, the signal output part of on-site programmable gate array FPGA is connected with the signal input part of static RAM SRAM, and the signal output part of static RAM SRAM is connected to the SRAM interface of DSP.

2. the high-velocity scanning of many windows of grating scale according to claim 1 view data and harvester, is characterized in that above-mentioned on-site programmable gate array FPGA includes image data acquiring module, imageing sensor register configuration module, static RAM SRAM control module.