CN103646906B - 无引线球脚表贴式厚膜混合集成电路的集成方法 - Google Patents

无引线球脚表贴式厚膜混合集成电路的集成方法 Download PDF

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CN103646906B
CN103646906B CN201310706157.1A CN201310706157A CN103646906B CN 103646906 B CN103646906 B CN 103646906B CN 201310706157 A CN201310706157 A CN 201310706157A CN 103646906 B CN103646906 B CN 103646906B
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杨成刚
黄晓山
苏贵东
赵晓辉
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Guizhou Zhenhua Fengguang Semiconductor Co.,Ltd.
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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Abstract

本发明公开了无引线球脚表贴式厚膜混合集成电路集成方法，该方法是采用在陶瓷基片上，直接将厚膜混合集成电路对外连接端制作在陶瓷基片的底面，对外连接端为金属球面形；在陶瓷基片的正面进行混合集成，对厚膜导带、厚膜阻带、厚膜电容、厚膜电感采用绝缘介质厚膜进行密封、绝缘保护，对半导体裸芯片采用绝缘介质浆料进行涂封和固化保护。本方法特点有：①体积大幅缩小；②减小高频干扰；③减小正面导带长度，提升频率特性和集成度；④缩小装备体积，提升装备的高频性能；⑤提高装备系统的可靠性。本方法生产的集成电路广泛应用于航天、航空、船舶、电子、通讯、医疗设备、工业控制等领域，特别适用于装备系统小型化、高频、高可靠的领域。

Description

无引线球脚表贴式厚膜混合集成电路的集成方法
技术领域
本发明涉及集成电路，进一步来说，涉及厚膜混合集成电路，尤其涉及表贴式厚膜混合集成电路。
背景技术
原有混合电路的集成技术中，在陶瓷基片上，将半导体芯片、片式元器件直接装贴在厚膜基片上，再采用键合丝(金丝或硅铝丝)进行芯片与基片的引线键合，基片和管脚的引线键合，完成整个电器连接，最后在特定的气氛中将管基和管帽进行密封而成。原有混合电路的集成技术存在的主要问题是必须采用管基和管帽对内部电路进行封装，由于管基和管帽体积大、管脚长、连接管脚的内引线多、而且较长，因此，封装后厚膜混合集成电路的体积较大、高频干扰大，在装备小型化、高频等应用领域受到一定的限制。
经检索，中国专利数据库中涉及厚膜混合集成电路的申请件有11件，基本上是近年申请的，如200910102792.2号《高可靠厚膜混合集成电路键合系统及其制造方法》、201110446104.1号《高集成高可靠工作温度可控厚膜混合集成电路的集成方法》、201210396194.2号《高灵敏温控厚膜混合集成电路的集成方法》、201210496732.5号《高密度厚膜混合集成电路的集成方法》等。目前还没有无引线球脚表贴式厚膜混合集成电路的申请件。
发明内容
本发明的目的就是提供一种无引线球脚表贴式厚膜混合集成电路集成方法，通过取消封装外壳(含管基、管帽)、取消管脚及其内引线，从而解决原有混合电路的集成技术存在的问题。
为达到上述发明目的，发明人提供的无引线球脚表贴式厚膜混合集成电路集成方法与原有厚膜混合集成电路不同的是：它不需要管基、管脚和连接管脚的引线，而是采用在陶瓷基片上，直接将厚膜混合集成电路对外连接端制作在陶瓷基片的底面，对外连接端为金属球面形；在陶瓷基片的正面进行混合集成，对厚膜导带、厚膜阻带、厚膜电容、厚膜电感采用绝缘介质厚膜进行密封、绝缘保护，对半导体裸芯片采用绝缘介质浆料进行涂封和固化保护；具体做法是取消原有集成方法的封帽工序，增加如下工序：
(1)在厚膜导带印刷前增加基片通孔打孔工序；
(2)在进行导带印刷的同时，进行通孔金属浆料填充；
(3)阻带修调完毕后，进行绝缘介质浆料印刷，采用三氧化二铝陶瓷浆料，烧结形成介质膜；
(4)在介质膜烧结完毕后，采用高压金丝打火或印刷金浆料再回流的方法形成金焊接球；
(5)在已组装和键合后的半导体裸芯片区域涂封绝缘介质浆料，采用低温固化玻璃浆料进行涂封。
上述基片通孔的孔径精确控制在0.1μm以内。
上述烧结成膜的工艺条件是：温度为650℃、烧结时间60min，在氮气保护环境中进行烧结。
上述低温固化的工艺条件是：温度为400℃、45min，在氮气保护环境中完成固化涂封。
本发明的集成方法集成的无引线球脚表贴式厚膜混合集成电路有以下特点：①无封装外壳，体积大幅缩小；②无引脚及相应的内引线，减小相应的高频干扰；③采用底部球形引脚，减小正面导带长度，可提升频率特性和集成度；④实现表贴式安装，缩小装备体积，提升装备的高频性能；⑤提高装备系统的可靠性。
本发明方法生产的集成电路广泛应用于航天、航空、船舶、电子、通讯、医疗设备、工业控制等领域，特别适用于装备系统小型化、高频、高可靠的领域，具有广阔的市场前景和应用空间。
附图说明
图1为本发明方法生产的集成电路示意图，图2为陶瓷基片通孔示意图，图3为厚膜导带、通孔填充示意图，图4为厚膜阻带示意图，图5为厚膜绝缘介质保护层示意图，图6为球型焊接区示意图，图7为组装与键合示意图，图8为绝缘介质浆料涂封示意图，图9为原有工艺流程框图，图10为本发明方法的工艺流程框图。
其中图2至图8为实施本发明方法的具体工序示意图。
上述各图中，1为陶瓷基片，2通孔，3为导带/键合区，4为阻带，5为绝缘介质保护层，6为引出端焊接球面，7为球形焊接区，8为片式元器件，9为半导体裸芯片，10为键合丝，11为封装芯片，12为绝缘介质涂封层，13为金属通孔。
具体实施方式
实施例：本发明方法的工艺流程如图10所示，包括以下工序：
(1)陶瓷基片、金浆料、钌系电阻浆料的准备；
(2)基片清洗与烘干、管壳清洗与烘干；
(3)基片通孔打孔；
(4)厚膜导带浆料的印刷，并在150℃下烘干10min；
(5)通孔填充金属浆料；
(6)电阻浆料的印刷，并在150℃下烘干10min；
(7)在850℃下成膜烧结10min，总时间35min；
(8)激光调整电阻；
(9)参数及功能测试；
(10)绝缘介质浆料印刷，采用三氧化二铝陶瓷浆料，烧结成膜；
(11)用高压金丝打火或印刷金浆料再回流的方法形成金焊接球；
(12)划片分离；
(13)将厚膜基片组装到管基的底座上；
(14)组装半导体芯片和片式元器件；
(15)用硅-铝丝或金丝键合以完成半导体芯片的电路连接、基片与管脚的电路连接；
(16)在已组装和键合后的半导体裸芯片区域涂封绝缘介质浆料，采用低温固化玻璃浆料进行涂封。
(17)性能测试；
(18)老化筛选测试、密封性检查；
(19)产品编号打印、包装入库。
采用本发明方法，通过取消封装外壳(含管基、管帽)、取消管脚及连接管脚的内引线，解决了原有混合电路的集成技术存在的封装后厚膜混合集成电路的体积较大、高频干扰大等问题，实现了在装备小型化、高频等领域的应用。

Claims (4)

1.无引线球脚表贴式厚膜混合集成电路集成方法，其基本工艺是常规的厚膜混合集成电路制作工艺，其特征在于：采用在陶瓷基片上，直接将厚膜混合集成电路对外连接端制作在陶瓷基片的底面，对外连接端为金属球面形；在陶瓷基片的正面进行混合集成，对厚膜导带、厚膜阻带、厚膜电容、厚膜电感采用绝缘介质厚膜进行密封、绝缘保护，对半导体裸芯片采用绝缘介质浆料进行涂封和固化保护；具体做法是取消原有集成方法的封帽工序，增加如下工序：
⑴在厚膜导带印刷前增加基片通孔打孔工序；
⑵在进行导带印刷的同时，进行通孔金属浆料填充；
⑶阻带修调完毕后，进行绝缘介质浆料印刷，采用三氧化二铝陶瓷浆料，烧结形成介质膜；
⑷在介质膜烧结完毕后，采用高压金丝打火或印刷金浆料再回流的方法形成金焊接球；
⑸在已组装和键合后的半导体裸芯片区域涂封绝缘介质浆料，采用低温固化玻璃浆料进行涂封。
2.如权利要求1所述的集成方法，其特征在于所述基片通孔打孔的孔径精度控制在0.1μm以内。
3.如权利要求1所述的集成方法，其特征在于所述烧结形成介质膜的工艺条件是：温度为650℃、烧结时间60min，在氮气保护环境中进行烧结。
4.如权利要求1所述的集成方法，其特征在于所述低温固化的工艺条件是：温度为400℃、45min，在氮气保护环境中完成固化涂封。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201498510U (zh) * 2009-09-22 2010-06-02 贵州振华风光半导体有限公司 高可靠厚膜混合集成电路键合系统
CN103280424A (zh) * 2012-12-12 2013-09-04 贵州振华风光半导体有限公司 一种高集成度功率厚膜混合集成电路的集成方法

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CN201498510U (zh) * 2009-09-22 2010-06-02 贵州振华风光半导体有限公司 高可靠厚膜混合集成电路键合系统
CN103280424A (zh) * 2012-12-12 2013-09-04 贵州振华风光半导体有限公司 一种高集成度功率厚膜混合集成电路的集成方法

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