CN204289431U - 无引线球脚表贴式微波薄膜混合集成电路 - Google Patents

无引线球脚表贴式微波薄膜混合集成电路 Download PDF

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CN204289431U
CN204289431U CN201420794469.2U CN201420794469U CN204289431U CN 204289431 U CN204289431 U CN 204289431U CN 201420794469 U CN201420794469 U CN 201420794469U CN 204289431 U CN204289431 U CN 204289431U
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film
thin
ceramics substrate
integrated circuit
ball pin
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杨成刚
黄晓山
刘学林
卢生贵
赵晓辉
徐勇
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Guizhou Zhenhua Fengguang Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

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  • Wire Bonding (AREA)

Abstract

无引线球脚表贴式微波薄膜混合集成电路，由薄膜陶瓷基片、薄膜导带、薄膜阻带、薄膜电容、薄膜电感、片式元器件、半导体裸芯片和管帽组成；薄膜陶瓷基片正面与底面之间有通孔；薄膜导带、薄膜阻带、薄膜电容、薄膜电感集成在薄膜陶瓷基片的正面，底面有绝缘介质薄膜；薄膜陶瓷基片底面为球脚型对外连接端；管帽装贴在薄膜陶瓷基片的正面；半导体芯片包括正装型半导体裸芯片和倒装型半导体裸芯片，前者有键合丝与薄膜阻带连接,后者的球脚与金属球球脚焊接；管帽外层为金属层，内壁为陶瓷涂覆层。使用本实用新型的器件广泛应用于航天、航空、船舶、电子、通讯、医疗设备、工业控制等领域，特别适用于装备系统小型化的领域。

Description

无引线球脚表贴式微波薄膜混合集成电路
技术领域
本实用新型涉及混合集成电路，具体来说，涉及薄膜混合集成电路，更进一步来说，涉及无引线球脚表贴式微波薄膜混合集成电路。
背景技术
原有薄膜混合电路的集成技术是先将薄膜陶瓷基片装贴在管基上，接着将半导体芯片、片式元器件直接装贴在薄膜基片上，再采用键合丝（金丝或硅铝丝）进行芯片与基片的引线键合，基片和管脚的引线键合，完成整个电器连接，最后在高真空、高纯氮气或高纯氩气等特定的气氛中将管基和管帽进行密封而成。这种集成电路存在以下问题：必须采用管基和管帽对内部电路进行封装，由于管基和管帽的体积大、管脚长、连接管脚的内引线多、而且较长，因此，封装后薄膜混合集成电路的体积较大、高频干扰大，在装备小型化、高频等应用领域受到一定的限制。
中国专利数据库中涉及的薄膜混合集成电路专利申请件有9件，例如2012104928157号《高密度薄膜混合集成电路的集成方法》、2012105373324号《三维集成功率薄膜混合集成电路的集成方法》、2012103962589号《高灵敏温控薄膜混合集成电路的集成方法》、2011205566949号《高集成高可靠工作温度可控薄膜混合集成电路》等。然而迄今为止，尚无球脚表贴式微波薄膜混合集成电路的申请件。
发明内容
本实用新型旨在提供无引线球脚表贴式微波薄膜混合集成电路，克服原有技术难以实现装备小型化、高频等应用领域受到限制的缺陷。
设计人针对原有的薄膜混合集成电路存在的问题，取消了薄膜混合集成电路原有的封装管基、管脚及其内引线，提供的无引线球脚表贴式微波薄膜混合集成电路由薄膜陶瓷基片、薄膜导带、薄膜阻带、薄膜电容、薄膜电感、片式元器件、半导体裸芯片和管帽组成；薄膜导带、薄膜阻带、薄膜电容、薄膜电感集成在薄膜陶瓷基片正面，在薄膜陶瓷基片底面有绝缘介质薄膜；对外连接端制作在薄膜陶瓷基片底面；管帽封焊在薄膜陶瓷基片的正面，管帽外层为金属，内层为陶瓷层。
上述管帽封焊在薄膜陶瓷基片的管帽封焊区以固定并密封。
上述对外连接端为金属球脚型引出端。
上述半导体裸芯片包括正装型和倒装型，正装型半导体裸芯片有键合丝与薄膜陶瓷基片正面的键合区电气连接, 倒装型半导体裸芯片有球脚与薄膜陶瓷基片正面球形焊接区的球脚球焊连接。
上述薄膜陶瓷基片正面与底面之间有金属化通孔。
无引线球脚表贴式微波薄膜混合集成电路使用时以贴片式使用，该集成电路具有以下优点：①管基与薄膜陶瓷基片一体化，无封装外壳管基，体积大幅缩小；②无引脚及相应的内引线，减小相应的高频干扰；③用金属球型引出端焊接面代替原有管基中的有引线引脚，可实现高密度引脚；④可实现多层布线与集成，实现高密度集成；⑤可集成更多的电路功能，实现系统集成；⑥   实现表贴式安装，缩小装备体积，提升装备的高频性能；⑦内涂陶瓷层金属管帽除保护封装内部电路外，同时起到电磁屏蔽和封装内部和外部的高频绝缘作用，确保微波混合集成电路的可靠使用；⑧提高装备系统的可靠性。
本实用新型解决了原有的微波薄膜混合集成电路在装备小型化、高频等应用领域受到限制的难题，使用本实用新型的器件广泛应用于航天、航空、船舶、电子、通讯、医疗设备、工业控制等领域，特别适用于装备系统小型化、高频、高可靠的领域，具有广阔的市场前景和应用空间。
附图说明
图1为无引线球脚表贴式微波薄膜混合集成电路结构示意图。
图中，1为薄膜陶瓷基片，2为陶瓷涂覆层，3为金属层，4为片式元器件，5为薄膜阻带，6为导带/键合区，7为正装型半导体芯片，8为键合丝，9为倒装型半导体芯片，10为封焊层，11为球脚焊接区，12为绝缘介质保护层，13为金属化通孔，14为管帽封焊区，15为引出端焊接球，16为金属球。
具体实施方式
实施例   结构如图1的无引线球脚表贴式微波薄膜混合集成电路，由薄膜陶瓷基片1、薄膜导带、薄膜阻带5、薄膜电容、薄膜电感、片式元器件4、半导体裸芯片和管帽组成；薄膜陶瓷基片1正面与底面之间有金属化通孔13；薄膜导带、薄膜阻带5、薄膜电容、薄膜电感集成在薄膜陶瓷基片1正面，薄膜陶瓷基片底面有绝缘介质薄膜；薄膜陶瓷基片1底面为球脚型对外连接端；管帽装贴在薄膜陶瓷基片1的正面；半导体芯片包括正装型半导体裸芯片7和倒装型半导体裸芯片9，前者有键合丝8与薄膜阻带5连接,后者有球脚与薄膜导带/键合区6焊接；管帽外层为金属层3，管帽内壁有陶瓷涂覆层2。管帽封焊在薄膜陶瓷基片1的管帽封焊区14以固定并密封。对外连接端包括绝缘介质保护层12和引出端焊接球15。

Claims (5)

1.无引线球脚表贴式微波薄膜混合集成电路，其特征在于该集成电路由薄膜陶瓷基片(1)、薄膜导带、薄膜阻带(5)、薄膜电容、薄膜电感、片式元器件(4)、半导体裸芯片和管帽组成，薄膜导带、薄膜阻带(5)、薄膜电容、薄膜电感集成在薄膜陶瓷基片(1)的正面，在薄膜陶瓷基片(1)底面有绝缘介质薄膜；球脚型对外连接端制作在薄膜陶瓷基片(1)底面；管帽封焊在薄膜陶瓷基片(1)正面，管帽外层为金属(3)，内层为陶瓷层(2)。
2. 如权利要求1所述的无引线球脚表贴式微波薄膜混合集成电路，其特征在于所述管帽封焊在薄膜陶瓷基片(1)的管帽封焊区(14)以固定并密封，形成封焊层(10)。
3.  如权利要求1所述的无引线球脚表贴式微波薄膜混合集成电路，其特征在于所述对外连接端为金属球脚型引出端(15)。
4.  如权利要求1所述的无引线球脚表贴式微波薄膜混合集成电路，其特征在于所述半导体裸芯片包括正装型半导体裸芯片(7)和倒装型半导体裸芯片(9)，前者有键合丝(8)与薄膜陶瓷基片正面的导带/键合区(6)以电气连接, 后者的球脚与薄膜陶瓷基片正面的球形焊接区上的金属球(16)球脚用球焊连接。
5.  如权利要求1所述的无引线球脚表贴式微波薄膜混合集成电路，其特征在于所述薄膜陶瓷基片(1)的正面与底面之间有金属化通孔(13)。
CN201420794469.2U 2014-12-15 2014-12-15 无引线球脚表贴式微波薄膜混合集成电路 Expired - Fee Related CN204289431U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114364125A (zh) * 2021-12-31 2022-04-15 中国电子科技集团公司第十四研究所 一种双面布置器件的厚膜混合集成电路及其生产方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114364125A (zh) * 2021-12-31 2022-04-15 中国电子科技集团公司第十四研究所 一种双面布置器件的厚膜混合集成电路及其生产方法

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