CN205488120U - 一种抗干扰薄膜混合集成电路 - Google Patents

一种抗干扰薄膜混合集成电路 Download PDF

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CN205488120U
CN205488120U CN201520992983.1U CN201520992983U CN205488120U CN 205488120 U CN205488120 U CN 205488120U CN 201520992983 U CN201520992983 U CN 201520992983U CN 205488120 U CN205488120 U CN 205488120U
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integrated circuit
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杨成刚
黄晓山
苏贵东
赵晓辉
杨晓琴
聂平健
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Guizhou Zhenhua Fengguang Semiconductor Co.,Ltd.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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Abstract

抗干扰薄膜混合集成电路，由管帽、管基、管脚、半导体集成电路芯片组成，半导体集成电路芯片用键合丝键合在管基薄膜陶瓷基片金属键合区上，管帽封装在管基之上；与原有薄膜混合集成电路不同的是：管帽有金属外层和陶瓷内层，管基有陶瓷基体,管基外表面有金属外层；另有片式元器件装贴在薄膜陶瓷基片上。这样，管基和管帽将陶瓷材料和金属材料二者有机结合，实现从低频到高频的电磁屏蔽，使封装内外电磁环境达到良好的隔离，从而实现薄膜混合集成电路的抗干扰能力。用本方法生产的器件广泛应用于航天、航空、船舶、电子、通讯、医疗设备、工业控制等领域，特别适用于装备系统小型化、高频、高可靠的领域。

Description

一种抗干扰薄膜混合集成电路
技术领域
本实用新型涉及混合集成电路，具体来说，涉及薄膜混合集成电路，更进一步来说，涉及抗干扰薄膜混合集成电路。
背景技术
原有薄膜混合集成电路的集成技术中，先将薄膜陶瓷基片装贴在金属管基上，再将半导体芯片、片式元器件直接装贴在薄膜基片上，再采用键合丝(金丝或硅铝丝)进行芯片与基片的引线键合，基片和管脚的引线键合，完成整个电器连接，最后在高真空、高纯氮气或高纯氩气等特定的气氛中将金属管基和金属管帽(或陶瓷管基和陶瓷管帽)进行密封而成。此方法存在的主要问题是在高频或电磁干扰的环境中，金属能有效地屏蔽低频、中频和部分高频干扰的影响，当频率继续增高时，金属的屏蔽作用就会变差。相反，陶瓷对低频、中频没有屏蔽能力，但对高频有良好的屏蔽能力。因此，采用金属封装、陶瓷封装均不能满足从低频、中频到高频全频段的屏蔽要求。导致薄膜混合集成电路在要求抗干扰的环境中使用时，需要在使用系统中增加大量的屏蔽措施，给使用造成诸多不便，不利于装备系统的小型化、集成化和轻便化。
中国专利数据库中，涉及薄膜混合集成电路的专利以及专利申请件有十余件，如2011104457489号《高集成高可靠工作温度可控薄膜混合集成电路的集成方法》、ZL2012103962589号《高灵敏温控薄膜混合集成电路的集成方法》、ZL2012104928157号《高密度薄膜混合集成电路的集成方法》、ZL2012105350271号《一种高集成度功率薄膜混合集成电路的集成方法》、2012105373324号《三维集成功率薄膜混合集成电路的集成方法》、 2012105941093号《一种薄膜混合集成电路电镀方法》、2014107757385号《无引线球脚表贴式微波薄膜混合集成电路及其集成方法》等。迄今为止，尚无抗干扰薄膜混合集成电路的专利申请件。
发明内容
本实用新型旨在提供一种抗干扰薄膜混合集成电路，实现从低频到高频的电磁屏蔽，增加抗干扰能力；从而有利于装备系统的小型化、集成化和轻便化。
设计人提供的抗干扰薄膜混合集成电路由管帽、管基、管脚、半导体集成电路芯片、片式元器件组成，半导体集成电路芯片装贴在薄膜陶瓷基片上，并用金属键合丝将半导体集成电路芯片表面的键合区与薄膜陶瓷基片相应的金属键合区进行键合连接，管帽封装在管基之上；与原有薄膜混合集成电路不同的是：管帽和管基有金属外层和内层陶瓷基体；另有片式元器件装贴在薄膜陶瓷基片上。
上述管帽金属层和管基金属层的金属是铬和金。
抗干扰薄膜混合集成电路的集成方法是：在预先烧结成型的陶瓷管基、陶瓷管帽的外表面，采用涂覆金属浆料烧结或化学电镀的方式生长所需金属层，再进行半导体集成电路芯片的装贴、引线键合和封帽。
本实用新型具有以下优点：①从低频到高频的电磁屏蔽，使封装内外电磁环境达到良好的隔离，提升集成电路的抗干扰能力；②有利于装备系统的小型化、集成化和轻便化；③提高装备系统可靠性。
本实用新型的器件广泛应用于航天、航空、船舶、电子、通讯、医疗设备、工业控制等领域，特别适用于装备系统小型化、高频、高可靠的领域，具有广阔的市场前景和应用空间。
附图说明
图1为原有薄膜混合集成电路组装示意图，图2为本发明的抗干扰薄膜混合集成电路组装示意图。
图中，1为金属管基，2为金属底座，3为金属管脚，4为金属管帽，5为半导体集成电路芯片，6为键合丝，7为薄膜电阻，8为薄膜导带/键合区，9为薄膜陶瓷基片背面金属层，10为薄膜陶瓷基片，11为管帽陶瓷基体，12为管帽外表面金属外层，13为管基陶瓷基体，14为管基外表面金属外层，15为片式元器件。
具体实施方式
实施例：如图2的抗干扰薄膜混合集成电路，由管帽、管基、管脚、半导体集成电路芯片5、片式元器件15组成，半导体集成电路芯片5用键合丝6键合在管基薄膜陶瓷基片金属键合区8上，管帽封装在管基之上；管帽有陶瓷内层11和管帽外表面金属外层12，管基有陶瓷基体13,管基外表面金属外层14；薄膜陶瓷基片通过背面金属层9装贴在管基上；另有片式元器件装贴在薄膜陶瓷基片上。
管帽外表面金属外层12和管基外表面金属外层14的金属层结构是铬和金。

Claims (2)

1.一种抗干扰薄膜混合集成电路，由管帽、管基、管脚、半导体集成电路芯片(5)、片式元器件(15)组成，半导体集成电路芯片(5)用键合丝(6)键合在管基上面的薄膜陶瓷基片金属键合区(8)上，管帽封装在管基之上；其特征在于管帽有陶瓷内层(11)和管帽外表面金属外层(12)，管基有陶瓷基体(13),管帽外表面金属外层(14)；薄膜陶瓷基片通过背面金属层(9)装贴在管基上；另有片式元器件装贴在薄膜陶瓷基片上。
2.如权利要求1所述的抗干扰薄膜混合集成电路，其特征在于所述管帽外表面金属外层(12)和管基外表面金属外层(14)的金属层结构是铬和金。
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