CN105405803A - 抗干扰厚膜混合集成电路的集成方法 - Google Patents

抗干扰厚膜混合集成电路的集成方法 Download PDF

Info

Publication number
CN105405803A
CN105405803A CN201510882055.4A CN201510882055A CN105405803A CN 105405803 A CN105405803 A CN 105405803A CN 201510882055 A CN201510882055 A CN 201510882055A CN 105405803 A CN105405803 A CN 105405803A
Authority
CN
China
Prior art keywords
integrated circuit
pipe cap
ceramic
metal
thick film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510882055.4A
Other languages
English (en)
Inventor
杨成刚
苏贵东
赵晓辉
黄晓山
刘学林
路兰艳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guizhou Zhenhua Fengguang Semiconductor Co Ltd
Original Assignee
Guizhou Zhenhua Fengguang Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guizhou Zhenhua Fengguang Semiconductor Co Ltd filed Critical Guizhou Zhenhua Fengguang Semiconductor Co Ltd
Priority to CN201510882055.4A priority Critical patent/CN105405803A/zh
Publication of CN105405803A publication Critical patent/CN105405803A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/705—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thick-film circuits or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

抗干扰厚膜混合集成电路的集成方法，是将金属与陶瓷的复合材料用作管基和管帽外层的材料，以满足从低频、中频到高频全频段的屏蔽要求，具体的集成方法是：在预先烧结成型的陶瓷管基、陶瓷管帽的外表面，采用涂覆金属浆料烧结或化学电镀的方式生长所需金属层，再进行半导体集成电路芯片和片式元器件的装贴、引线键合和封帽；这样，管基和管帽用陶瓷材料和金属材料二者有机结合，即实现从低频到高频的电磁屏蔽，使封装内外电磁环境达到良好的隔离，从而实现提高厚膜混合集成电路抗干扰能力的目的。用本方法生产的器件广泛应用于航天、航空、船舶、电子、通讯、医疗设备、工业控制等领域，特别适用于装备系统小型化、高频、高可靠的领域。

Description

抗干扰厚膜混合集成电路的集成方法
技术领域
本发明涉及集成电路，具体来说，涉及厚膜混合集成电路，更进一步来说，涉及抗干扰厚膜混合集成电路。
技术背景
原有厚膜混合集成电路的集成技术中，先将厚膜陶瓷基片装贴在金属管基上，再将半导体芯片、片式元器件直接装贴在厚膜基片上，再采用键合丝（金丝或硅铝丝）进行芯片与基片的引线键合，基片和管脚的引线键合，完成整个电器连接，最后在高真空、高纯氮气或高纯氩气等特定的气氛中将金属管基和金属管帽（或陶瓷管基和陶瓷管帽）进行密封而成。此方法存在的主要问题是在高频或电磁干扰的环境中，金属能有效地屏蔽低频、中频和部分高频干扰的影响，当频率继续增高时，金属的屏蔽作用就会变差。相反，陶瓷对低频、中频没有屏蔽能力，但对高频有良好的屏蔽能力。因此，采用金属封装、陶瓷封装均不能满足从低频、中频到高频全频段的屏蔽要求。导致厚膜混合集成电路在要求抗干扰的环境中使用时，需要在使用系统中增加大量的屏蔽措施，给使用造成诸多不便，不利于装备系统的小型化、集成化和轻便化。
中国专利数据库中，涉及厚膜混合集成电路的专利以及专利申请件有十余件，如2011104461041号《高集成高可靠工作温度可控厚膜混合集成电路的集成方法》、2012105301453号《一种用于厚膜混合集成电路的成膜工艺》、ZL2012103961942号《高灵敏温控厚膜混合集成电路的集成方法》、ZL2012105353566号《三维集成功率厚膜混合集成电路的集成方法》、ZL201210535366X号《一种高集成度功率厚膜混合集成电路的集成方法》、2012105373165号《改善厚膜混合集成电路同质键合系统质量一致性的方法》等。迄今为止，尚无抗干扰厚膜混合集成电路的专利申请件。
发明内容
本发明旨在提供抗干扰厚膜混合集成电路的集成方法，将金属和陶瓷的特性有机地结合在一起，实现从低频到高频的电磁屏蔽，增加厚膜混合集成电路的抗干扰能力。
为实现上述的目标，发明人将金属与陶瓷的复合材料用作封装外壳的管基和管帽材料，以满足从低频、中频到高频全频段的屏蔽要求，提供的集成方法是：在预先烧结成型的陶瓷管基、陶瓷管帽的外表面，采用涂覆金属浆料烧结或化学电镀的方式生长所需金属层，再进行半导体集成电路芯片和片式元器件的装贴、引线键合和封帽；这样，管基和管帽将陶瓷材料和金属材料二者有机结合，即实现从低频到高频的电磁屏蔽，使封装内外电磁环境达到良好的隔离，从而实现提高厚膜混合集成电路的抗干扰能力的目的。
上述方法中，所述管帽金属层和管基金属层的金属是铬和金。
本发明的方法具有以下优点：①从低频到高频的电磁屏蔽，使封装内外电磁环境达到良好的隔离，提升厚膜混合集成电路的抗干扰能力；②陶瓷高温烧结成型与金属层成型的工艺兼容性；③提高装备系统的可靠性；④可扩展到其他电路模块的电磁屏蔽。
用本发明方法生产的器件广泛应用于航天、航空、船舶、电子、通讯、医疗设备、工业控制等领域，特别适用于装备系统小型化、高频、高可靠的领域，具有广阔的市场前景和应用空间。
附图说明
图1为原有厚膜混合集成电路的管基示意图，图2为原有管帽示意图，图3为原有厚膜混合集成电路组装示意图，图4为本发明的管帽结构示意图，图5为本发明的厚膜混合集成电路示意图。
图中，1为金属管基，2为金属底座，3为金属管脚，4为金属管帽，5为半导体集成电路芯片，6为键合丝，7为厚膜电阻，8为厚膜导带/键合区，9为厚膜陶瓷基片背面金属层，10为厚膜陶瓷基片，11为管帽陶瓷基体，12为管帽外表面金属镀层，13为管基陶瓷基体，14为管基外表面金属镀层，15为片式元器件。
具体实施方式
实施例：以下为本发明的抗干扰厚膜混合集成电路的集成工艺：
（1）陶瓷管基、陶瓷管帽、镀层材料的准备；
（2）在陶瓷管基、陶瓷管帽的外表面化学镀铬；
（3）在陶瓷管基、陶瓷管帽的外表面电镀金；
（4）电镀后陶瓷管基、陶瓷管帽的清洗与烘干；
（5）基片清洗与烘干；
（6）在基片正面按设计图形要求进行厚膜导体浆料的印刷与烘干（150℃、10min）；
（7）在基片背面进行厚膜导体浆料的印刷与烘干（150℃、10min）
（8）在基片正面按设计图形要求进行厚膜电阻浆料的印刷和烘干（150℃、10min）；
（9）成膜烧结（850℃、10min，总时间35min）；
（10）调整电阻（激光调阻）；
（11）参数及功能测试；
（12）划片分离；
（13）将厚膜基片组装到管基的底座上；
（14）组装半导体芯片和片式元器件；
（15）用硅-铝丝或金丝键合以完成半导体芯片的电路连接、基片与管脚的电路连接；
（16）封帽；
（17）性能测试；
（18）老化筛选测试、密封性检查；
（19）产品编号打印、包装入库。
结果示意图如图5所示，实现本发明的目的。

Claims (3)

1.抗干扰厚膜混合集成电路的集成方法，其特征是将金属与陶瓷的复合材料用作管基和管帽的材料，以满足从低频、中频到高频全频段的屏蔽要求，具体的集成方法是：在预先烧结成型的陶瓷管基、陶瓷管帽的外表面，采用涂覆金属浆料烧结或化学电镀的方式生长所需金属层，再进行半导体集成电路芯片和片式元器件的装贴、引线键合和封帽；这样，管基和管帽将陶瓷材料和金属材料二者有机结合，即实现从低频到高频的电磁屏蔽，使封装内外电磁环境达到良好的隔离，从而实现提高厚膜混合集成电路抗干扰能力的目的。
2.如权利要求1所述的方法，详细的工艺流程是：
陶瓷管基、陶瓷管帽、镀层材料的准备；
在陶瓷管基、陶瓷管帽的外表面化学镀铬；
在陶瓷管基、陶瓷管帽的外表面电镀金；
电镀后陶瓷管基、陶瓷管帽的清洗与烘干；
基片清洗与烘干；
在基片正面按设计图形要求进行厚膜导体浆料的印刷与烘干，烘干温度150℃，烘干时间10min；
在基片背面进行厚膜导体浆料的印刷与烘干，烘干温度150℃，烘干时间10min；
在基片正面按设计图形要求进行厚膜电阻浆料的印刷和烘干，烘干温度150℃，烘干时间10min；
成膜烧结，峰值温度850℃、峰值温度时间10min，总时间35min；
激光调阻；
参数及功能测试；
划片分离；
将厚膜基片组装到管基的底座上；
组装半导体芯片和片式元器件；
用硅-铝丝或金丝键合以完成半导体芯片的电路连接、基片与管脚的电路连接；
封帽；
性能测试；
老化筛选测试、密封性检查；
产品编号打印、包装入库。
3.如权利要求1所述的方法，其特征在于所述管帽金属层和管基金属层的金属是铬和金。
CN201510882055.4A 2015-12-04 2015-12-04 抗干扰厚膜混合集成电路的集成方法 Pending CN105405803A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510882055.4A CN105405803A (zh) 2015-12-04 2015-12-04 抗干扰厚膜混合集成电路的集成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510882055.4A CN105405803A (zh) 2015-12-04 2015-12-04 抗干扰厚膜混合集成电路的集成方法

Publications (1)

Publication Number Publication Date
CN105405803A true CN105405803A (zh) 2016-03-16

Family

ID=55471205

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510882055.4A Pending CN105405803A (zh) 2015-12-04 2015-12-04 抗干扰厚膜混合集成电路的集成方法

Country Status (1)

Country Link
CN (1) CN105405803A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107640738A (zh) * 2017-07-24 2018-01-30 中北大学 一种用于射频mems开关的封装方法
CN112067931A (zh) * 2020-09-16 2020-12-11 中国电子科技集团公司第二十四研究所 厚膜电阻可靠性测试结构及测试方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201829493U (zh) * 2010-05-07 2011-05-11 贵州振华风光半导体有限公司 高可靠功率混合集成电路
CN102891113A (zh) * 2012-10-18 2013-01-23 贵州振华风光半导体有限公司 高灵敏温控厚膜混合集成电路的集成方法
CN103107123A (zh) * 2012-12-12 2013-05-15 贵州振华风光半导体有限公司 三维集成功率厚膜混合集成电路的集成方法
CN204118071U (zh) * 2014-06-30 2015-01-21 贵州振华风光半导体有限公司 高可靠氮化铝成膜基片厚膜混合集成电路
CN104485324A (zh) * 2014-12-15 2015-04-01 贵州振华风光半导体有限公司 无引线球脚表贴式微波薄膜混合集成电路及其集成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201829493U (zh) * 2010-05-07 2011-05-11 贵州振华风光半导体有限公司 高可靠功率混合集成电路
CN102891113A (zh) * 2012-10-18 2013-01-23 贵州振华风光半导体有限公司 高灵敏温控厚膜混合集成电路的集成方法
CN103107123A (zh) * 2012-12-12 2013-05-15 贵州振华风光半导体有限公司 三维集成功率厚膜混合集成电路的集成方法
CN204118071U (zh) * 2014-06-30 2015-01-21 贵州振华风光半导体有限公司 高可靠氮化铝成膜基片厚膜混合集成电路
CN104485324A (zh) * 2014-12-15 2015-04-01 贵州振华风光半导体有限公司 无引线球脚表贴式微波薄膜混合集成电路及其集成方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107640738A (zh) * 2017-07-24 2018-01-30 中北大学 一种用于射频mems开关的封装方法
CN107640738B (zh) * 2017-07-24 2019-05-28 中北大学 一种用于射频mems开关的封装方法
CN112067931A (zh) * 2020-09-16 2020-12-11 中国电子科技集团公司第二十四研究所 厚膜电阻可靠性测试结构及测试方法

Similar Documents

Publication Publication Date Title
CN101866861B (zh) 高可靠功率混合集成电路的集成方法
CN107919862A (zh) 一种声表面波器件气密性晶圆级封装结构和工艺
CN104485324A (zh) 无引线球脚表贴式微波薄膜混合集成电路及其集成方法
US7362038B1 (en) Surface acoustic wave (SAW) device package and method for packaging a SAW device
CN105405803A (zh) 抗干扰厚膜混合集成电路的集成方法
CN103632984B (zh) 无引线平面表贴式厚膜混合集成电路的集成方法
CN109361388B (zh) 一种小型化高气密性频率源及其封装方法
CN204145913U (zh) 一种片式微波组件结构
CN208087501U (zh) 一种AlN陶瓷金属化敷铜基板
CN204289432U (zh) 无引线平面表贴式微波薄膜混合集成电路
CN105489505A (zh) 抗干扰抗腐蚀厚膜混合集成电路的集成方法
CN205488129U (zh) 一种抗干扰抗腐蚀厚膜混合集成电路
CN209134387U (zh) 一种小型化高气密性频率源
CN205159318U (zh) 一种抗干扰厚膜混合集成电路
CN103107123B (zh) 三维集成功率厚膜混合集成电路的集成方法
CN104269382B (zh) 基于高温共烧陶瓷技术的x波段高可靠表贴型陶瓷外壳
CN105428298A (zh) 抗干扰薄膜混合集成电路的集成方法
CN205159317U (zh) 一种抗干扰半导体集成电路
CN205488120U (zh) 一种抗干扰薄膜混合集成电路
CN105024556A (zh) 基于低温共烧陶瓷混合集成的dc-dc变换器及其制造方法
CN205488089U (zh) 一种抗干扰抗腐蚀薄膜混合集成电路
CN105489545A (zh) 抗干扰抗腐蚀薄膜混合集成电路的集成方法
CN203690290U (zh) 无引线平面表贴式厚膜混合集成电路
CN103681364B (zh) 无引线球脚表贴式高密度厚膜混合集成电路的集成方法
CN108231722A (zh) 高密度表贴式半导体集成电路的集成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20160316

WD01 Invention patent application deemed withdrawn after publication