CN205159317U - 一种抗干扰半导体集成电路 - Google Patents

一种抗干扰半导体集成电路 Download PDF

Info

Publication number
CN205159317U
CN205159317U CN201520992894.7U CN201520992894U CN205159317U CN 205159317 U CN205159317 U CN 205159317U CN 201520992894 U CN201520992894 U CN 201520992894U CN 205159317 U CN205159317 U CN 205159317U
Authority
CN
China
Prior art keywords
integrated circuit
semiconductor integrated
metal
pipe cap
tube base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201520992894.7U
Other languages
English (en)
Inventor
杨成刚
刘学林
苏贵东
赵晓辉
黄晓山
杨晓琴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guizhou Zhenhua Fengguang Semiconductor Co.,Ltd.
Original Assignee
Guizhou Zhenhua Fengguang Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guizhou Zhenhua Fengguang Semiconductor Co Ltd filed Critical Guizhou Zhenhua Fengguang Semiconductor Co Ltd
Priority to CN201520992894.7U priority Critical patent/CN205159317U/zh
Application granted granted Critical
Publication of CN205159317U publication Critical patent/CN205159317U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

本实用新型公开的抗干扰半导体集成电路,由管帽、管基、管脚、半导体集成电路芯片组成,管帽封装在管基之上;其特征是管帽有金属外层和陶瓷内层,管基有金属层和陶瓷基体,管基顶层镶有陶瓷;管脚采用金属引脚;半导体集成电路芯片用金属键合丝键合在管基金属层上或采用金属球焊接集成在管基金属层上。本实用新型的管基和管帽外层为金属层、内层为陶瓷材料,将二者有机结合得到复合材料,实现从低频到高频的电磁屏蔽,使封装内外电磁环境达到良好的隔离,提升半导体集成电路的抗干扰能力。本实用新型的器件广泛应用于航天、航空、船舶、电子、通讯、医疗设备、工业控制等领域,特别适用于装备系统小型化、高频、高可靠的领域。

Description

一种抗干扰半导体集成电路
技术领域
本实用新型涉及集成电路,具体来说,涉及半导体集成电路,更进一步来说,涉及抗干扰半导体集成电路。
背景技术
原有半导体集成电路的集成技术中,将半导体集成电路芯片封装在金属管基和金属管帽内,或封装在陶瓷管基和陶瓷管帽内,先将半导体集成电路芯片装贴在管基上,再采用键合丝(金丝或硅铝丝)进行芯片与管脚的引线键合,完成整个电器连接,最后将管基和管帽进行密封而成。此方法存在的主要问题是在高频或电磁干扰的环境中,金属能有效地屏蔽低频、中频和部分高频干扰的影响,当频率继续增高时,金属的屏蔽作用就会变差;相反,陶瓷对低频、中频没有屏蔽能力,但对高频有良好的屏蔽能力。因此,采用金属封装、陶瓷封装均不能满足从低频、中频到高频全频段的屏蔽要求,还导致半导体集成电路在要求抗干扰的环境中使用时,需要在使用系统中增加大量的屏蔽措施,给使用造成诸多不便,不利于装备系统的小型化、集成化和轻便化。
中国专利数据库中,涉及半导体集成电路的专利以及专利申请件多达上千件,但涉及抗干扰半导体集成电路的专利仅有2012200511925号《环境因素采集系统以及半导体集成电路生产工艺测量设备》1件。迄今为止,尚无抗干扰半导体集成电路集成方法的专利申请件。
发明内容
本实用新型旨在提供一种抗干扰半导体集成电路,将金属和陶瓷的特性有机地结合在一起,实现从低频到高频的电磁屏蔽,增加抗干扰能力;从而有利于装备系统的小型化、集成化和轻便化。
设计人提供的抗干扰半导体集成电路由管帽、管基、管脚、半导体集成电路芯片组成,管帽封装在管基之上;与原有半导体集成电路不同的是:管帽有金属外层和陶瓷内层,管基有金属层和陶瓷基体,管基顶层镶有陶瓷;管脚采用金属引脚,引脚形状是球形、或针形、或平面形;半导体集成电路芯片用金属键合丝键合在管基金属层上或采用金属球焊接集成在管基金属层上。
上述集成电路中,所述管帽金属层的金属是铬和金;所述管基金属层的金属是金。
抗干扰半导体集成电路的集成方法是:在预先烧结成型的陶瓷管帽的外表面,采用涂覆金属浆料烧结方式或化学电镀方式或真空镀膜的方式形成所需管帽金属层;采用低温共烧陶瓷工艺(LTCC工艺)及厚膜印刷与烧结工艺制作管基底座,形成半导体集成电路芯片键合区、外表面管基金属层、对外引脚结构;再进行半导体集成电路芯片的装贴、引线键合和封帽。
本实用新型的具有以下优点:①管基和管帽外层为金属层、内层为陶瓷材料,将二者有机结合得到复合材料,即实现从低频到高频的电磁屏蔽,使封装内外电磁环境达到良好的隔离,提升半导体集成电路的抗干扰能力;②可以实现多层布线与集成,实现高密度集成;③可集成更多的电路功能,实现系统集成;④实现表贴式安装,缩小装备体积,提升装备的高频性能;⑤提高装备系统的可靠性;⑥可扩展到其他电路模块的电磁屏蔽。
本实用新型的器件广泛应用于航天、航空、船舶、电子、通讯、医疗设备、工业控制等领域,特别适用于装备系统小型化、高频、高可靠的领域,具有广阔的市场前景和应用空间。
附图说明
图1为本实用新型的引线键合的半导体集成电路示意图,图2为本实用新型的倒装键合的半导体集成电路示意图。
图中,1为管帽金属外层,2为管帽陶瓷内层,3为管基陶瓷基体,4为管基金属层,5为半导体集成电路芯片,6为键合丝,7为管基顶层的陶瓷,8为金属引脚,9为金属球焊接。
具体实施方式
实施例1:如图1的引线键合的半导体集成电路,由管帽、管基、管脚、半导体集成电路芯片组成,管帽封装在管基之上;与原有半导体集成电路不同的是:管帽有金属外层1和陶瓷内层2,管基有金属层4和陶瓷基体3,管基顶层镶有陶瓷7;管脚采用金属球引脚8;半导体集成电路芯片5用金属键合丝6键合在管基金属层4上。管帽金属外层1的金属是铬和金;管基金属层4的金属是金。
实施例2:如图2的倒装键合的半导体集成电路,由管帽、管基、管脚、半导体集成电路芯片组成,管帽封装在管基之上;与原有半导体集成电路不同的是:管帽有金属外层1和陶瓷内层2,管基有金属层4和陶瓷基体3,管脚采用金属球引脚8;半导体集成电路芯片5用金属球焊接9集成在管基金属层4上。管帽金属外层1的金属是铬和金;管基金属层4的金属是金。

Claims (3)

1.一种抗干扰半导体集成电路,由管帽、管基、管脚、半导体集成电路芯片(5)组成,管帽封装在管基之上;其特征在于管帽有金属外层(1)和陶瓷内层(2),管基有金属层(4)和陶瓷基体(3),管基顶层镶有陶瓷(7);管脚采用金属引脚(8);半导体集成电路芯片(5)用金属键合丝(6)键合在管基金属层(4)上或采用金属球焊接(9)集成在管基金属层(4)上。
2.如权利要求1所述的集成电路,其特征在于所述金属球引脚(8)的形状为是球形、或针形、或平面形。
3.如权利要求1所述的集成电路,其特征在于所述管帽金属外层(1)的金属是铬和金;管基金属层(4)的金属是金。
CN201520992894.7U 2015-12-04 2015-12-04 一种抗干扰半导体集成电路 Active CN205159317U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201520992894.7U CN205159317U (zh) 2015-12-04 2015-12-04 一种抗干扰半导体集成电路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201520992894.7U CN205159317U (zh) 2015-12-04 2015-12-04 一种抗干扰半导体集成电路

Publications (1)

Publication Number Publication Date
CN205159317U true CN205159317U (zh) 2016-04-13

Family

ID=55694979

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201520992894.7U Active CN205159317U (zh) 2015-12-04 2015-12-04 一种抗干扰半导体集成电路

Country Status (1)

Country Link
CN (1) CN205159317U (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108063130A (zh) * 2017-12-29 2018-05-22 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的电磁屏蔽封装结构及其制造工艺

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108063130A (zh) * 2017-12-29 2018-05-22 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的电磁屏蔽封装结构及其制造工艺

Similar Documents

Publication Publication Date Title
CN106298708B (zh) 封装结构及三维封装结构
CN104485324A (zh) 无引线球脚表贴式微波薄膜混合集成电路及其集成方法
CN205159317U (zh) 一种抗干扰半导体集成电路
CN105789142B (zh) 一种有机基板高密度集成的三维微波电路结构
CN103632984B (zh) 无引线平面表贴式厚膜混合集成电路的集成方法
CN204289432U (zh) 无引线平面表贴式微波薄膜混合集成电路
CN205159319U (zh) 一种抗干扰抗腐蚀半导体集成电路
CN105742195A (zh) 一种蚀刻埋孔型表面声滤波芯片封装结构的制造方法
CN205159318U (zh) 一种抗干扰厚膜混合集成电路
CN105405803A (zh) 抗干扰厚膜混合集成电路的集成方法
CN205610595U (zh) 金属圆片级表面声滤波芯片封装结构
CN205609499U (zh) 圆片级表面声滤波芯片封装结构
CN205488129U (zh) 一种抗干扰抗腐蚀厚膜混合集成电路
CN205754241U (zh) 一种体声波滤波器芯片的封装结构
CN205488120U (zh) 一种抗干扰薄膜混合集成电路
CN205488089U (zh) 一种抗干扰抗腐蚀薄膜混合集成电路
CN106952886B (zh) 一种射频芯片封装结构
CN203690290U (zh) 无引线平面表贴式厚膜混合集成电路
CN105897215A (zh) 一种体声波滤波器芯片的封装结构
CN211088262U (zh) 一种电磁屏蔽结构
CN107731763A (zh) 一种芯片封装模块及集成化ad采集装置
CN105552062A (zh) 抗干扰半导体集成电路的集成方法
CN210641072U (zh) 一种传感器封装结构以及电子设备
CN204289431U (zh) 无引线球脚表贴式微波薄膜混合集成电路
CN103681364B (zh) 无引线球脚表贴式高密度厚膜混合集成电路的集成方法

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: 550018 Guizhou Province, Guiyang city new North Avenue No. 238

Patentee after: Guizhou Zhenhua Fengguang Semiconductor Co.,Ltd.

Address before: 550018 Guizhou Province, Guiyang city new North Avenue No. 238

Patentee before: GUIZHOU ZHENHUA FENGGUANG SEMICONDUCTOR Co.,Ltd.