CN105489505A - 抗干扰抗腐蚀厚膜混合集成电路的集成方法 - Google Patents

抗干扰抗腐蚀厚膜混合集成电路的集成方法 Download PDF

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CN105489505A
CN105489505A CN201510882088.9A CN201510882088A CN105489505A CN 105489505 A CN105489505 A CN 105489505A CN 201510882088 A CN201510882088 A CN 201510882088A CN 105489505 A CN105489505 A CN 105489505A
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杨成刚
赵晓辉
刘学林
杨晓琴
路兰艳
聂平健
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Guizhou Zhenhua Fengguang Semiconductor Co Ltd
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Abstract

抗干扰抗腐蚀厚膜混合集成电路的集成方法，是将陶瓷与金属的复合材料用作管基和管帽材料，以满足从低频、中频到高频全频段的屏蔽和抗腐蚀要求，具体做法是：在预先烧结成型的陶瓷管基、陶瓷管帽的内表面，采用涂覆金属浆料烧结或化学电镀的方式生长所需金属层，再进行半导体集成电路芯片的装贴、引线键合和封帽，这样，管基和管帽将陶瓷材料和金属材料二者有机结合，实现从低频到高频的电磁屏蔽，使封装内外电磁环境达到良好的隔离，从而实现厚膜混合集成电路的抗干扰抗腐蚀能力。用本方法生产的器件广泛应用于航天、航空、船舶、电子、通讯、医疗设备、工业控制等领域，特别适用于装备系统小型化、高频、高可靠的领域。

Description

抗干扰抗腐蚀厚膜混合集成电路的集成方法
技术领域
本发明涉及集成电路，具体来说，涉及厚膜混合集成电路，更进一步来说，涉及抗干扰抗腐蚀厚膜混合集成电路。
技术背景
原有厚膜混合集成电路的集成技术中，先将厚膜陶瓷基片装贴在金属管基上，再将半导体芯片、片式元器件直接装贴在厚膜基片上，再采用键合丝（金丝或硅铝丝）进行芯片与基片的引线键合，基片和管脚的引线键合，完成整个电器连接，最后在高真空、高纯氮气或高纯氩气等特定的气氛中将金属管基和金属管帽（或陶瓷管基和陶瓷管帽）进行密封而成。此方法存在的主要问题是在高频或电磁干扰的环境中，金属能有效地屏蔽低频、中频和部分高频干扰的影响，当频率继续增高时，金属的屏蔽作用就会变差。相反，陶瓷对低频、中频没有屏蔽能力，但对高频有良好的屏蔽能力。因此，采用金属封装、陶瓷封装均不能满足从低频、中频到高频全频段的屏蔽要求。导致厚膜混合集成电路在要求抗干扰的环境中使用时，需要在使用系统中增加大量的屏蔽措施，给使用造成诸多不便，不利于装备系统的小型化、集成化和轻便化。另一方面，由于使用金属外壳，抗腐蚀性差，不适用于带腐蚀性的恶劣气氛环境中。
中国专利数据库中，涉及厚膜混合集成电路的专利以及专利申请件有十余件，如2011104461041号《高集成高可靠工作温度可控厚膜混合集成电路的集成方法》、2012105301453号《一种用于厚膜混合集成电路的成膜工艺》、ZL2012103961942号《高灵敏温控厚膜混合集成电路的集成方法》、ZL2012105353566号《三维集成功率厚膜混合集成电路的集成方法》、ZL201210535366X号《一种高集成度功率厚膜混合集成电路的集成方法》、2012105373165号《改善厚膜混合集成电路同质键合系统质量一致性的方法》等。迄今为止，尚无抗干扰厚膜混合集成电路的专利申请件。
发明内容
本发明旨在提供抗干扰抗腐蚀厚膜混合集成电路的集成方法，实现从低频到高频的电磁屏蔽，增加厚膜混合集成电路的抗干扰能力，同时解决抗腐蚀性问题。
为实现上述的目标，发明人将陶瓷与金属复合材料用作封装外壳的管基和管帽材料，以满足从低频、中频到高频全频段的屏蔽和抗腐蚀要求，具体做法是：在预先烧结成型的陶瓷管基、陶瓷管帽的内表面，采用涂覆金属浆料烧结或化学电镀的方式生长所需金属层，再进行半导体集成电路芯片的装贴、引线键合和封帽，这样，管基和管帽外层为陶瓷材料，内层为金属材料，二者有机结合，实现从低频到高频的电磁屏蔽，使封装内外电磁环境达到良好的隔离，从而实现厚膜混合集成电路的抗干扰能力，同时，由于封装外层为陶瓷，具有很强的抗腐蚀能力，从而实现使厚膜混合集成电路的抗干扰抗腐蚀的目的。
上述方法中，所述管帽金属层和管基金属层涂覆的金属是铬和金。
本发明的方法具有以下优点：①从低频到高频的电磁屏蔽，使封装内外电磁环境达到良好的隔离，提升厚膜混合集成电路的抗干扰能力；②抗腐蚀能力强；③陶瓷高温烧结成型与金属层成型的工艺兼容性；④有利于装备系统的小型化、集成化和轻便化；⑤提高装备系统的可靠性。
用本发明方法生产的器件广泛应用于航天、航空、船舶、电子、通讯、医疗设备、工业控制等领域，特别适用于装备系统小型化、高频、高可靠的领域，具有广阔的市场前景和应用空间。
附图说明
图1为原有厚膜混合集成电路的管基示意图，图2为原有管帽示意图，图3为原有厚膜混合集成电路组装示意图，图4为本发明的管帽结构示意图，图5为本发明的厚膜混合集成电路组装示意图。
图中，1为金属管基，2为金属底座，3为金属管脚，4为金属管帽，5为半导体集成电路芯片，6为键合丝，7为厚膜电阻，8为厚膜导带/键合区，9为厚膜陶瓷基片背面金属层，10为厚膜陶瓷基片，11为管帽陶瓷基体，12为管帽内表面金属镀层，13为管基陶瓷基体，14为管基内表面金属镀层，15为片式元器件。
具体实施方式
实施例：以下为本发明的抗干扰抗腐蚀厚膜混合集成电路的集成工艺：
（1）陶瓷管基、陶瓷管帽、镀层材料的准备；
（2）在陶瓷管基、陶瓷管帽的内表面化学镀铬；
（3）在陶瓷管基、陶瓷管帽的内表面电镀金；
（4）电镀后陶瓷管基、陶瓷管帽的清洗与烘干；
（5）基片清洗与烘干；
（6）在基片正面按设计图形要求进行厚膜导体浆料的印刷并在150℃下烘干10min；
（7）在基片背面进行厚膜导体浆料的印刷并在150℃下烘干10min；
（8）在基片正面按设计图形要求进行厚膜电阻浆料的印刷并在150℃下烘干10min；
（9）成膜在850℃下烧结10min，总时间35min；
（10）激光调整电阻；
（11）参数及功能测试；
（12）划片分离；
（13）将厚膜基片组装到管基的底座上；
（14）组装半导体芯片和片式元器件；
（15）用硅-铝丝或金丝键合以完成半导体芯片的电路连接、基片与管脚的电路连接；
（16）封帽；
（17）性能测试；
（18）老化筛选测试、密封性检查；
（19）产品编号打印、包装入库。
得到的抗干扰抗腐蚀厚膜混合集成电路如图5所示。

Claims (3)

1.抗干扰抗腐蚀厚膜混合集成电路的集成方法，其特征是将陶瓷与金属的复合材料用作管基和管帽材料，以满足从低频、中频到高频全频段的屏蔽和抗腐蚀要求，具体做法是：在预先烧结成型的陶瓷管基、陶瓷管帽的内表面，采用涂覆金属浆料烧结或化学电镀的方式生长所需金属层，再进行半导体集成电路芯片的装贴、引线键合和封帽，这样，管基和管帽外层为陶瓷材料，内层为金属材料，二者有机结合，实现从低频到高频的电磁屏蔽，使封装内外电磁环境达到良好的隔离，从而实现厚膜混合集成电路的抗干扰能力，同时，由于封装外层为陶瓷，具有很强的抗腐蚀能力，从而实现使厚膜混合集成电路抗干扰抗腐蚀的目的。
2.如权利要求1所述的方法，详细的集成工艺是：
陶瓷管基、陶瓷管帽、镀层材料的准备；
在陶瓷管基、陶瓷管帽的内表面化学镀铬；
在陶瓷管基、陶瓷管帽的内表面电镀金；
电镀后陶瓷管基、陶瓷管帽的清洗与烘干；
基片清洗与烘干；
在基片正面按设计图形要求进行厚膜导体浆料的印刷与烘干，烘干温度150℃，烘干时间10min；
在基片背面进行厚膜导体浆料的印刷与烘干，烘干温度150℃，烘干时间10min；
在基片正面按设计图形要求进行厚膜电阻浆料的印刷和烘干，烘干温度150℃，烘干时间10min；
成膜烧结，峰值温度850℃、峰值温度时间10min，总时间35min；
激光调阻；
参数及功能测试；
划片分离；
将厚膜基片组装到管基的底座上；
组装半导体芯片和片式元器件；
用硅-铝丝或金丝键合以完成半导体芯片的电路连接、基片与管脚的电路连接；
封帽；
性能测试；
老化筛选测试、密封性检查；
产品编号打印、包装入库。
3.如权利要求1所述的方法，其特征在于所述管帽金属层和管基金属层的金属层结构是铬和金。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107640738A (zh) * 2017-07-24 2018-01-30 中北大学 一种用于射频mems开关的封装方法

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Application publication date: 20160413