CN103621005B - 用于快速相位对齐的增强型鉴相器 - Google Patents
用于快速相位对齐的增强型鉴相器 Download PDFInfo
- Publication number
- CN103621005B CN103621005B CN201280032101.6A CN201280032101A CN103621005B CN 103621005 B CN103621005 B CN 103621005B CN 201280032101 A CN201280032101 A CN 201280032101A CN 103621005 B CN103621005 B CN 103621005B
- Authority
- CN
- China
- Prior art keywords
- phase
- clock
- signal
- adjustment
- sample
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/173,377 US8611487B2 (en) | 2011-06-30 | 2011-06-30 | Enhanced phase discriminator for fast phase alignment |
US13/173,377 | 2011-06-30 | ||
US13/173377 | 2011-06-30 | ||
PCT/EP2012/062317 WO2013000891A1 (en) | 2011-06-30 | 2012-06-26 | Enhanced phase discriminator for fast phase alignment |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103621005A CN103621005A (zh) | 2014-03-05 |
CN103621005B true CN103621005B (zh) | 2017-08-25 |
Family
ID=46489188
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201280032101.6A Expired - Fee Related CN103621005B (zh) | 2011-06-30 | 2012-06-26 | 用于快速相位对齐的增强型鉴相器 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8611487B2 (zh) |
EP (1) | EP2727276A1 (zh) |
CN (1) | CN103621005B (zh) |
DE (1) | DE112012002684B4 (zh) |
WO (1) | WO2013000891A1 (zh) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9832009B2 (en) * | 2015-07-28 | 2017-11-28 | Rambus Inc. | Collaborative clock and data recovery |
US10177897B2 (en) | 2016-10-07 | 2019-01-08 | Analog Devices, Inc. | Method and system for synchronizing and interleaving separate sampler groups |
US10389366B2 (en) * | 2017-06-29 | 2019-08-20 | Qualcomm Incorporated | SerDes with adaptive clock data recovery |
TWI707544B (zh) * | 2018-11-22 | 2020-10-11 | 瑞昱半導體股份有限公司 | 訊號偵測器與訊號偵測方法 |
CN111239476B (zh) * | 2018-11-29 | 2022-11-22 | 瑞昱半导体股份有限公司 | 信号检测器与信号检测方法 |
US10862666B2 (en) * | 2019-01-14 | 2020-12-08 | Texas Instruments Incorporated | Sampling point identification for low frequency asynchronous data capture |
US11984896B2 (en) | 2021-09-23 | 2024-05-14 | Apple Inc. | Clock alignment and uninterrupted phase change systems and methods |
US11740650B2 (en) | 2021-09-23 | 2023-08-29 | Apple Inc. | Clock alignment and uninterrupted phase change systems and methods |
US12088303B1 (en) | 2023-02-23 | 2024-09-10 | Qualcomm Incorporated | Self-calibrated phase tuning system |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5068628A (en) * | 1990-11-13 | 1991-11-26 | Level One Communications, Inc. | Digitally controlled timing recovery loop |
CN1322073A (zh) * | 2000-07-26 | 2001-11-14 | 深圳市中兴通讯股份有限公司 | 一种宽带码分多址系统码跟踪及解扩解扰方法和装置 |
US7113560B1 (en) * | 2002-09-24 | 2006-09-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Serial link scheme based on delay lock loop |
US7349509B2 (en) * | 2004-04-21 | 2008-03-25 | Kawasaki Lsi U.S.A., Inc. | Multi rate clock data recovery based on multi sampling technique |
CN101800540A (zh) * | 2010-03-15 | 2010-08-11 | 中国电子科技集团公司第十研究所 | 锁定假锁判决电路 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040088594A1 (en) | 2002-10-31 | 2004-05-06 | Canagasaby Karthisha S. | Receiver tracking mechanism for an I/O circuit |
DE102004014695B4 (de) | 2003-03-26 | 2007-08-16 | Infineon Technologies Ag | Takt- und Datenwiedergewinnungseinheit |
US7340021B1 (en) | 2003-11-13 | 2008-03-04 | Altera Corporation | Dynamic phase alignment and clock recovery circuitry |
KR100633774B1 (ko) * | 2005-08-24 | 2006-10-16 | 삼성전자주식회사 | 넓은 위상 여유를 가지는 클럭 및 데이터 리커버리 회로 |
US7844021B2 (en) * | 2006-09-28 | 2010-11-30 | Agere Systems Inc. | Method and apparatus for clock skew calibration in a clock and data recovery system using multiphase sampling |
US8699647B2 (en) | 2009-06-23 | 2014-04-15 | Intel Mobile Communications GmbH | Fast phase alignment for clock and data recovery |
JP5300671B2 (ja) * | 2009-09-14 | 2013-09-25 | 株式会社東芝 | クロックリカバリ回路およびデータ再生回路 |
-
2011
- 2011-06-30 US US13/173,377 patent/US8611487B2/en not_active Expired - Fee Related
-
2012
- 2012-06-26 WO PCT/EP2012/062317 patent/WO2013000891A1/en active Application Filing
- 2012-06-26 DE DE112012002684.5T patent/DE112012002684B4/de not_active Expired - Fee Related
- 2012-06-26 CN CN201280032101.6A patent/CN103621005B/zh not_active Expired - Fee Related
- 2012-06-26 EP EP12733447.2A patent/EP2727276A1/en not_active Withdrawn
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5068628A (en) * | 1990-11-13 | 1991-11-26 | Level One Communications, Inc. | Digitally controlled timing recovery loop |
CN1322073A (zh) * | 2000-07-26 | 2001-11-14 | 深圳市中兴通讯股份有限公司 | 一种宽带码分多址系统码跟踪及解扩解扰方法和装置 |
US7113560B1 (en) * | 2002-09-24 | 2006-09-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Serial link scheme based on delay lock loop |
US7349509B2 (en) * | 2004-04-21 | 2008-03-25 | Kawasaki Lsi U.S.A., Inc. | Multi rate clock data recovery based on multi sampling technique |
CN101800540A (zh) * | 2010-03-15 | 2010-08-11 | 中国电子科技集团公司第十研究所 | 锁定假锁判决电路 |
Also Published As
Publication number | Publication date |
---|---|
DE112012002684B4 (de) | 2015-11-26 |
EP2727276A1 (en) | 2014-05-07 |
US20130003907A1 (en) | 2013-01-03 |
US8611487B2 (en) | 2013-12-17 |
DE112012002684T5 (de) | 2014-06-12 |
CN103621005A (zh) | 2014-03-05 |
WO2013000891A1 (en) | 2013-01-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103621005B (zh) | 用于快速相位对齐的增强型鉴相器 | |
KR100780952B1 (ko) | 디스큐 장치 및 방법, 그리고 이를 이용한 데이터 수신장치및 방법 | |
US7630467B2 (en) | Data recovery circuits using oversampling for best data sample selection | |
US7349509B2 (en) | Multi rate clock data recovery based on multi sampling technique | |
US20070047686A1 (en) | Clock and data recovery circuit | |
US7957497B2 (en) | Clock and data recovery circuits using random edge sampling and recovery method therefor | |
CN102148616B (zh) | 防止延迟锁相环错误锁定的方法及其系统 | |
US20020027964A1 (en) | Data recovery apparatus and method for minimizing errors due to clock skew | |
US8594264B1 (en) | Phase detection and aligned signal selection with multiple phases of clocks | |
CN103490775A (zh) | 基于双环结构的时钟数据恢复控制器 | |
CN116707521A (zh) | 面向8.1Gbps eDP高速显示接口接收端时钟数据恢复关键电路系统 | |
CN100531026C (zh) | 跃迁检测、确认和存储电路 | |
US20050135518A1 (en) | Improvements to data recovery circuits using oversampling for isi compensation | |
JP5166924B2 (ja) | 信号再生回路 | |
US9568890B1 (en) | All-digital delay-locked loop circuit based on time-to-digital converter and control method thereof | |
CN103077731B (zh) | 校正装置与校正方法 | |
CN102299786A (zh) | 数字接收机 | |
US20200099506A1 (en) | Fixing dead-zone in clock data recovery circuits | |
US11012077B2 (en) | Integrated circuit detecting frequency and phase of clock signal and clock and data recovery circuit including the integrated circuit | |
US8718215B2 (en) | Method and apparatus for deskewing data transmissions | |
CN104038216A (zh) | 一种高速信号中提取比特同步时钟的电路 | |
US7260145B2 (en) | Method and systems for analyzing the quality of high-speed signals | |
CN106254287B (zh) | 一种基于FPGA的多通道高速输入信号自动de-skew方法 | |
CN101873133B (zh) | 应用于通信时钟恢复的频率锁定方法及其电学器件结构 | |
US20090257537A1 (en) | Data recovery circuit of semiconductor memory apparatus that minimizes jitter during data transmission |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information |
Address after: Neubiberg, Germany Applicant after: Intel Mobile Communications GmbH Address before: Neubiberg, Germany Applicant before: Intel Mobile Communications GmbH |
|
COR | Change of bibliographic data | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20200717 Address after: California, USA Patentee after: Apple Inc. Address before: California, USA Patentee before: INTEL Corp. Effective date of registration: 20200717 Address after: California, USA Patentee after: INTEL Corp. Address before: Neubiberg, Germany Patentee before: Intel Mobile Communications GmbH |
|
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170825 |