CN103617952A - Diode wet etching method - Google Patents
Diode wet etching method Download PDFInfo
- Publication number
- CN103617952A CN103617952A CN201310635376.5A CN201310635376A CN103617952A CN 103617952 A CN103617952 A CN 103617952A CN 201310635376 A CN201310635376 A CN 201310635376A CN 103617952 A CN103617952 A CN 103617952A
- Authority
- CN
- China
- Prior art keywords
- layer
- conductive layer
- barrier layer
- diode
- corroded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000001039 wet etching Methods 0.000 title claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 73
- 239000002184 metal Substances 0.000 claims abstract description 45
- 229910052751 metal Inorganic materials 0.000 claims abstract description 45
- 238000005530 etching Methods 0.000 claims abstract description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 42
- 229910052710 silicon Inorganic materials 0.000 claims description 42
- 239000010703 silicon Substances 0.000 claims description 42
- 239000007788 liquid Substances 0.000 claims description 40
- 230000007797 corrosion Effects 0.000 claims description 28
- 238000005260 corrosion Methods 0.000 claims description 28
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 238000001514 detection method Methods 0.000 abstract 1
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 230000003628 erosive effect Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 229960000583 acetic acid Drugs 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012362 glacial acetic acid Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 239000003518 caustics Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000008450 motivation Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
Abstract
The invention discloses a diode wet etching method. The diode wet etching method comprises the first step of etching a conducting layer and a barrier layer to form a plurality of etched units, the second step of etching adhesion layers formed among the etched units, the third step of etching the edge parts of the conducting layers of the etched units and the edge parts of the barrier layers of the etched units to enable the edges of the adhesion layers of the etched units to be exposed below the conducting layers and the barrier layers. Compared with an existing wet etching method, the diode wet etching method has the advantage that a secondary conducting layer and barrier layer etching step is added. Therefore, the adhesion layers have one more edge to be exposed compared with the barrier layers and the conducting layers on the adhesion layers, and the frequency of adhesion layer undercutting is effectively reduced. When detection is carried out under a lens, whether undercutting exists in the adhesion layer of a metal layer on the bottom layer or not is judged according to the existence of the exposed edge. If the exposed edge exists, undercutting does not happen, and the using of a product cannot be affected even when the exposed edge exists.
Description
Technical field
The present invention relates to diode fabricating method, particularly Schottky barrier diode wet etching method.
Background technology
The front of Schottky barrier diode (SBD) adopts multi-layer metal structure, in this structure, by silicon substrate 4, is upwards followed successively by adhesion layer 1, barrier layer 2 (filter course) and conductive layer 3.
In Schottky barrier diode manufacture process, the wet etching method of the multiple layer metal layer corrosion on silicon substrate has multiple.For example:
But it is intrinsic that problems is generally considered to be this technique, do not attract people's attention and improved motivation.
Summary of the invention
The object of this invention is to provide a kind of diode wet etching method, can overcome one or more in above-mentioned prior art defect.
According to an aspect of the present invention, provide diode wet etching method, comprised the following steps: a, corrosion conductive layer and barrier layer, formed a plurality of unit that are corroded; B, corrode the adhesion layer being corroded between unit described in a plurality of; C, the marginal portion of conductive layer and the marginal portion on barrier layer of corroding the unit that is corroded described in a plurality of, the edge of the adhesion layer of the unit that is corroded described in making exposes from conductive layer and barrier layer.
The present invention has increased the step on a step anticaustic conductive layer and barrier layer than existing wet etching.Make like this adhesion layer expose a limit than barrier layer and conductive layer above more, effectively reduce the generation of adhesion layer undercutting situation.While checking, according to the existence on this limit, whether judge the whether undercutting of bottom metal layer adhesion layer under mirror.This limit exists, and illustrates and does not occur undercutting, and the existence on this limit can not exert an influence to the use of product.
In some embodiments, step a comprises, on the silicon chip with multiple layer metal to be corroded, applies mask; Mask silicon chip is inserted in conductive layer corrosive liquid, the conductive layer in mask window is once corroded; The silicon chip that erodes conductive layer is inserted in the corrosive liquid of barrier layer, the barrier layer in mask window is once corroded.
In some embodiments, step c comprises: the silicon chip that step b is obtained is inserted in conductive layer corrosive liquid, and the conductive layer in mask window is carried out to anticaustic; By inserting in the corrosive liquid of barrier layer through the silicon chip of conductive layer anticaustic, anticaustic is carried out in the barrier layer in mask window.
In some embodiments, step a comprises: on the silicon chip with multiple layer metal to be corroded, apply mask, the cut edge that mask window is monocrystalline; Mask silicon chip is inserted in conductive layer-barrier layer corrosive liquid that can simultaneously corrode conductive layer and barrier layer, and the conductive layer in mask window and barrier layer are once corroded.Thus, reduce corrosion step, make technique simple, reduce the phenomenons such as each layer of layering and metal edge be uneven.
In some embodiments, step c comprises: the silicon chip obtaining in step b is inserted again in the erosion liquid of conductive layer-barrier layer corruption, conductive layer and barrier layer are carried out to anticaustic.The generation of the phenomenons such as thus, minimizing corrosion step, makes technique simple, reduces the layering of metal, and metal edge is uneven.
In some embodiments, in step c, etching time is shorter than etching time in step a.Again can be to barrier layer and conductive layer excessive corrosion when making barrier layer above of adhesion layer and conductive layer expose a limit more.
In some embodiments, in step b, the adhesion layer being corroded between unit described in the corrosion of employing adhesion layer corrosive liquid is a plurality of.
In some embodiments, after each corrosion, the silicon chip through corrosion treatment is washed by water.Remove residual corrosive liquid, prevent conductive layer and barrier layer excessive corrosion, eliminate the impact on next treatment step.
In some embodiments, after described step c, also comprise steps d: the silicon chip of processing through step c is checked, the edge that can see adhesion layer exposes to be judged as and do not occur undercutting from conductive layer and barrier layer.Can judge that thus whether diode is qualified.
The problem of easy generation undercutting phenomenon when the present invention has overcome multiple layer metal corrosion on silicon chip.Solve underlying metal undercutting simultaneously and be difficult for found problem.
Accompanying drawing explanation
Fig. 1 is the structural representation after the multiple layer metal of diode under perfect condition corrodes;
Fig. 2 is for adopting existing wet etching method to produce undercutting situation schematic diagram;
Fig. 3 is for adopting the rear structural representation of diode wet etching method corrosion of the present invention.
Embodiment
Below lithographic method of the present invention is described in further detail.
As shown in Figure 1, the multi-layer metal structure in silicon substrate 4 fronts of Schottky barrier diode is followed successively by adhesion layer 1, barrier layer 2 and conductive layer 3.The layer structure of silicon chip for the manufacture of Schottky barrier diode is identical with the layer structure of Schottky barrier diode.
Step a:
Adopt mask etch method, to be corroded, apply in a conventional manner mask on the silicon chip of multiple layer metal, mask window position is the cut edge of a plurality of unit that are corroded;
Mask silicon chip is inserted in the conductive layer corrosive liquid that can corrode conductive layer 3, the conductive layer 3 in mask window is once corroded, form a plurality of unit that are corroded;
The silicon chip bath of conductive layer will be eroded;
By the silicon chip after bath insert can the barrier layer corrosive liquid of corrosion barrier layer 2 in, the barrier layer 2 in mask window is once corroded, a plurality of barrier layers 2 that are corroded between unit are eroded;
The silicon chip bath on barrier layer 2 will be eroded.
Step b:
A plurality of adhesion layers 1 that are corroded between unit of adhesion layer corrosive liquid corrosion with corroding adhesion layer 1, separate a plurality of being corroded completely between unit;
By eroding the silicon chip bath of adhesion layer 1, remove residual adhesion layer corrosive liquid, prevent adhesion layer 1 excessive corrosion and eliminate the impact of remaining adhesion layer corrosive liquid on next treatment step.
Step c:
The silicon chip that step b is obtained is inserted in conductive layer corrosive liquid, and the conductive layer 3 in mask window is carried out to anticaustic.In this step, conductive layer corrosive liquid is identical with conductive layer corrosive liquid in step a, and the time that etching time once corrodes than conductive layer in step a is short; In the etching time in step a, conductive layer 3 once being corroded and step c, the etching time sum of conductive layer 3 anticaustics is equal to or greater than to the etching time to conductive layer 3 in conventional method.Different according to conductive layer metal thickness, determine the ratio of twice etching time, for example, when metal thickness is larger, can select for the first time and for the second time etching time than being 8:2, metal thickness hour, can select time than for 7:3 etc.
By the silicon chip bath through conductive layer anticaustic;
To insert in the corrosive liquid of barrier layer through the silicon chip of conductive layer anticaustic, anticaustic is carried out in the barrier layer 2 in mask window, the edge of the adhesion layer 1 of the unit that makes to be corroded exposes for 2 from conductive layer 3 and barrier layer.In this step, barrier layer corrosive liquid is identical with barrier layer corrosive liquid in step a, and the time that etching time once corrodes than barrier layer in step a is short.
In the etching time in step a, barrier layer 2 once being corroded and step c, the etching time sum of barrier layer 2 anticaustics is equal to or greater than to the etching time to barrier layer 2 in conventional method.
By the silicon chip bath through barrier layer anticaustic, and dry.
Steps d: the silicon chip of processing through step c is checked under mirror, as shown in Figure 3, can see that undercutting does not appear in being judged as that the edge 11 of adhesion layer 1 exposes from conductive layer and barrier layer.While checking, according to the existence at this edge 11, whether judge whether undercutting of adhesion layer under mirror.This edge 11 exists, and illustrate and do not occur undercutting, and the existence at this edge 11 can not exert an influence to the use of product.
Step a:
Adopt mask etch method, on the silicon chip with multiple layer metal to be corroded, apply mask, mask window position is the cut edge of a plurality of unit that are corroded;
Mask silicon chip is inserted in conductive layer-barrier layer corrosive liquid that can simultaneously corrode conductive layer 3 and barrier layer 2, the conductive layer 3 in mask window and barrier layer 2 are once corroded, form a plurality of unit that are corroded;
By the silicon chip bath of once corroding through conductive layer and barrier layer.
Step b:
A plurality of adhesion layers 1 that are corroded between unit of adhesion layer corrosive liquid corrosion with corroding adhesion layer 1, separate a plurality of being corroded completely between unit.The silicon chip bath of adhesion layer 1 will be eroded.
Step c: the silicon chip obtaining in step b is inserted in the corrosive liquid of conductive layer-barrier layer again, conductive layer 3 and barrier layer 2 are carried out to anticaustic, the edge of adhesion layer 1 is exposed for 2 from conductive layer 3 and barrier layer, obtain diode shown in Fig. 3, an edge 11 is exposed on adhesion layer 1 conductive layer 3 and barrier layer more than 2 above.In this step, conductive layer-barrier layer corrosive liquid is identical with the conductive layer-barrier layer corrosive liquid in step a, etching time is shorter than etching time in step a, can either make thus the edge of adhesion layer 1 expose for 2 from conductive layer 3 and barrier layer, whether convenient inspection product is qualified, can too much not corrode conductive layer 3 and barrier layer 2 again.Then bath, and dry.
Steps d: the silicon chip of processing through step c is checked under mirror, and the edge 11 that can see adhesion layer 1 exposes for 2 to be judged as from conductive layer 3 and barrier layer and do not occur undercutting.While checking, according to the existence at this edge 11, whether judge whether undercutting of adhesion layer under mirror.This edge 11 exists, and illustrate and do not occur undercutting, and the existence at this edge 11 can not exert an influence to the use of product.
In above-mentioned execution mode of the present invention, total etching time of anticaustic technique combination as mentioned above, is to need design.The corrosion of first step time used from conventional caustic solution is also different.For example: adopt conventional method corrosion with 7 minutes; And adopt after the method for embodiment of the present invention, corrosion was for the first time with 5 minutes, and corrosion was with 2 minutes for the second time.In the preparation technology of the Schottky barrier diode of prior art, there is no so simple edge that again corrodes and expose the anticaustic technique of metal (being referred to as returning of metal in the present invention floats) below.
The multi-layer metal structure of maximum Schottky barrier diodes of use is at present: adhesion layer 1 is Ti metal level, and barrier layer 2 is Ni metal level, and conductive layer 3 is Ag metal level.Also have some other conventional metal structures, as: Ti/Ni/AL, V/Ni/Ag, V/Ni/AL etc.
The diode of Ti/Ni/Ag=2000/3000/30000 dust of take is example, and corrosion step is the same, wherein:
The corrosive liquid adopting in step a is Ni-Ag corrosive liquid, and Ni-Ag corrosive liquid is that volume ratio is nitric acid and the glacial acetic acid of 1:2.Wherein, etching time is 10 minutes.In Ni-Ag corrosive liquid the volume ratio of nitric acid and glacial acetic acid can be between 1:2～1:3 value.Etching time can be also other numerical value between 5～10 minutes.
In step b, corrosive liquid used is Ti corrosive liquid, and Ti corrosive liquid is that volume ratio is water and the hydrofluoric acid of 50:1.Etching time is 30 seconds.Etching time also can, for the numerical value between 30～60 seconds, be determined according to the thickness of metal level equally.
In step c, adopt and corrosive liquid identical in step a, etching time is 2 minutes.Etching time is shorter than etching time in step a, and the edge that can erode Ni metal level and Ag metal level makes the edge of Ti metal level expose from the below of Ni metal level and Ag metal level, can not cause Ni metal level and Ag metal level are too much corroded again.In this step, etching time can be also other numerical value between 1～3 minute.
In the etching time in step a, conductive layer 3 and barrier layer 2 once being corroded and step c, the etching time sum of conductive layer 3 and barrier layer 2 anticaustics is equal to or greater than to the etching time to conductive layer 3 and barrier layer 2 in conventional method.
The bath time in step a1, step b1 and step c1 is 10 minutes.
When the multiple layer metal on diode is the structures such as Ti/Ni/Al, V/Ni/Ag, V/Ni/Al, can adopt corresponding corrosive liquid and according to the thickness of each layer of metal level, etching time is set can obtain the product of structure shown in Fig. 3 equally according to above-mentioned steps.
Above-described is only some embodiments of the present invention.For the person of ordinary skill of the art, without departing from the concept of the premise of the invention, can also make some distortion and improvement, these all belong to protection scope of the present invention.
Claims (9)
1. diode wet etching method, wherein, comprises the following steps:
A, corrosion conductive layer and barrier layer, form a plurality of unit that are corroded;
B, corrode the adhesion layer being corroded between unit described in a plurality of;
Described in c, corrosion, the be corroded marginal portion of conductive layer and the marginal portion on barrier layer of unit, the edge of the adhesion layer of the unit that is corroded described in making exposes from conductive layer and barrier layer.
2. diode wet etching method according to claim 1, wherein, described step a comprises,
On the silicon chip with multiple layer metal to be corroded, apply mask;
Mask silicon chip is inserted in conductive layer corrosive liquid, the conductive layer in mask window is once corroded;
The silicon chip that erodes conductive layer is inserted in the corrosive liquid of barrier layer, the barrier layer in mask window is once corroded.
3. diode wet etching method according to claim 2, wherein, described step c comprises:
The silicon chip that step b is obtained is inserted in conductive layer corrosive liquid, and the conductive layer in mask window is carried out to anticaustic;
By inserting in the corrosive liquid of barrier layer through the silicon chip of conductive layer anticaustic, anticaustic is carried out in the barrier layer in mask window.
4. diode wet etching method according to claim 1, wherein, step a comprises
On the silicon chip with multiple layer metal to be corroded, apply mask;
Mask silicon chip is inserted in conductive layer-barrier layer corrosive liquid that can simultaneously corrode conductive layer and barrier layer, the conductive layer in mask window and barrier layer are once corroded.
5. diode wet etching method according to claim 4, wherein, step c comprises: the silicon chip obtaining in step b is inserted in the corrosive liquid of conductive layer-barrier layer again, conductive layer and barrier layer are carried out to anticaustic.
6. diode wet etching method according to claim 5, wherein, in step c, etching time is shorter than etching time in step a.
7. according to the diode wet etching method described in claim 1～6 any one, wherein, in described step b, the adhesion layer that adopts the corrosion of adhesion layer corrosive liquid to be corroded between unit described in a plurality of.
8. diode wet etching method according to claim 7, wherein, washes by water to the silicon chip through corrosion treatment after each corrosion.
9. according to the diode wet etching method described in claim 1～8 any one, wherein, after described step c, also comprise steps d: the silicon chip of processing through step c is checked, the edge that can see adhesion layer exposes to be judged as and do not occur undercutting from conductive layer and barrier layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310635376.5A CN103617952B (en) | 2013-11-29 | 2013-11-29 | Diode wet etching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310635376.5A CN103617952B (en) | 2013-11-29 | 2013-11-29 | Diode wet etching method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103617952A true CN103617952A (en) | 2014-03-05 |
| CN103617952B CN103617952B (en) | 2016-08-17 |
Family
ID=50168655
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310635376.5A Active CN103617952B (en) | 2013-11-29 | 2013-11-29 | Diode wet etching method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103617952B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0519301B2 (en) * | 1988-12-08 | 1993-03-16 | Sanken Electric Co Ltd | |
| JPH05102524A (en) * | 1991-10-11 | 1993-04-23 | Oki Electric Ind Co Ltd | Semiconductor element |
| CN101710571A (en) * | 2009-12-14 | 2010-05-19 | 天水天光半导体有限责任公司 | Forward and reverse corrosion technology of Schottky diode metal structure |
| CN102915927A (en) * | 2012-10-11 | 2013-02-06 | 杭州立昂微电子股份有限公司 | Wet etching method for metal layer on front surface of high inverse-voltage Schottky diode |
-
2013
- 2013-11-29 CN CN201310635376.5A patent/CN103617952B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0519301B2 (en) * | 1988-12-08 | 1993-03-16 | Sanken Electric Co Ltd | |
| JPH05102524A (en) * | 1991-10-11 | 1993-04-23 | Oki Electric Ind Co Ltd | Semiconductor element |
| CN101710571A (en) * | 2009-12-14 | 2010-05-19 | 天水天光半导体有限责任公司 | Forward and reverse corrosion technology of Schottky diode metal structure |
| CN102915927A (en) * | 2012-10-11 | 2013-02-06 | 杭州立昂微电子股份有限公司 | Wet etching method for metal layer on front surface of high inverse-voltage Schottky diode |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103617952B (en) | 2016-08-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6354084B2 (en) | Etching solution, replenisher, and wiring formation method | |
| KR20000023524A (en) | Liquid crystal device, liquid crystal display panel and method for manufacturing the same | |
| CN104701411A (en) | Edge insulating method used during manufacturing of silicon-based heterojunction battery piece | |
| KR20120046055A (en) | Method of preparing pad for touch panel and pad for touch panel prepared thereby | |
| CN102026491A (en) | Manufacturing process of whole gold-plated panel | |
| CN102014580A (en) | Manufacturing technology of whole-plate gold-plated plate | |
| CN103617952A (en) | Diode wet etching method | |
| CN102865841B (en) | The Thickness sensitivity Detection of Stability method of crystal round fringes tolerance and testing tool | |
| CN103943528B (en) | Monitored off-line method for NDC thin film | |
| CN204302942U (en) | Electrostatic transducer | |
| JP6417556B2 (en) | Wiring forming method and etching solution | |
| CN102076175A (en) | Full gold-plated board manufacturing technology | |
| CN102522436B (en) | Silicon chip for testing bulk service life, silicon chip manufacturing method, and bulk service life test method | |
| CN103346102A (en) | Method for detecting preprocessing capacity | |
| CN206210758U (en) | It is a kind of to detect the abnormal device of plating side washing | |
| CN109860043A (en) | A kind of array substrate preparation method | |
| JP3085180B2 (en) | Field effect solar cell | |
| CN113130315A (en) | Thinning processing method of semiconductor | |
| CN105253854A (en) | Method for protecting metal electrode during SOI MEMS sacrificial layer etching | |
| CN103137510B (en) | A kind of method and monitoring module monitoring metal level over etching | |
| CN105448658B (en) | The method for cleaning wafer for preventing tungsten from corroding | |
| CN103972125A (en) | Method for monitoring and preventing spalling defect of connecting hole tungsten plug adhesive layer in advance | |
| US20130334168A1 (en) | Manufacturing method of circuit pattern | |
| CN115101412A (en) | Preparation method of TVS chip | |
| CN104103728B (en) | Prevent processing method and process equipment that light-emitting diode chip electrode comes off |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |